EP1366402A1 - Voltage regulator protected against short-circuits - Google Patents

Voltage regulator protected against short-circuits

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Publication number
EP1366402A1
EP1366402A1 EP02700338A EP02700338A EP1366402A1 EP 1366402 A1 EP1366402 A1 EP 1366402A1 EP 02700338 A EP02700338 A EP 02700338A EP 02700338 A EP02700338 A EP 02700338A EP 1366402 A1 EP1366402 A1 EP 1366402A1
Authority
EP
European Patent Office
Prior art keywords
potential
current
terminal
transistor
voltage regulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP02700338A
Other languages
German (de)
French (fr)
Other versions
EP1366402B1 (en
Inventor
Cécile HAMON
Christophe Bernard
Alexandre Pons
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
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Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of EP1366402A1 publication Critical patent/EP1366402A1/en
Application granted granted Critical
Publication of EP1366402B1 publication Critical patent/EP1366402B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
    • G05F1/573—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector

Definitions

  • the present invention relates to the field of voltage regulators and in particular that of regulators with low waste voltage.
  • a Low Drop Out regulator in the form of an integrated circuit can be used to supply a predetermined potential with low noise to a set of electronic circuits from a supply potential supplied by a rechargeable battery. .
  • a supply potential decreases over time, and is likely to include noise caused by the action of neighboring electromagnetic radiation on the battery / regulator links.
  • the regulator is said to have a low waste voltage because it provides a potential close to the supply potential.
  • Figure 1 schematically shows a conventional low voltage waste regulator.
  • the regulator has an output terminal O designed to be connected to a load R.
  • the essentially resistive load R represents the input impedance of all the circuits supplied by the regulator. For simplicity, it is subsequently considered that the load R is a resistance.
  • the regulator comprises an operational amplifier 2 whose inverting input E " is connected to a positive reference potential Vref and whose non-inverting input E + is connected to the output terminal O by a feedback loop.
  • the operational amplifier 2 is supplied between a positive supply potential Vbat supplied by the battery and a ground potential GND.
  • a power MOS transistor Tl with P channel, has its drain connected to the output terminal O and its source connected to the potential Vbat.
  • the gate of the transistor Tl is connected to the output terminal of the amplifier 2.
  • the transistor Tl is a MOS transistor, in particular to minimize, compared to the use of a bipolar transistor, the difference between the output potential Vout of terminal O and the supply potential Vbat.
  • a charge capacitor C is disposed between the output terminal O and the potential GND.
  • the voltage regulator comprises a short-circuit protection device intended to limit the consumption of the regulator by fixing the maximum current which can be supplied by the regulator.
  • the regulator comprises a device 4 for protection against short circuits.
  • the device 4 comprises a MOS transistor T2, with P channel, the source of which is connected to the potential Vbat and the gate of which is connected to the gate of the transistor T1.
  • the drain of the transistor T2 is connected to the drain and the gate of a MOS transistor 6, with channel ⁇ , the source of which is connected to the potential G ⁇ D.
  • a current source CS producing a current Iref is also connected to the drain of the transistor T2.
  • a MOS transistor 7, with channel ⁇ has its source connected to the potential GND and its gate connected to the gate of transistor 6.
  • the drain of transistor 7 is connected to potential Vbat via resistance RI.
  • a MOS transistor T3, with P channel has its source connected to the potential Vbat, its drain connected to the gate of the transistor Tl, and its gate connected to the drain of the transistor 7.
  • the current Irep passing through the transistor T2 depends on the current Iout passing through the transistor Tl because the sources of these transistors are connected and their gates receive the same signal.
  • the current passing through the transistor 6 is zero when the current Irep passing through the transistor T2 is less than the current Iref. No current then flows through transistor 7 and resistance RI, and the gate of transistor T3 has a potential equal to Vbat.
  • the current Irep is greater than Iref
  • the current 6 the transistor 7 and the resistor RI are crossed by a current equal to Irep - Iref.
  • the gate of transistor T3 then has a potential equal to Vbat - RI (Irep - Iref).
  • the transistors T2 and T3, the resistance RI and the current Iref are chosen so that, when the current Iout is less than a threshold value It, the transistor T3 is not conductive. If the current Iout exceeds the threshold value It, the transistor T3 becomes conductive and tends to bring the potential of the gate of the transistor Tl to the potential
  • Circuit 4 therefore makes it possible to limit the current in the load to the value It.
  • the current It must be greater than the nominal current which the regulator must supply.
  • a drawback of the device 4 is that when the regulator is energized, the capacitor C is charged with a current equal to the current It whatever the value of the resistance R. This high current charge has the effect of heating and damage capacitor C.
  • An object of the present invention is to provide a short circuit protection device which makes it possible to prevent the capacitor C from being crossed by a strong current when the regulator is energized.
  • the present invention provides a voltage regulator having an output terminal suitable for being connected to a load, comprising a device for limiting the current passing through the load to a first threshold current if the potential of the output terminal is less than a threshold potential, and a second threshold current higher than the first threshold current if the potential of the output terminal is greater than the threshold potential.
  • the limiting device comprises a comparator for comparing the potential of the output terminal with the threshold potential, first and second feedback loops adapted to limit the current passing through the load respectively to the first and second threshold currents, and a switching block controllable by the comparator to activate either the first or the second feedback loop depending on whether the potential of the output terminal is lower or not than the threshold potential.
  • the switch block is capable of supplying a current dependent on the current passing through the load on a first or on a second output
  • each feedback loop connected to an output of the block of switch, comprises a control block suitable for supplying a control signal when it receives from the switch block a current greater than a reference current, and further comprises a blocking means which receives the output of the control blocks and which decreases the current flowing through the load when any of the first and second control signals are active.
  • the voltage regulator comprises a power switch arranged so as to connect the output terminal to a first supply potential, and a first operational amplifier whose inverting and non-inverting inputs are respectively connected at the reference potential and at the output terminal, a control terminal of the power switch being connected to the output of the first operational amplifier and the device for limiting the current passing through the load being connected to the control terminal of the power switch, the load comprising a capacitor and a first impedance connected in parallel between the output terminal and a second feeding potential.
  • the switching block comprises a first MOS transistor of a first type having its source connected to the first supply potential and its gate connected to the control terminal of the power switch, and second and third MOS transistors of the first type having their sources connected to the drain of the first transistor, the drains of the second and third transistors respectively constituting the first and second outputs of the switching block.
  • the comparator comprises fourth and fifth MOS transistors of a second type, the drains of which are connected to the first supply potential, the gates of which are respectively connected to the threshold potential and to the terminal. output, the sources of the fourth and fifth transistors being respectively connected to the gates of the second and third transistors, as well as to the second supply potential via first and second current sources.
  • the control block of each feedback loop comprises a pair of MOS transistors of the second type, the sources of which are connected to the second supply potential, the gates of which are connected to each other.
  • the blocking means which receives the output of the control blocks comprises a resistor of which a first terminal is connected to the first supply potential and of which a second terminal is arranged so as to receive the sum control signals supplied by the control blocks, and a sixth MOS transistor of the first type whose source is connected to the first supply potential, whose drain is connected to the control terminal of the power switch, and whose gate is connected to the second terminal of the resistor.
  • the blocking means which receives the output of the control blocks comprises a second impedance, a first terminal of which is connected to the first supply potential and a second terminal of which is arranged so as to receive the sum of the control signals supplied by the control blocks, a third impedance, paired with the second impedance, a first terminal of which is connected to the first supply potential and a second terminal of which receives a predetermined constant current, a second operational amplifier whose non-inverting and inverting inputs are respectively connected to the second terminal of the second and third impedances, and a seventh MOS transistor of the first type whose source is connected to the first supply potential, whose drain is connected to the control terminal of the switch power, and the grid of which is connected to the output of the second operator amplifier ional.
  • the first supply potential, the reference potential and the threshold potential are positive potentials of decreasing values
  • the second supply potential is a ground potential
  • the power switch and the transistors of the first type are P-channel MOS transistors
  • the transistors of the second type are N-channel MOS transistors
  • FIG. 1 previously described, schematically represents a voltage regulator provided with a conventional device for protection against short- circuits;
  • FIG. 2 schematically represents a voltage regulator comprising a current limiting device according to the present invention;
  • Figure 3 schematically shows a first embodiment of the voltage regulator of Figure 2;
  • FIG. 4 represents an exemplary embodiment of the voltage regulator of FIG. 3;
  • FIG. 5 schematically represents a second embodiment of the voltage regulator of FIG. 2.
  • FIG. 2 schematically represents a voltage regulator whose output terminal O is connected to a load R, and which comprises the operational amplifier 2, the transistor Tl and the charge capacitor C of the conventional regulator described above.
  • the regulator comprises a device 8 for limiting the current, a first input terminal of which is connected to the output terminal O and a second input terminal of which is connected to a threshold potential Vt.
  • the device 8 is also connected to the gate of the transistor Tl.
  • the device 8 compares the potential Vout of terminal O with the potential Vt.
  • the potential Vt is chosen lower than the potential Vref.
  • the current Iout is limited to a first or to a second threshold current Itl low or strong It2.
  • the capacitor C is charged by the current Itl until the potential Vout reaches the value Vt.
  • the current Itl is low so as not to damage the capacitor C.
  • the potential Vout becomes greater than the potential Vt
  • the current passing through the transistor Tl becomes equal to It2 while capacitor C is not fully charged. The charging of the capacitor C ends with the current It2.
  • the current Iout is limited to the current It2.
  • FIG. 3 schematically represents a first embodiment of the voltage regulator of FIG. 2.
  • the device 8 comprises a MOS transistor T2 with P channel, the source of which is connected to the potential Vbat and the gate of which is connected to the gate of the transistor Tl.
  • the transistor T2 is arranged so as to be traversed by a current Irep depending on the output current Iout.
  • the drain of transistor T2 is connected to an input terminal of a switching means 10.
  • a voltage comparator 12 has a first input terminal connected to the output terminal O, a second input terminal connected to a threshold potential Vt, and is provided for controlling the switching means 10.
  • a first output terminal of the switching means 10 is connected to an input terminal of a control means 14 which controls a switch 16 and a second output terminal of the switching means 10 is connected to an input terminal of a control means 20 which controls a switch 22.
  • a MOS transistor T3, with P channel, has its source connected to the potential Vbat and its drain connected to the gate of transistor Tl.
  • the gate of transistor T3 is coupled to a node G3.
  • the node G3 is connected to the potential Vbat via a resistor RI.
  • the knot G3 is connected to the GND potential via switches 22 and 16, in parallel.
  • the voltage comparator 12 controls the switching means 10 so that the current Irep is supplied either to the control means 14 or to the control means 20, depending on whether the potential Vout is lower or higher than the potential Vt.
  • the current Irep is supplied to the control means 14.
  • the control means 14 is provided to keep the switch 16 open or closed depending on whether the current Irep, received on its terminal d 'input, is lower or higher than a reference current Irefl.
  • the switch 16 is closed and a current flows through the resistor RI.
  • the potential of the node G3 drops, the transistor T3 becomes conducting and decreases the conduction of the transistors Tl and T2 until the current Irep becomes lower than the current Irefl.
  • the circuit acts as a current limiter limiting the current Irep to the value Irefl.
  • the current Iout is therefore limited to a current Itl depending on the current Irefl.
  • the switching means 10 is controlled by the voltage comparator 12 so that the current Irep is supplied to the input terminal of the control means 20.
  • the means of control 20, of the same structure as the control means 14, is provided to keep the switch 22 open or closed depending on whether the current received on its input terminal is less than or greater than a reference current Iref2.
  • the current Iout supplied by the voltage regulator is then limited to a value It2 depending on the current Iref2.
  • FIG. 4 represents an exemplary embodiment of the voltage regulator of FIG. 3.
  • the voltage comparator 12 comprises two MOS transistors T4 and T5, with channel ⁇ , whose drains are connected to the potential Vbat and whose sources are respectively connected to the GND potential through current sources CS4 and CS5.
  • the gates of the transistors T5 and T4 constitute the first and second inputs of the comparator 12.
  • the switching means 10 comprises two MOS transistors T6 and T7, with P channel, the sources of which are connected to the drain of the transistor T2 and the gates of which are respectively connected to the sources of transistors T4 and T5.
  • the transistors T4 and T5 form a differential pair.
  • the drains of the transistors T7 and T6 respectively constitute the first and second output terminals of the switching means 10.
  • the control means 14 comprises an N-channel MOS transistor whose source is connected to the potential GND, and whose drain and grid are connected to one another as well as to a current source producing the current Irefl.
  • the drain and the gate of the transistor of the control means 14 constitute the input terminal of the control means 14.
  • the switch 16 is an N-channel MOS transistor connected in current mirror with the transistor of the control means 14.
  • the source of transistor 16 is connected to potential GND and the drain of transistor 16 is connected to node G3.
  • the control means 20 comprises an N-channel MOS transistor whose source is connected to the potential GND and whose drain and gate are connected to one another as well as to a current source producing the current Iref2.
  • the drain and the gate of the transistor of the control means 20 constitute the input terminal of the control means 20.
  • the switch 22 is an N-channel MOS transistor connected in current mirror with the transistor of the control means 20.
  • the source of transistor 22 is connected to potential GND and the drain of transistor 22 is connected to node G3.
  • the potential of the source of transistor T5 is less than the potential of the source of transistor T4.
  • the potential of the gate of transistor T7 is less than the potential of the gate of transistor T6.
  • the transistor T7 is then more conductive than the transistor T6.
  • the transistors T4, T5, T6 and T7 are chosen so that the current Irep then passes only through the transistor T7 and not the transistor T6.
  • the drain of transistor of the control means 14 then receives the current Irep. As long as the current Irep is less than the current Irefl, the transistors 14 and 16 are not crossed by any current.
  • the current Irep passes through the transistor T6 and not the transistor T7.
  • the operation of the control means 20 and of the switch 22 is then similar to the operation of the control means 14 and of the switch 16 which has just been exposed and the current Iout is limited to a value It2.
  • FIG. 5 schematically represents a second embodiment of the voltage regulator of FIG. 2.
  • the device 8 comprises the P channel T2 MOS transistor, the voltage comparator 12, the switching means 10, the switches 16 and 22 and the control means 14 and 20 of the device 8 described above.
  • a MOS transistor T3 ′ with P channel, has its source connected to the potential Vbat and its drain connected to the gate of the transistor Tl.
  • the gate of transistor T3 ' is connected to the output of an operational amplifier 26 supplied between the potentials Vbat and GND.
  • the non-inverting E + and inverting E ⁇ inputs of the amplifier 26 are connected to the potential Vbat by means of impedances Z1 and Z2 respectively.
  • the impedances Zl and Z2 are equal and matched, so that any variation in the value of Zl, for example following a variation in temperature or in the manufacturing process, corresponds to an equal variation in Z2.
  • the inverting input of the amplifier 26 is also connected to the potential GND via a current source producing a predetermined constant current 12.
  • the non-inverting input of amplifier 26 is connected to GND potential via switches 16 and 22, in parallel.
  • the control of the transistor T3 by the amplifier 26 depends on the ratio of the potential drops in the impedances Z1 and Z2.
  • the impedances Zl and Z2 being equal and matched, it follows that the control of the transistor T3 'is independent of the values of the impedances Zl and Z2 and depends only on the ratio between the currents crossing the impedances Zl and Z2.
  • the current 12 passing through the impedance Z2 is constant.
  • the current passing through the impedance Zl is comparable to the current passing through the resistance RI of FIG. 3.
  • the current Iout thus depends on Irefl or Iref2 depending on whether the potential Vout is lower or higher than the potential Vt.
  • the control of the transistor T3 being independent of the values Zl and Z2, the current Iout is independent of the variations of the impedances Zl and Z2, which constitutes an additional advantage of the present invention.
  • the gain of the amplifier 26 can be chosen to be high so that the control of the transistor T3 'is not very sensitive to a drift in the threshold voltage of the transistor T3', which constitutes another advantage of the present invention.
  • the present invention has been described in relation to a voltage regulator using positive Vbat, Vref and Vt potentials, but a person skilled in the art will easily adapt the present invention to a voltage regulator using negative potentials by inverting the types of the transistors. MOS described.
  • the present invention has for reasons of simplicity been described in relation to a voltage regulator using a non-resistive feedback loop and providing a potential equal to a reference potential Vref received. However, a person skilled in the art will easily adapt the present invention to a voltage regulator, the feedback loop of which comprises a resistive bridge, and which provides an output potential different from the potential Vref received.
  • the present invention has been described in relation to a voltage regulator using a power transistor T1, but a person skilled in the art will easily adapt the present invention to a voltage regulator using another type of voltage-controlled power switch.

Abstract

The invention concerns a voltage regulator having an output terminal (O) adapted to be connected to a load (R, C), comprising a device (1) limiting the current (Iout) passing through the load to a threshold current (It1) if the output terminal potential (Vout) is lower than a threshold potential (Vt), and to a second threshold current (It2) is higher than the first threshold current if the output terminal potential (Vout) is higher than the threshold potential (Vt).

Description

REGULATEUR DE TENSION PROTEGE CONTRE LES COURTS-CIRCUITS VOLTAGE REGULATOR PROTECTED AGAINST SHORT CIRCUITS
La présente invention concerne le domaine des régulateurs de tension et en particulier celui des régulateurs à faible tension de déchet.The present invention relates to the field of voltage regulators and in particular that of regulators with low waste voltage.
Un régulateur à faible tension de déchet (Low Drop Out) réalisé sous forme de circuit intégré peut être utilisé pour fournir un potentiel prédéterminé avec un faible bruit à un ensemble de circuits électroniques à partir d'un potentiel d'alimentation fourni par une pile rechargeable. Un tel potentiel d'alimentation décroît avec le temps, et est susceptible de comporter du bruit causé par l'action de radiations électromagnétiques voisines sur les liaisons pile/régulateur. Le régulateur est dit à faible tension de déchet car il permet de fournir un potentiel proche du potentiel d' alimentation. La figure 1 représente schématiquement un régulateur à faible tension de déchet classique. Le régulateur comporte une borne de sortie O prévue pour être reliée à une charge R. La charge R, essentiellement résistive, représente l'impédance d'entrée de l'ensemble des circuits alimentés par le régulateur. Par simplicité, on considère par la suite que la charge R est une résistance. Le régulateur comprend un amplificateur opérationnel 2 dont l'entrée inverseuse E" est reliée à un potentiel de référence positif Vref et dont l'entrée non- inverseuse E+ est reliée à la borne de sortie O par une boucle de contre réaction. L'amplificateur opérationnel 2 est alimenté entre un potentiel d'alimentation Vbat positif fourni par la pile et un potentiel de masse GND. Un transistor MOS de puissance Tl, à canal P, a son drain relié à la borne de sortie O et sa source reliée au potentiel Vbat. La grille du transistor Tl est reliée à la borne de sortie de 1 ' amplificateur 2. Le transistor Tl est un transistor MOS, notamment pour minimiser, par rapport à l'emploi d'un transistor bipolaire, la différence entre le potentiel de sortie Vout de la borne O et le potentiel d'alimentation Vbat. Un condensateur de charge C est disposé entre la borne de sortie O et le potentiel GND.A Low Drop Out regulator in the form of an integrated circuit can be used to supply a predetermined potential with low noise to a set of electronic circuits from a supply potential supplied by a rechargeable battery. . Such a supply potential decreases over time, and is likely to include noise caused by the action of neighboring electromagnetic radiation on the battery / regulator links. The regulator is said to have a low waste voltage because it provides a potential close to the supply potential. Figure 1 schematically shows a conventional low voltage waste regulator. The regulator has an output terminal O designed to be connected to a load R. The essentially resistive load R represents the input impedance of all the circuits supplied by the regulator. For simplicity, it is subsequently considered that the load R is a resistance. The regulator comprises an operational amplifier 2 whose inverting input E " is connected to a positive reference potential Vref and whose non-inverting input E + is connected to the output terminal O by a feedback loop. The operational amplifier 2 is supplied between a positive supply potential Vbat supplied by the battery and a ground potential GND. A power MOS transistor Tl, with P channel, has its drain connected to the output terminal O and its source connected to the potential Vbat. The gate of the transistor Tl is connected to the output terminal of the amplifier 2. The transistor Tl is a MOS transistor, in particular to minimize, compared to the use of a bipolar transistor, the difference between the output potential Vout of terminal O and the supply potential Vbat. A charge capacitor C is disposed between the output terminal O and the potential GND.
Le régulateur maintient le potentiel de la borne de sortie O à une valeur égale au potentiel de référence Vref. Toute variation du potentiel Vbat se traduit par une variation du potentiel Vout, qui est transmise par la boucle de contre réaction sur la borne E~ . Toute variation de la charge R se traduit par une variation du courant Iout fourni par le régulateur à la charge. Lorsque la charge R diminue, le courant Iout augmente. De manière classique, le régulateur de tension comporte un dispositif de protection contre les courts-circuits destiné à limiter la consommation du régulateur en fixant le courant maximal qui peut être fourni par le régulateur. Le régulateur comporte un dispositif 4 de protection contre les courts-circuits. Le dispositif 4 comporte un transistor MOS T2, à canal P, dont la source est reliée au potentiel Vbat et dont la grille est reliée à la grille du transistor Tl. Le drain du transistor T2 est relié au drain et à la grille d'un transistor MOS 6, à canal Ν, dont la source est reliée au potentiel GΝD. Une source de courant CS produisant un courant Iref est également reliée au drain du transistor T2. Un transistor MOS 7, à canal Ν, a sa source reliée au potentiel GND et sa grille reliée à la grille du transistor 6. Le drain du transistor 7 est relié au potentiel Vbat par l'intermédiaire d'une résistance RI. Un transistor MOS T3, à canal P, a sa source reliée au potentiel Vbat, son drain relié à la grille du transistor Tl, et sa grille reliée au drain du transistor 7.The regulator maintains the potential of the output terminal O at a value equal to the reference potential Vref. Any variation of the potential Vbat results in a variation of the potential Vout, which is transmitted by the feedback loop on the terminal E ~ . Any variation in the load R results in a variation in the current Iout supplied by the regulator to the load. When the load R decreases, the current Iout increases. Conventionally, the voltage regulator comprises a short-circuit protection device intended to limit the consumption of the regulator by fixing the maximum current which can be supplied by the regulator. The regulator comprises a device 4 for protection against short circuits. The device 4 comprises a MOS transistor T2, with P channel, the source of which is connected to the potential Vbat and the gate of which is connected to the gate of the transistor T1. The drain of the transistor T2 is connected to the drain and the gate of a MOS transistor 6, with channel Ν, the source of which is connected to the potential GΝD. A current source CS producing a current Iref is also connected to the drain of the transistor T2. A MOS transistor 7, with channel Ν, has its source connected to the potential GND and its gate connected to the gate of transistor 6. The drain of transistor 7 is connected to potential Vbat via resistance RI. A MOS transistor T3, with P channel, has its source connected to the potential Vbat, its drain connected to the gate of the transistor Tl, and its gate connected to the drain of the transistor 7.
Le courant Irep traversant le transistor T2 dépend du courant Iout traversant le transistor Tl du fait que les sources de ces transistors sont connectées et que leurs grilles reçoivent un même signal. Le courant traversant le transistor 6 est nul quand le courant Irep traversant le transistor T2 est inférieur au courant Iref. Aucun courant ne traverse alors le transistor 7 et la résistance RI, et la grille du transistor T3 a un potentiel égal à Vbat. Lorsque le courant Irep est supérieur à Iref, le transistor 6, le transistor 7 et la résistance RI sont traversés par un courant égal à Irep - Iref. La grille du transistor T3 a alors un potentiel égal à Vbat - RI (Irep - Iref). Les transistors T2 et T3, la résistance RI et le courant Iref sont choisis de telle manière que, lorsque le courant Iout est inférieur à une valeur seuil It, le transistor T3 n'est pas conducteur. Si le courant Iout dépasse la valeur seuil It, le transistor T3 devient conducteur et tend à amener le potentiel de la grille du transistor Tl au potentielThe current Irep passing through the transistor T2 depends on the current Iout passing through the transistor Tl because the sources of these transistors are connected and their gates receive the same signal. The current passing through the transistor 6 is zero when the current Irep passing through the transistor T2 is less than the current Iref. No current then flows through transistor 7 and resistance RI, and the gate of transistor T3 has a potential equal to Vbat. When the current Irep is greater than Iref, the current 6, the transistor 7 and the resistor RI are crossed by a current equal to Irep - Iref. The gate of transistor T3 then has a potential equal to Vbat - RI (Irep - Iref). The transistors T2 and T3, the resistance RI and the current Iref are chosen so that, when the current Iout is less than a threshold value It, the transistor T3 is not conductive. If the current Iout exceeds the threshold value It, the transistor T3 becomes conductive and tends to bring the potential of the gate of the transistor Tl to the potential
Vbat. Le transistor Tl devient alors moins conducteur et le courant Iout revient vers la valeur limite It. Le circuit 4 permet donc de limiter le courant dans la charge à la valeur It. Le courant It doit être supérieur au courant nominal que le régulateur doit fournir.Vbat. The transistor Tl then becomes less conductive and the current Iout returns to the limit value It. Circuit 4 therefore makes it possible to limit the current in the load to the value It. The current It must be greater than the nominal current which the regulator must supply.
Un inconvénient du dispositif 4 est qu'à la mise sous tension du régulateur, le condensateur C est chargé avec un courant égal au courant It quelle que soit la valeur de la résistance R. Cette charge à fort courant a pour effet d'échauffer et de détériorer le condensateur C.A drawback of the device 4 is that when the regulator is energized, the capacitor C is charged with a current equal to the current It whatever the value of the resistance R. This high current charge has the effect of heating and damage capacitor C.
Un objet de la présente invention est de prévoir un dispositif de protection contre les courts circuits qui permette d'éviter que le condensateur C soit traversé par un fort courant à la mise sous tension du régulateur. Pour atteindre cet objet, la présente invention prévoit un régulateur de tension ayant une borne de sortie propre à être reliée à une charge, comportant un dispositif de limitation du courant traversant la charge à un premier courant de seuil si le potentiel de la borne de sortie est inférieur à un potentiel de seuil, et à un second courant de seuil plus élevé que le premier courant de seuil si le potentiel de la borne de sortie est supérieur au potentiel de seuil.An object of the present invention is to provide a short circuit protection device which makes it possible to prevent the capacitor C from being crossed by a strong current when the regulator is energized. To achieve this object, the present invention provides a voltage regulator having an output terminal suitable for being connected to a load, comprising a device for limiting the current passing through the load to a first threshold current if the potential of the output terminal is less than a threshold potential, and a second threshold current higher than the first threshold current if the potential of the output terminal is greater than the threshold potential.
Selon un mode de réalisation de la présente invention, le dispositif de limitation comporte un comparateur pour comparer le potentiel de la borne de sortie au potentiel de seuil, des première et seconde boucles de réaction propres à limiter le courant traversant la charge respectivement aux premier et second courants de seuil, et un bloc d'aiguillage commandable par le comparateur pour activer soit la première soit la seconde boucle de réaction selon que le potentiel de la borne de sortie est inférieur ou non au potentiel de seuil.According to an embodiment of the present invention, the limiting device comprises a comparator for comparing the potential of the output terminal with the threshold potential, first and second feedback loops adapted to limit the current passing through the load respectively to the first and second threshold currents, and a switching block controllable by the comparator to activate either the first or the second feedback loop depending on whether the potential of the output terminal is lower or not than the threshold potential.
Selon un mode de réalisation de la présente invention, le bloc d'aiguillage est propre à fournir un courant dépendant du courant traversant la charge sur une première ou sur une seconde sortie, et chaque boucle de réaction, reliée à une sortie du bloc d'aiguillage, comporte un bloc de commande propre à fournir un signal de commande lorsqu'il reçoit du bloc d'aiguillage un courant supérieur à un courant de référence, et comporte en outre un moyen de blocage qui reçoit la sortie des blocs de commande et qui fait décroître le courant traversant la charge lorsque l'un quelconque des premier et second signaux de commande est actif.According to an embodiment of the present invention, the switch block is capable of supplying a current dependent on the current passing through the load on a first or on a second output, and each feedback loop, connected to an output of the block of switch, comprises a control block suitable for supplying a control signal when it receives from the switch block a current greater than a reference current, and further comprises a blocking means which receives the output of the control blocks and which decreases the current flowing through the load when any of the first and second control signals are active.
Selon un mode de réalisation de la présente invention le régulateur de tension comporte un commutateur de puissance disposé de manière à relier la borne de sortie à un premier potentiel d'alimentation, et un premier amplificateur opérationnel dont les entrées inverseuse et non inverseuse sont respectivement reliées au potentiel de référence et à la borne de sortie, une borne de commande du commutateur de puissance étant reliée à la sortie du premier amplificateur opérationnel et le dispositif de limitation du courant traversant la charge étant relié à la borne de commande du commutateur de puissance, la charge comportant un condensateur et une première impédance reliés en parallèle entre la borne de sortie et un second potentiel d'alimentation.According to an embodiment of the present invention, the voltage regulator comprises a power switch arranged so as to connect the output terminal to a first supply potential, and a first operational amplifier whose inverting and non-inverting inputs are respectively connected at the reference potential and at the output terminal, a control terminal of the power switch being connected to the output of the first operational amplifier and the device for limiting the current passing through the load being connected to the control terminal of the power switch, the load comprising a capacitor and a first impedance connected in parallel between the output terminal and a second feeding potential.
Selon un mode de réalisation de la présente invention, le bloc d'aiguillage comporte un premier transistor MOS d'un premier type ayant sa source reliée au premier potentiel d'alimentation et sa grille reliée à la borne de commande du commutateur de puissance, et des deuxième et troisième transistors MOS du premier type ayant leurs sources reliées au drain du premier transistor, les drains des deuxième et troisième transistors constituant respectivement les première et seconde sorties du bloc d'aiguillage.According to one embodiment of the present invention, the switching block comprises a first MOS transistor of a first type having its source connected to the first supply potential and its gate connected to the control terminal of the power switch, and second and third MOS transistors of the first type having their sources connected to the drain of the first transistor, the drains of the second and third transistors respectively constituting the first and second outputs of the switching block.
Selon un mode de réalisation de la présente invention, le comparateur comprend des quatrième et cinquième transistors MOS d'un second type dont les drains sont reliés au premier potentiel d'alimentation, dont les grilles sont respectivement reliées au potentiel de seuil et à la borne de sortie, les sources des quatrième et cinquième transistors étant respectivement reliées aux grilles des deuxième et troisième transistors, ainsi qu'au second potentiel d'alimentation par l'intermédiaire de première et deuxième sources de courant. Selon un mode de réalisation de la présente invention, le bloc de commande de chaque boucle de réaction comporte un couple de transistors MOS du second type dont les sources sont reliées au second potentiel d'alimentation, dont les grilles sont reliées l'une à l'autre ainsi qu'à une source de courant produisant un courant de référence, le drain et la grille d'un premier transistor du couple de transistors étant reliés l'un à l'autre ainsi qu'à l'une des sorties du bloc d'aiguillage, le courant traversant le second transistor du couple de transistors correspondant au signal de commande fourni par le bloc de commande . Selon un mode de réalisation de la présente invention, le moyen de blocage qui reçoit la sortie des blocs de commande comprend une résistance dont une première borne est reliée au premier potentiel d'alimentation et dont une seconde borne est disposée de manière à recevoir la somme des signaux de commande fournis par les blocs de commande, et un sixième transistor MOS du premier type dont la source est reliée au premier potentiel d'alimentation, dont le drain est relié à la borne de commande du commutateur de puissance, et dont la grille est reliée à la seconde borne de la résistance.According to an embodiment of the present invention, the comparator comprises fourth and fifth MOS transistors of a second type, the drains of which are connected to the first supply potential, the gates of which are respectively connected to the threshold potential and to the terminal. output, the sources of the fourth and fifth transistors being respectively connected to the gates of the second and third transistors, as well as to the second supply potential via first and second current sources. According to an embodiment of the present invention, the control block of each feedback loop comprises a pair of MOS transistors of the second type, the sources of which are connected to the second supply potential, the gates of which are connected to each other. other as well as a current source producing a reference current, the drain and the gate of a first transistor of the pair of transistors being connected to each other as well as to one of the outputs of the block switch, the current passing through the second transistor of the pair of transistors corresponding to the control signal supplied by the control block. According to an embodiment of the present invention, the blocking means which receives the output of the control blocks comprises a resistor of which a first terminal is connected to the first supply potential and of which a second terminal is arranged so as to receive the sum control signals supplied by the control blocks, and a sixth MOS transistor of the first type whose source is connected to the first supply potential, whose drain is connected to the control terminal of the power switch, and whose gate is connected to the second terminal of the resistor.
Selon un mode de réalisation de la présente invention, le moyen de blocage qui reçoit la sortie des blocs de commande comprend une seconde impédance dont une première borne est reliée au premier potentiel d'alimentation et dont une seconde borne est disposée de manière à recevoir la somme des signaux de commande fournis par les blocs de commande, une troisième impédance, appariée à la seconde impédance dont une première borne est reliée au premier potentiel d'alimentation et dont une seconde borne reçoit un courant constant prédéterminé, un second amplificateur opérationnel dont les entrées non inverseuse et inverseuse sont respectivement reliées à la seconde borne des seconde et troisième impédances, et un septième transistor MOS du premier type dont la source est reliée au premier potentiel d'alimentation, dont le drain est relié à la borne de commande du commutateur de puissance, et dont la grille est reliée à la sortie du second amplificateur opérationnel.According to an embodiment of the present invention, the blocking means which receives the output of the control blocks comprises a second impedance, a first terminal of which is connected to the first supply potential and a second terminal of which is arranged so as to receive the sum of the control signals supplied by the control blocks, a third impedance, paired with the second impedance, a first terminal of which is connected to the first supply potential and a second terminal of which receives a predetermined constant current, a second operational amplifier whose non-inverting and inverting inputs are respectively connected to the second terminal of the second and third impedances, and a seventh MOS transistor of the first type whose source is connected to the first supply potential, whose drain is connected to the control terminal of the switch power, and the grid of which is connected to the output of the second operator amplifier ional.
Selon un mode de réalisation de la présente invention, le premier potentiel d'alimentation, le potentiel de référence et le potentiel de seuil sont des potentiels positifs de valeurs décroissantes, le second potentiel d'alimentation est un potentiel de masse, le commutateur de puissance et les transistors du premier type sont des transistors MOS à canal P, et les transistors du second type sont des transistors MOS à canal N.According to an embodiment of the present invention, the first supply potential, the reference potential and the threshold potential are positive potentials of decreasing values, the second supply potential is a ground potential, the power switch and the transistors of the first type are P-channel MOS transistors, and the transistors of the second type are N-channel MOS transistors
Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles : la figure 1, précédemment décrite, représente schéma- tiquement un régulateur de tension muni d'un dispositif classique de protection contre les courts-circuits ; la figure 2 représente schématiquement un régulateur de tension comprenant un dispositif de limitation de courant selon la présente invention ; la figure 3 représente schématiquement un premier mode de réalisation du régulateur de tension de la figure 2 ; la figure 4 représente un exemple de réalisation du régulateur de tension de la figure 3 ; et la figure 5 représente schématiquement un second mode de réalisation du régulateur de tension de la figure 2.These and other objects, features and advantages of the present invention will be discussed in detail in the following description of particular embodiments given without limitation in relation to the appended figures among which: FIG. 1, previously described, schematically represents a voltage regulator provided with a conventional device for protection against short- circuits; FIG. 2 schematically represents a voltage regulator comprising a current limiting device according to the present invention; Figure 3 schematically shows a first embodiment of the voltage regulator of Figure 2; FIG. 4 represents an exemplary embodiment of the voltage regulator of FIG. 3; and FIG. 5 schematically represents a second embodiment of the voltage regulator of FIG. 2.
La figure 2 représente schématiquement un régulateur de tension dont la borne de sortie O est reliée à une charge R, et qui comporte l'amplificateur opérationnel 2, le transistor Tl et le condensateur de charge C du régulateur classique décrit précédemment. Selon la présente invention, le régulateur comporte un dispositif 8 de limitation de courant dont une première borne d'entrée est reliée à la borne de sortie O et dont une seconde borne d'entrée est reliée à un potentiel de seuil Vt. Le dispositif 8 est en outre relié à la grille du transistor Tl.FIG. 2 schematically represents a voltage regulator whose output terminal O is connected to a load R, and which comprises the operational amplifier 2, the transistor Tl and the charge capacitor C of the conventional regulator described above. According to the present invention, the regulator comprises a device 8 for limiting the current, a first input terminal of which is connected to the output terminal O and a second input terminal of which is connected to a threshold potential Vt. The device 8 is also connected to the gate of the transistor Tl.
Le dispositif 8 compare le potentiel Vout de la borne O au potentiel Vt. Le potentiel Vt est choisi inférieur au potentiel Vref. Selon que Vout est inférieur ou supérieur à Vt, le courant Iout est limité à un premier ou à un second courant de seuil faible Itl ou fort It2. A la mise sous tension du régulateur, le condensateur C est chargé par le courant Itl jusqu'à ce que le potentiel Vout atteigne la valeur Vt. Le courant Itl est faible pour ne pas détériorer le condensateur C. Lorsque le potentiel Vout devient supérieur au potentiel Vt, le courant traversant le transistor Tl devient égal à It2 alors que le condensateur C n'est pas complètement chargé. La fin de la charge du condensateur C se fait avec le courant It2. Après la mise sous tension du régulateur, si la charge R devient faible sans que le potentiel Vout chute en deçà du potentiel Vt, par exemple en cas de court-circuit limité de la charge R, le courant Iout est limité au courant It2. Le courant fourni par le régulateur est alors sensiblement égal au courant fourni par un régulateur muni d'un dispositif de protection classique si It2 = It. Si la charge R devient très faible et que le potentiel Vout chute en deçà du potentiel Vt, par exemple en cas de court- circuit franc, le courant traversant le transistor Tl est limité au courant Itl. Le courant fourni par le régulateur est alors inférieur au courant fourni par un régulateur muni d'un dispositif de protection classique, ce qui représente un avantage supplémentaire de la présente invention.The device 8 compares the potential Vout of terminal O with the potential Vt. The potential Vt is chosen lower than the potential Vref. Depending on whether Vout is less than or greater than Vt, the current Iout is limited to a first or to a second threshold current Itl low or strong It2. When the regulator is energized, the capacitor C is charged by the current Itl until the potential Vout reaches the value Vt. The current Itl is low so as not to damage the capacitor C. When the potential Vout becomes greater than the potential Vt, the current passing through the transistor Tl becomes equal to It2 while capacitor C is not fully charged. The charging of the capacitor C ends with the current It2. After the regulator is energized, if the load R becomes low without the potential Vout falling below the potential Vt, for example in the event of a limited short circuit of the load R, the current Iout is limited to the current It2. The current supplied by the regulator is then substantially equal to the current supplied by a regulator provided with a conventional protection device if It2 = It. If the load R becomes very low and the potential Vout drops below the potential Vt, for example in the event of a short-circuit, the current passing through the transistor Tl is limited to the current Itl. The current supplied by the regulator is then lower than the current supplied by a regulator provided with a conventional protection device, which represents an additional advantage of the present invention.
La figure 3 représente schématiquement un premier mode de réalisation du régulateur de tension de la figure 2. Le dispositif 8 comprend un transistor MOS T2 à canal P, dont la source est reliée au potentiel Vbat et dont la grille est reliée à la grille du transistor Tl. Le transistor T2 est disposé de manière à être traversé par un courant Irep dépendant du courant de sortie Iout. Le drain du transistor T2 est relié à une borne d'entrée d'un moyen d'aiguillage 10. Un comparateur de tension 12 a une première borne d'entrée reliée à la borne de sortie O, une deuxième borne d'entrée reliée à un potentiel de seuil Vt, et est prévu pour commander le moyen d'aiguillage 10. Une première borne de sortie du moyen d'aiguillage 10 est reliée à une borne d'entrée d'un moyen de commande 14 qui commande un commutateur 16 et une seconde borne de sortie du moyen d'aiguillage 10 est reliée à une borne d'entrée d'un moyen de commande 20 qui commande un commutateur 22. Un transistor MOS T3, à canal P, a sa source reliée au potentiel Vbat et son drain relié à la grille du transistor Tl. La grille du transistor T3 est couplée à un noeud G3. Le noeud G3 est relié au potentiel Vbat par l'intermédiaire d'une résistance RI. En outre, le noeud G3 est relié au potentiel GND par l'intermédiaire des commutateurs 22 et 16, en parallèle.FIG. 3 schematically represents a first embodiment of the voltage regulator of FIG. 2. The device 8 comprises a MOS transistor T2 with P channel, the source of which is connected to the potential Vbat and the gate of which is connected to the gate of the transistor Tl. The transistor T2 is arranged so as to be traversed by a current Irep depending on the output current Iout. The drain of transistor T2 is connected to an input terminal of a switching means 10. A voltage comparator 12 has a first input terminal connected to the output terminal O, a second input terminal connected to a threshold potential Vt, and is provided for controlling the switching means 10. A first output terminal of the switching means 10 is connected to an input terminal of a control means 14 which controls a switch 16 and a second output terminal of the switching means 10 is connected to an input terminal of a control means 20 which controls a switch 22. A MOS transistor T3, with P channel, has its source connected to the potential Vbat and its drain connected to the gate of transistor Tl. The gate of transistor T3 is coupled to a node G3. The node G3 is connected to the potential Vbat via a resistor RI. In addition, the knot G3 is connected to the GND potential via switches 22 and 16, in parallel.
Le comparateur de tension 12 commande le moyen d'aiguillage 10 de manière que le courant Irep soit fourni soit au moyen de commande 14 soit au moyen de commande 20, selon que le potentiel Vout est inférieur ou supérieur au potentiel Vt.The voltage comparator 12 controls the switching means 10 so that the current Irep is supplied either to the control means 14 or to the control means 20, depending on whether the potential Vout is lower or higher than the potential Vt.
Dans le cas où le potentiel Vout est inférieur au potentiel Vt, le courant Irep est fourni au moyen de commande 14. Le moyen de commande 14 est prévu pour maintenir le commutateur 16 ouvert ou fermé selon que le courant Irep, reçu sur sa borne d'entrée, est inférieur ou supérieur à un courant de référence Irefl. Quand le courant Irep devient supérieur au courant Irefl, le commutateur 16 est fermé et un courant circule dans la résistance RI. Le potentiel du noeud G3 chute, le transistor T3 devient passant et fait décroître la conduction des transistors Tl et T2 jusqu'à ce que le courant Irep devienne inférieur au courant Irefl. Le circuit agit comme un limiteur de courant limitant le courant Irep à la valeur Irefl. Le courant Iout est donc limité à un courant Itl dépendant du courant Irefl.In the case where the potential Vout is less than the potential Vt, the current Irep is supplied to the control means 14. The control means 14 is provided to keep the switch 16 open or closed depending on whether the current Irep, received on its terminal d 'input, is lower or higher than a reference current Irefl. When the current Irep becomes greater than the current Irefl, the switch 16 is closed and a current flows through the resistor RI. The potential of the node G3 drops, the transistor T3 becomes conducting and decreases the conduction of the transistors Tl and T2 until the current Irep becomes lower than the current Irefl. The circuit acts as a current limiter limiting the current Irep to the value Irefl. The current Iout is therefore limited to a current Itl depending on the current Irefl.
Dans le cas où le potentiel Vout est supérieur au potentiel Vt, le moyen d'aiguillage 10 est commandé par le comparateur de tension 12 de manière que le courant Irep est fourni à la borne d'entrée du moyen de commande 20. Le moyen de commande 20, de même structure que le moyen de commande 14, est prévu pour maintenir le commutateur 22 ouvert ou fermé selon que le courant reçu sur sa borne d'entrée est inférieur ou supérieur à un courant de référence Iref2. Le courant Iout fourni par le régulateur de tension est alors limité à une valeur It2 dépendant du courant Iref2.In the case where the potential Vout is greater than the potential Vt, the switching means 10 is controlled by the voltage comparator 12 so that the current Irep is supplied to the input terminal of the control means 20. The means of control 20, of the same structure as the control means 14, is provided to keep the switch 22 open or closed depending on whether the current received on its input terminal is less than or greater than a reference current Iref2. The current Iout supplied by the voltage regulator is then limited to a value It2 depending on the current Iref2.
La figure 4 représente un exemple de réalisation du régulateur de tension de la figure 3. Le comparateur de tension 12 comprend deux transistors MOS T4 et T5, à canal Ν, dont les drains sont reliés au potentiel Vbat et dont les sources sont respectivement reliées au potentiel GND par 1 ' intermédiaire de sources de courant CS4 et CS5. Les grilles des transistors T5 et T4 constituent les première et seconde entrées du comparateur 12. Le moyen d'aiguillage 10 comprend deux transistors MOS T6 et T7, à canal P, dont les sources sont reliées au drain du transistor T2 et dont les grilles sont respectivement reliées aux sources des transistors T4 et T5. Les transistors T4 et T5 forment une paire différentielle. Les drains des transistors T7 et T6 constituent respectivement les première et seconde bornes de sortie du moyen d'aiguillage 10. Le moyen de commande 14 comprend un transistor MOS à canal N dont la source est reliée au potentiel GND, et dont le drain et la grille sont connectés 1 'un à 1 ' autre ainsi qu' à une source de courant produisant le courant Irefl. Le drain et la grille du transistor du moyen de commande 14 constituent la borne d'entrée du moyen de commande 14. Le commutateur 16 est un transistor MOS à canal N connecté en miroir de courant avec le transistor du moyen de commande 14. La source du transistor 16 est reliée au potentiel GND et le drain du transistor 16 est relié au noeud G3. Le moyen de commande 20 comprend un transistor MOS à canal N dont la source est reliée au potentiel GND et dont le drain et la grille sont reliés 1 'un à 1 ' autre ainsi qu' à une source de courant produisant le courant Iref2. Le drain et la grille du transistor du moyen de commande 20 constituent la borne d'entrée du moyen de commande 20. Le commutateur 22 est un transistor MOS à canal N connecté en miroir de courant avec le transistor du moyen de commande 20. La source du transistor 22 est reliée au potentiel GND et le drain du transistor 22 est relié au noeud G3.FIG. 4 represents an exemplary embodiment of the voltage regulator of FIG. 3. The voltage comparator 12 comprises two MOS transistors T4 and T5, with channel Ν, whose drains are connected to the potential Vbat and whose sources are respectively connected to the GND potential through current sources CS4 and CS5. The gates of the transistors T5 and T4 constitute the first and second inputs of the comparator 12. The switching means 10 comprises two MOS transistors T6 and T7, with P channel, the sources of which are connected to the drain of the transistor T2 and the gates of which are respectively connected to the sources of transistors T4 and T5. The transistors T4 and T5 form a differential pair. The drains of the transistors T7 and T6 respectively constitute the first and second output terminals of the switching means 10. The control means 14 comprises an N-channel MOS transistor whose source is connected to the potential GND, and whose drain and grid are connected to one another as well as to a current source producing the current Irefl. The drain and the gate of the transistor of the control means 14 constitute the input terminal of the control means 14. The switch 16 is an N-channel MOS transistor connected in current mirror with the transistor of the control means 14. The source of transistor 16 is connected to potential GND and the drain of transistor 16 is connected to node G3. The control means 20 comprises an N-channel MOS transistor whose source is connected to the potential GND and whose drain and gate are connected to one another as well as to a current source producing the current Iref2. The drain and the gate of the transistor of the control means 20 constitute the input terminal of the control means 20. The switch 22 is an N-channel MOS transistor connected in current mirror with the transistor of the control means 20. The source of transistor 22 is connected to potential GND and the drain of transistor 22 is connected to node G3.
Lorsque le potentiel Vout est inférieur au potentiel Vt, le potentiel de la source du transistor T5 est inférieur au potentiel de la source du transistor T4. Il en résulte que le potentiel de la grille du transistor T7 est inférieur au potentiel de la grille du transistor T6. Le transistor T7 est alors plus conducteur que le transistor T6. Les transistors T4, T5, T6 et T7 sont choisis de manière que le courant Irep traverse alors uniquement le transistor T7 et non le transistor T6. Le drain du transistor du moyen de commande 14 reçoit alors le courant Irep. Tant que le courant Irep est inférieur au courant Irefl, les transistors 14 et 16 ne sont traversés par aucun courant. Lorsque le courant Irep devient supérieur au courant Irefl, les transistors 14 et 16 sont traversés par un courant Irep - Irefl. Lorsque le courant Irep - Irefl est suffisamment élevé, la chute de potentiel aux bornes de la résistance RI met en conduction le transistor T3 de manière à limiter le courant Iout à une valeur Itl, comme cela a été décrit en relation avec les figures 2 et 3.When the potential Vout is less than the potential Vt, the potential of the source of transistor T5 is less than the potential of the source of transistor T4. As a result, the potential of the gate of transistor T7 is less than the potential of the gate of transistor T6. The transistor T7 is then more conductive than the transistor T6. The transistors T4, T5, T6 and T7 are chosen so that the current Irep then passes only through the transistor T7 and not the transistor T6. The drain of transistor of the control means 14 then receives the current Irep. As long as the current Irep is less than the current Irefl, the transistors 14 and 16 are not crossed by any current. When the current Irep becomes greater than the current Irefl, the transistors 14 and 16 are crossed by a current Irep - Irefl. When the current Irep - Irefl is sufficiently high, the potential drop across the resistor RI turns on the transistor T3 so as to limit the current Iout to a value Itl, as has been described in relation to FIGS. 2 and 3.
Lorsque le potentiel Vout est supérieur au potentiel Vt, le courant Irep traverse le transistor T6 et non le transistor T7. Le fonctionnement du moyen de commande 20 et du commutateur 22 est alors semblable au fonctionnement du moyen de commande 14 et du commutateur 16 qui vient d'être exposé et le courant Iout est limité à une valeur It2.When the potential Vout is greater than the potential Vt, the current Irep passes through the transistor T6 and not the transistor T7. The operation of the control means 20 and of the switch 22 is then similar to the operation of the control means 14 and of the switch 16 which has just been exposed and the current Iout is limited to a value It2.
La figure 5 représente schématiquement un second mode de réalisation du régulateur de tension de la figure 2. Le dispositif 8 comprend le transistor MOS T2 à canal P, le comparateur de tension 12, le moyen d'aiguillage 10, les commutateurs 16 et 22 et les moyens de commande 14 et 20 du dispositif 8 décrit précédemment . Un transistor MOS T3 ' , à canal P, a sa source reliée au potentiel Vbat et son drain relié à la grille du transistor Tl . La grille du transistor T3 ' est reliée à la sortie d'un amplificateur opérationnel 26 alimenté entre les potentiels Vbat et GND. Les entrées non inverseuse E+ et inverseuse E~ de l'amplificateur 26 sont reliées au potentiel Vbat par l'intermédiaire respectivement d'impédances Zl et Z2. Les impédances Zl et Z2 sont égales et appariées, de manière que toute variation de valeur de Zl, par exemple à la suite d'une variation de température ou de processus de fabrication, corresponde à une variation égale de Z2. L' entrée inverseuse de l'amplificateur 26 est également reliée au potentiel GND par l'intermédiaire d'une source de courant produisant un courant 12 constant prédéterminé. L'entrée non inverseuse de l'amplificateur 26 est reliée au potentiel GND par l'intermédiaire des commutateurs 16 et 22, en parallèle.FIG. 5 schematically represents a second embodiment of the voltage regulator of FIG. 2. The device 8 comprises the P channel T2 MOS transistor, the voltage comparator 12, the switching means 10, the switches 16 and 22 and the control means 14 and 20 of the device 8 described above. A MOS transistor T3 ′, with P channel, has its source connected to the potential Vbat and its drain connected to the gate of the transistor Tl. The gate of transistor T3 'is connected to the output of an operational amplifier 26 supplied between the potentials Vbat and GND. The non-inverting E + and inverting E ~ inputs of the amplifier 26 are connected to the potential Vbat by means of impedances Z1 and Z2 respectively. The impedances Zl and Z2 are equal and matched, so that any variation in the value of Zl, for example following a variation in temperature or in the manufacturing process, corresponds to an equal variation in Z2. The inverting input of the amplifier 26 is also connected to the potential GND via a current source producing a predetermined constant current 12. The non-inverting input of amplifier 26 is connected to GND potential via switches 16 and 22, in parallel.
La commande du transistor T3 par l'amplificateur 26 dépend du rapport des chutes de potentiel dans les impédances Zl et Z2. Les impédances Zl et Z2 étant égales et appariées, il en découle que la commande du transistor T3 ' est indépendante des valeurs des impédances Zl et Z2 et dépend seulement du rapport entre les courants traversant les impédances Zl et Z2. Le courant 12 traversant l'impédance Z2 est constant. Le courant traversant l'impédance Zl est comparable au courant traversant la résistance RI de la figure 3. Le courant Iout dépend ainsi de Irefl ou de Iref2 selon que le potentiel Vout est inférieur ou supérieur au potentiel Vt. La commande du transistor T3 étant indépendante des valeurs Zl et Z2, le courant Iout est indépendant des variations des impédances Zl et Z2, ce qui constitue un avantage supplémentaire de la présente invention. En outre, le gain de l'amplificateur 26 peut être choisi élevé de manière que la commande du transistor T3 ' soit peu sensible à une dérive de la tension de seuil du transistor T3 ' , ce qui constitue un autre avantage de la présente invention.The control of the transistor T3 by the amplifier 26 depends on the ratio of the potential drops in the impedances Z1 and Z2. The impedances Zl and Z2 being equal and matched, it follows that the control of the transistor T3 'is independent of the values of the impedances Zl and Z2 and depends only on the ratio between the currents crossing the impedances Zl and Z2. The current 12 passing through the impedance Z2 is constant. The current passing through the impedance Zl is comparable to the current passing through the resistance RI of FIG. 3. The current Iout thus depends on Irefl or Iref2 depending on whether the potential Vout is lower or higher than the potential Vt. The control of the transistor T3 being independent of the values Zl and Z2, the current Iout is independent of the variations of the impedances Zl and Z2, which constitutes an additional advantage of the present invention. In addition, the gain of the amplifier 26 can be chosen to be high so that the control of the transistor T3 'is not very sensitive to a drift in the threshold voltage of the transistor T3', which constitutes another advantage of the present invention.
Lorsque le courant Iout varie brusquement, la boucle de limitation de courant réagit avec un retard, introduit notamment par l'amplificateur 26. Ce retard peut entraîner 1 ' apparition d'un pic du courant Iout entre 1 ' instant où le courant Iout commence à croître et l'instant où le transistor T3 ' est rendu passant. Un bloc de protection (non représenté) peut être disposé de manière à rendre le transistor T3 ' inconditionnellement passant pendant une durée prédéterminée après toute chute brutale du potentiel Vout ou à la mise sous tension du régulateur de tension, de manière à supprimer un tel pic de courant.When the current Iout varies suddenly, the current limiting loop reacts with a delay, introduced in particular by the amplifier 26. This delay can cause the appearance of a peak of the current Iout between the moment when the current Iout begins to grow and the instant when the transistor T3 'is turned on. A protective block (not shown) can be arranged so as to make the transistor T3 'unconditionally on for a predetermined period after any sudden drop in the potential Vout or when the voltage regulator is energized, so as to suppress such a peak current.
Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaîtront à l'homme de l'art. A titre d'exemple, la présente invention a été décrite en relation avec des moyens de commande 14 et 20, des commutateurs 16 et 22, un comparateur de tension 12 et un moyen d'aiguillage 10 particuliers, mais l'homme du métier adaptera sans difficultés la présente invention à un régulateur de tension utilisant des éléments de structures différentes mais remplissant des mêmes fonctions.Of course, the present invention is susceptible of various variants and modifications which will appear to those skilled in the art. By way of example, the present invention has been described in relation to control means 14 and 20, switches 16 and 22, a particular voltage comparator 12 and switching means 10, but those skilled in the art will easily adapt the present invention to a voltage regulator using elements of different structures but fulfilling the same functions.
La présente invention a été décrite en relation avec un régulateur de tension utilisant des potentiels Vbat, Vref et Vt positifs, mais l'homme du métier adaptera sans difficultés la présente invention à un régulateur de tension utilisant des potentiels négatifs en intervertissant les types des transistors MOS décrits.The present invention has been described in relation to a voltage regulator using positive Vbat, Vref and Vt potentials, but a person skilled in the art will easily adapt the present invention to a voltage regulator using negative potentials by inverting the types of the transistors. MOS described.
La présente invention a été décrite en relation avec un régulateur de tension dans lequel le potentiel Vt est choisi inférieur au potentiel Vref, mais l'homme du métier adaptera sans difficultés la présente invention à un régulateur de tension utilisant des potentiels Vt et Vref égaux. Dans ce cas, la paire différentielle formée par les transistors T4 et T5 sera déséquilibrée pour rendre le transistor T6 conducteur lorsque Vout ≈ Vref = Vt. La présente invention a pour des raisons de simplicité été décrite en relation avec un régulateur de tension utilisant une boucle de contre-réaction non résistive et fournissant un potentiel égal à un potentiel de référence Vref reçu. Toutefois, l'homme du métier adaptera sans difficultés la présente invention à un régulateur de tension dont la boucle de contre- réaction comprend un pont résistif, et qui fournit en sortie un potentiel différent du potentiel Vref reçu.The present invention has been described in relation to a voltage regulator in which the potential Vt is chosen lower than the potential Vref, but a person skilled in the art will easily adapt the present invention to a voltage regulator using equal potentials Vt and Vref. In this case, the differential pair formed by the transistors T4 and T5 will be unbalanced to make the transistor T6 conductive when Vout ≈ Vref = Vt. The present invention has for reasons of simplicity been described in relation to a voltage regulator using a non-resistive feedback loop and providing a potential equal to a reference potential Vref received. However, a person skilled in the art will easily adapt the present invention to a voltage regulator, the feedback loop of which comprises a resistive bridge, and which provides an output potential different from the potential Vref received.
La présente invention a été décrite en relation avec un régulateur de tension utilisant un transistor de puissance Tl, mais l'homme du métier adaptera sans difficultés la présente invention à un régulateur de tension utilisant un autre type de commutateur de puissance à commande en tension. The present invention has been described in relation to a voltage regulator using a power transistor T1, but a person skilled in the art will easily adapt the present invention to a voltage regulator using another type of voltage-controlled power switch.

Claims

REVENDICATIONS
1. Régulateur de tension ayant une borne de sortie (O) propre à être reliée à une charge (R, C) , comportant un dispositif (8) de limitation du courant (Iout) traversant la charge à un premier courant de seuil (Itl) si le potentiel de la borne de sortie (Vout) est inférieur à un potentiel de seuil (Vt) , et à un second courant de seuil (It2) plus élevé que le premier courant de seuil si le potentiel de la borne de sortie (Vout) est supérieur au potentiel de seuil (Vt) , caractérisé en ce qu'il comporte : un comparateur (12) pour comparer le potentiel (Vout) de la borne de sortie (O) au potentiel de seuil (Vt) , des première et seconde boucles de réaction (14, 16, 20, 22, RI, T3) propres à limiter le courant traversant la charge respectivement aux premier (Itl) et second (It2) courants de seuil, et un bloc d'aiguillage (T2, 10) commandable par le comparateur pour activer soit la première soit la seconde boucle de réaction selon que le potentiel de la borne de sortie (Vout) est inférieur ou non au potentiel de seuil (Vt) . 1. Voltage regulator having an output terminal (O) suitable for being connected to a load (R, C), comprising a device (8) for limiting the current (Iout) passing through the load to a first threshold current (Itl ) if the potential of the output terminal (Vout) is less than a threshold potential (Vt), and a second threshold current (It2) higher than the first threshold current if the potential of the output terminal ( Vout) is greater than the threshold potential (Vt), characterized in that it comprises: a comparator (12) for comparing the potential (Vout) of the output terminal (O) with the threshold potential (Vt), of the first and second feedback loops (14, 16, 20, 22, RI, T3) capable of limiting the current passing through the load respectively to the first (Itl) and second (It2) threshold currents, and a switching block (T2, 10) controllable by the comparator to activate either the first or the second feedback loop depending on whether the potential of the output terminal ( Vout) is lower or lower than the threshold potential (Vt).
2. Régulateur de tension selon la revendication 1, dans lequel : le bloc d'aiguillage (T2, 10) est propre à fournir un courant (Irep) dépendant du courant (Iout) traversant la charge sur une première ou sur une seconde sortie, et chaque boucle de réaction, reliée à une sortie du bloc d'aiguillage, comporte un bloc de commande (14, 16 ; 20, 22) propre à fournir un signal de commande lorsqu'il reçoit du bloc d'aiguillage un courant supérieur à un courant de référence (Irefl ; Iref2) , et comporte en outre un moyen de blocage (T3, RI ; T3 ' , Zl, Z2, 26) qui reçoit la sortie des blocs de commande et qui fait décroître le courant traversant la charge lorsque l'un quelconque des premier et second signaux de commande est actif.2. Voltage regulator according to claim 1, in which: the switching block (T2, 10) is capable of supplying a current (Irep) dependent on the current (Iout) passing through the load on a first or on a second output, and each feedback loop, connected to an output of the switch block, comprises a control block (14, 16; 20, 22) suitable for supplying a control signal when it receives from the switch block a current greater than a reference current (Irefl; Iref2), and further comprises a blocking means (T3, RI; T3 ', Zl, Z2, 26) which receives the output of the control blocks and which decreases the current passing through the load when any of the first and second control signals are active.
3. Régulateur de tension selon la revendication 2 , comportant : un commutateur de puissance (Tl) disposé de manière à relier la borne de sortie (O) à un premier potentiel d'alimentation (Vbat) , et un premier amplificateur opérationnel (2) dont les entrées inverseuse (E~) et non inverseuse (E+) sont respectivement reliées au potentiel de référence (Vref) et à la borne de sortie (O) , une borne de commande du commutateur de puissance (Tl) étant reliée à la sortie du premier amplificateur opérationnel (2) et le dispositif (8) de limitation du courant (Iout) traversant la charge étant relié à la borne de commande du commutateur de puissance (Tl) , la charge comportant un condensateur (C) et une première impédance (R) reliés en parallèle entre la borne de sortie (O) et un second potentiel d'alimentation (GND) . 3. Voltage regulator according to claim 2, comprising: a power switch (Tl) arranged so as to connect the output terminal (O) to a first supply potential (Vbat), and a first operational amplifier (2) whose inverting (E ~ ) and non-inverting inputs ( E + ) are respectively connected to the reference potential (Vref) and to the output terminal (O), a control terminal of the power switch (Tl) being connected to the output of the first operational amplifier (2) and the device ( 8) for limiting the current (Iout) passing through the load being connected to the control terminal of the power switch (Tl), the load comprising a capacitor (C) and a first impedance (R) connected in parallel between the output terminal (O) and a second supply potential (GND).
4. Régulateur de tension selon la revendication 3, dans lequel le bloc d'aiguillage (T2, 10) comporte : un premier transistor MOS (T2) d'un premier type ayant sa source reliée au premier potentiel d'alimentation (Vbat) et sa grille reliée à la borne de commande du commutateur de puissance (Tl) , et des deuxième (T6) et troisième (T7) transistors MOS du premier type ayant leurs sources reliées au drain du premier transistor (T2) , les drains des deuxième (T6) et troisième (T7) transistors constituant respectivement les première et seconde sorties du bloc d'aiguillage.4. Voltage regulator according to claim 3, in which the switching block (T2, 10) comprises: a first MOS transistor (T2) of a first type having its source connected to the first supply potential (Vbat) and its gate connected to the control terminal of the power switch (Tl), and of the second (T6) and third (T7) MOS transistors of the first type having their sources connected to the drain of the first transistor (T2), the drains of the second ( T6) and third (T7) transistors respectively constituting the first and second outputs of the switch block.
5. Régulateur de tension selon la revendication 4, dans lequel le comparateur (12) comprend des quatrième (T4) et cinquième (T5) transistors MOS d'un second type dont les drains sont reliés au premier potentiel d'alimentation (Vbat), dont les grilles sont respectivement reliées au potentiel de seuil (Vt) et à la borne de sortie (O) , les sources des quatrième (T4) et cinquième (T5) transistors étant respectivement reliées aux grilles des deuxième (T6) et troisième (T7) transistors, ainsi qu'au second potentiel d'alimentation (GND) par l'intermédiaire de première (CS4) et deuxième (CS5) sources de courant. 5. Voltage regulator according to claim 4, in which the comparator (12) comprises fourth (T4) and fifth (T5) MOS transistors of a second type, the drains of which are connected to the first supply potential (Vbat), the gates of which are respectively connected to the threshold potential (Vt) and to the output terminal (O), the sources of the fourth (T4) and fifth (T5) transistors being respectively connected to the gates of the second (T6) and third (T7) ) transistors, as well as to the second supply potential (GND) via first (CS4) and second (CS5) current sources.
6. Régulateur de tension selon la revendication 5, dans lequel le bloc de commande de chaque boucle de réaction comporte un couple de transistors MOS (14, 16 ; 20, 22) du second type dont les sources sont reliées au second potentiel d'alimentation (GND), dont les grilles sont reliées l'une à 1 'autre ainsi qu 'à une source de courant produisant un courant de référence (Irefl ; Iref2) , le drain et la grille d'un premier transistor du couple de transistors étant reliés l'un à l'autre ainsi qu'à l'une des sorties du bloc d'aiguillage, le courant traversant le second transistor du couple de transistors correspondant au signal de commande fourni par le bloc de commande.6. Voltage regulator according to claim 5, in which the control block of each feedback loop comprises a pair of MOS transistors (14, 16; 20, 22) of the second type, the sources of which are connected to the second supply potential. (GND), the gates of which are connected to each other and to a current source producing a reference current (Irefl; Iref2), the drain and the gate of a first transistor of the couple of transistors being connected to each other as well as to one of the outputs of the switching block, the current passing through the second transistor of the pair of transistors corresponding to the control signal supplied by the control block.
7. Régulateur de tension selon la revendication 6, dans lequel le moyen de blocage qui reçoit la sortie des blocs de commande comprend : une résistance (RI) dont une première borne est reliée au premier potentiel d'alimentation (Vbat) et dont une seconde borne est disposée de manière à recevoir la somme des signaux de commande fournis par les blocs de commande, et un sixième transistor MOS (T3) du premier type dont la source est reliée au premier potentiel d'alimentation (Vbat), dont le drain est relié à la borne de commande du commutateur de puissance (Tl) , et dont la grille est reliée à la seconde borne de la résistance. 7. Voltage regulator according to claim 6, in which the blocking means which receives the output of the control blocks comprises: a resistor (RI) of which a first terminal is connected to the first supply potential (Vbat) and of which a second terminal is arranged to receive the sum of the control signals supplied by the control blocks, and a sixth MOS transistor (T3) of the first type, the source of which is connected to the first supply potential (Vbat), the drain of which is connected to the control terminal of the power switch (Tl), and the grid of which is connected to the second terminal of the resistor.
8. Régulateur de tension selon la revendication 6, dans lequel le moyen de blocage qui reçoit la sortie des blocs de commande comprend : une seconde impédance (Zl) dont une première borne est reliée au premier potentiel d'alimentation (Vbat) et dont une seconde borne est disposée de manière à recevoir la somme des signaux de commande fournis par les blocs de commande, une troisième impédance (Z2) , appariée à la seconde impédance (Zl) dont une première borne est reliée au premier potentiel d'alimentation (Vbat) et dont une seconde borne reçoit un courant constant prédéterminé (12) , un second amplificateur opérationnel (26) dont les entrées non inverseuse et inverseuse sont respectivement reliées à la seconde borne des seconde (Zl) et troisième (Z2) impédances, et un septième transistor MOS (T3 ' ) du premier type dont la source est reliée au premier potentiel d'alimentation (Vbat), dont le drain est relié à la borne de commande du commutateur de puissance (Tl) , et dont la grille est reliée à la sortie du second amplificateur opérationnel (26) . 8. Voltage regulator according to claim 6, in which the blocking means which receives the output of the control blocks comprises: a second impedance (Zl) of which a first terminal is connected to the first supply potential (Vbat) and of which a second terminal is arranged so as to receive the sum of the control signals supplied by the control blocks, a third impedance (Z2), paired with the second impedance (Zl), a first terminal of which is connected to the first supply potential (Vbat ) and a second terminal of which receives a predetermined constant current (12), a second operational amplifier (26) whose non-inverting and inverting inputs are respectively connected to the second terminal of the second (Zl) and third (Z2) impedances, and a seventh MOS transistor (T3 ') of the first type whose source is connected to the first supply potential (Vbat), the drain of which is connected to the control terminal of the power switch (T1), and the gate of which is connected to the output of the second operational amplifier (26).
9. Régulateur de tension selon l'une quelconque des revendications 3 à 8, dans lequel le premier potentiel d'alimentation (Vbat) , le potentiel de référence (Vref) et le potentiel de seuil (Vt) sont des potentiels positifs de valeurs décroissantes, le second potentiel d'alimentation est un potentiel de masse, le commutateur de puissance et les transistors du premier type sont des transistors MOS à canal P, et les transistors du second type sont des transistors MOS à canal N. 9. Voltage regulator according to any one of claims 3 to 8, in which the first supply potential (Vbat), the reference potential (Vref) and the threshold potential (Vt) are positive potentials of decreasing values. , the second supply potential is a ground potential, the power switch and the transistors of the first type are P-channel MOS transistors, and the transistors of the second type are N-channel MOS transistors
EP02700338.3A 2001-01-19 2002-01-18 Voltage regulator protected against short-circuits Expired - Lifetime EP1366402B1 (en)

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EP1366402B1 (en) 2015-11-04
US20030147193A1 (en) 2003-08-07
FR2819904B1 (en) 2003-07-25
FR2819904A1 (en) 2002-07-26
US6804102B2 (en) 2004-10-12
WO2002057863A1 (en) 2002-07-25

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