EP1148405A1 - Linear regulator with low over-voltage in transient-state - Google Patents

Linear regulator with low over-voltage in transient-state Download PDF

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Publication number
EP1148405A1
EP1148405A1 EP01108258A EP01108258A EP1148405A1 EP 1148405 A1 EP1148405 A1 EP 1148405A1 EP 01108258 A EP01108258 A EP 01108258A EP 01108258 A EP01108258 A EP 01108258A EP 1148405 A1 EP1148405 A1 EP 1148405A1
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Prior art keywords
voltage
regulator
transistor
output
switch
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EP01108258A
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German (de)
French (fr)
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EP1148405B1 (en
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Nicolas Marty
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STMicroelectronics SA
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STMICROELECTRONICS
STMicroelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to regulators linear low dropout series LDO type (Low Drop Out Regulators).
  • Such regulators are the subject of various applications, especially in the field of telephones movable to deliver regulated voltage to circuits radio transmission-reception from a voltage power supplied by a rechargeable battery.
  • Figure 1 shows a classic regulator 10 whose output delivers a regulated voltage Vout at a load Z.
  • the load Z represents for example various radio circuits present in a mobile phone.
  • Regulator 10 is powered by a voltage Vbat, delivered here by the battery 1 of the mobile phone, and includes an amplifier differential 2 whose output drives the grid G of a PMOS type regulation transistor 3.
  • the floor of amplifier 2 output has a resistor internal Rg shown in dotted lines, or gate resistance, which determines the gain of amplifier 2 and the maximum current it can output.
  • Transistor 3 receives at its source S the voltage Vbat and its drain D, which is connected to the output of regulator 10, is connected to the anode of a filtering and stabilizing capacitor Cst voltage Vout, arranged in parallel with the load Z.
  • Amplifier 2 receives on its negative input a reference voltage Vref and on its positive input a feedback voltage Vfb (feedback), for example a fraction of the voltage Vout brought back to the input of amplifier 2 via a divider bridge voltage comprising two resistors R1, R2.
  • the gate resistance Rg of the output stage of amplifier 2 must be chosen with a high value, for example 100K ⁇ , in order to limit the maximum current circulating in the output stage in the high state.
  • the regulation transistor 3 must have a low series resistance RdsON in the on state (drain-source resistance) in order to be able to deliver a large current without an unacceptable drop in voltage across its terminals.
  • the transistor 3 conventionally has a high width-to-length ratio of the gate, for example a gate width W of 2 10 5 micrometers for a gate length L of 0.6 micrometers, which represents a W / L ratio of l 'order of 3 10 5 and a very large transistor width. Because of its size and its high W / L ratio, the transistor 3 also has a high gate capacity Cg, shown in dotted lines in FIG. 1, of the order of 100 to 200 picofarads.
  • Figures 2A, 2B, 2C illustrate a phenomenon of overvoltage appearing at the mobile phone regulator output when the phone transmits at regular intervals, for example every 4 milliseconds, bursts of data or "GSM burst".
  • Figure 2A shows the voltage of Vbat battery whose nominal value Vbatnom is here from 3.5 v.
  • FIG. 2B represents the gate voltage Vg whose value oscillates in the vicinity of a voltage Vgnom equal to Vbat-Vtp when the regulator is stabilized, here 2.8 V if the threshold voltage Vtp of the transistor is 0.7 V.
  • Figure 2C shows the voltage output Vout whose nominal value Voutnom is here 2.8 V when the regulator is stabilized.
  • the radio circuits of the telephone enter service to issue a salvo.
  • the flow consumed is very important and the voltage Vbat drops suddenly below the nominal value Voutnom (fig. 2A) due to the internal resistance of the drums.
  • Amplifier 2 is unbalanced, the voltage Vg goes to 0 (fig. 2B), the gate capacity Cg is fully discharged and transistor 3 is on.
  • the regulator 10 thus operates in follower mode, the output voltage Vout being substantially equal to the Vbat voltage (fig. 2C).
  • Vbat battery goes up quickly (fig. 2A), for example in 1 microsecond, up to its nominal value Vbatnom.
  • the output voltage Vout follows voltage Vbat up to reach, at an instant t3, its nominal value Voutnom.
  • amplifier 2 releases its output from the low state to the high state and the gate of transistor 3 is connected to the voltage Vbat via the gate resistance Rg, which should normally should cause the immediate blocking of transistor 3.
  • the gate voltage Vg increases only very slowly in due to the high value of the gate resistance Rg, which limits the current delivered, and the high value of the grid capacity Cg.
  • the output stage of amplifier 2 is therefore unable to charge instantly the grid capacity Cg and block the transistor 3.
  • the latter continues to be on and the Vout voltage continues to follow Vbat voltage.
  • Vbat voltage As illustrated in Figure 2C, we thus see appear at the regulator output OS voltage spike. This peak of tension can disappear only from an instant t4, when the gate voltage Vg crosses the value Vbat-Vtp ensuring the blocking of transistor 3, and on condition that the load Z consumes current.
  • the present invention aims to overcome this disadvantage.
  • an objective of this invention is to remove, or at the very least limit, the effect of overvoltage in transient mode at the output a voltage regulator without the need to modify the structure of the regulation transistor to decrease its grid capacity.
  • Another object of the present invention is also to suppress or limit the effect of overvoltage transient without the need increase the maximum current that can be delivered by the output of the control amplifier.
  • a voltage regulator comprising a MOS transistor low resistance series control including one terminal receives a supply voltage and whose other terminal is connected to the regulator output, and an amplifier whose output drives the gate of the transistor in function the difference between a reference voltage and a voltage feedback
  • the regulator comprising a switch, one terminal of which is connected to the grid of the regulating transistor and the other terminal is brought to a blocking potential of the regulation transistor, and switch control means, monitoring the regulator output, arranged to close the switch when the regulator output voltage is higher at a first threshold higher than the nominal value of the output voltage.
  • the means of switch control are arranged to compare the regulator output voltage or a voltage proportional to the output voltage with the voltage of reference.
  • the means of switch control include comparator whose output delivers a closing signal of the switch, the comparator receiving on an input the reference voltage and on another input the voltage output or a voltage proportional to the voltage of exit.
  • the comparator has a switching hysteresis chosen so that the switch is reopened when the voltage of output becomes less than a second threshold less than first threshold and higher than the nominal value of the output voltage.
  • the transistor regulation is a PMOS transistor and the potential for blocking is the supply voltage.
  • the amplifier includes an output stage with a resistance of value grid too large for current crossing the grid resistor can assure it only rapid blocking of the regulation transistor when the supply voltage increases rapidly.
  • the switch is a PMOS transistor having a drain-source resistance at the passing state much lower than the gate resistance of the amplifier output stage.
  • the present invention also relates to a mobile phone including battery and circuits radio powered by the battery through a voltage regulator according to the invention.
  • the present invention also provides a method to prevent or limit the occurrence of a surge to the output of a voltage regulator when the voltage the regulator supply increases rapidly, the regulator comprising a regulation MOS transistor with high grid capacity, the grid of which is controlled by an amplifier delivering current alone insufficient to ensure rapid blocking of the transistor regulation, the method comprising a step consisting of to provide a switch connected between the grid of the regulating transistor and a blocking potential of the regulation transistor, and a step consisting in close the switch when the output voltage of the regulator becomes greater than a first threshold higher than the nominal value of the output voltage, so as to temporarily help the amplifier to block the regulating transistor.
  • the method comprises a step of reopening the switch when the regulator output voltage becomes less than one second threshold between the nominal value of the output voltage and the first threshold.
  • FIG. 3 represents a regulator 20 according to the invention, supplied here by a voltage Vbat supplied by the anode of a battery 1.
  • the regulator 20 comprises, like that of FIG. 1, a differential amplifier 2 whose output controls the gate d 'a PMOS type regulation transistor 3.
  • the drain D of transistor 3 is connected at the output of regulator 20 to a stabilization capacity Cst arranged in parallel with a load Z.
  • the output voltage Vout is brought to the positive input of the amplifier 2 via a divider bridge comprising two resistors R1, R2.
  • Resistor R2 here consists of two resistors R21, R22 in series.
  • the reference voltage Vref applied to the input negative of amplifier 2 is for example a voltage so-called band-gap with good stability in temperature function, generated by means of diodes PN junction and current mirrors.
  • the voltage Vref is thus independent of the voltage Vbat, on the condition of course to be chosen lower than the value the lower voltage Vbat.
  • Voutnom (R1 + R2) Vref / R2
  • the regulator 20 comprises a anti-overvoltage switch 4 connected between the anode of battery 1 and gate G of transistor 3.
  • Switch 4 is here a PMOS type transistor of which the source S receives the voltage Vbat and whose drain D is connected to gate G of transistor 3.
  • the W / L ratio length over gate width of transistor 4 is chosen so that its RdsON series resistance in the on state is quite low, preferably much lower than the gate resistance Rg of the output stage of amplifier 2.
  • the gate G of the transistor 4 is controlled by a signal Vos delivered by the output of a comparator 5.
  • the comparator 5 is supplied by the voltage Vbat and receives on its positive input the voltage Vref and on its input negative a VA voltage.
  • the resistor R21 is small compared to the resistor R22 so that the voltage VA is very close to the voltage Vfb.
  • R21 x R2
  • R22 (1-x) R2 with "x" between 0 and 1 and close to 0, x being for example equal to 0.05.
  • the voltage Va is significantly lower than the voltage Vref.
  • the voltage Vfb is in this case substantially equal to Vref and the relation (3) becomes: (6)
  • VA R22 Vref / R2 is : (7)
  • VA (1-x) Vref with x less than 1 and close to 0 as indicated above, and 1-x less than 1 and close to 1.
  • Comparator 5 and anti-overvoltage transistor 4 become active on a transitional basis, when the Vbat tension rises sharply after strongly decreased due to a peak in current consumption, by example in the situation described in the preamble, i.e. after the issuance of a data burst by the mobile phone radio circuit.
  • Such a situation is illustrated in Figures 2A, 4A, 4B, 4C, which respectively represent the voltage profile of Vbat battery, the voltage Vg delivered by the amplifier 2 on the gate of the regulation transistor 3, the voltage Vout and control voltage of the anti-overvoltage transistor 4.
  • regulator 20 During the fall of Vbat voltage, from time t1, regulator 20 is unbalanced and goes into follower mode, the output voltage Vout copying the Vbat voltage. During this period, the voltage VA continues to fall and thus remains below the voltage Vref, the signal Vos at the output of the comparator remaining at 1 (Vbat).
  • the voltage Vbat rises sharply and the voltage Vout follows the voltage Vbat.
  • the voltage Vout reaches the regulation point Voutnom and amplifier 2 switches its output to the high state.
  • the amplifier is, by design, incapable of supply the necessary current to immediately charge the gate capacity Cg of transistor 3.
  • the voltage of exit Vout therefore continues to rise after time t3 and to follow the voltage Vbat, the transistor 3 remaining passerby.
  • the voltage Vout reaches a threshold value Vout1 such that the voltage VA at the input of comparator 5 becomes equal to Vref.
  • the exit of the comparator 5 switches to 0 (fig. 4C) and the transistor surge protector 4 turns on.
  • Series resistance RdsON in the on state of transistor 4 being weak, the gate G of the regulation transistor 3 receives the current necessary to charge the grid capacity Cg and the transistor 3 crashes almost instantly.
  • the regulator 20 may have a direct feedback of the voltage Vout on the input of amplifier 2.
  • the comparator 5 has a switching hysteresis so avoid possible instability of the voltage Vout at neighborhood of the threshold Vout1.
  • the output of the comparator 5 changes to 1 when the voltage VA reaches a Vref 'value significantly lower than Vref.
  • FIG. 5 shows by way of example a low consumption amplifier structure 2, having limited output current.
  • the amplifier includes input a differential stage represented here in the form of a block 30, receiving the voltages Vref and Vfb.
  • the floor differential 30 is biased by a current generator 31 which limits its consumption.
  • the exit of the floor differential 30 drives the gate of a transistor 32 NMOS type, connected between the output node of amplifier 2 and ground.
  • the transistor 32 is polarized on its drain D by a current generator 33 limiting the consumption of the output stage to the state low.
  • the gate resistor Rg Also found in amplifier 2 is the gate resistor Rg, connected to the output node of the amplifier and receiving at its other end the Vbat voltage.
  • transistor 32 draws the output of the amplifier to ground and resistance Rg pulls the output at supply voltage Vbat according to the value of the signal delivered by the differential stage 30.
  • the anti-overvoltage transistor 4 can be modeled under the form of a perfect 4-1 switch in series with a resistor 4-2, which is here the RdsON series resistor of the transistor.
  • a resistor 4-2 which is here the RdsON series resistor of the transistor.
  • an external resistance can possibly be added to switch 4 to limit the charging current of the gate capacity Cg while maintaining an acceptable blocking time in transitional regime.
  • the regulator according to the invention is of course susceptible of various applications other than that set out in the preamble, and various variants of realization and improvements.
  • comparator 5 is a threshold comparator ⁇ .
  • the comparator output does not pass at 0 only at the moment when the voltage Vfb becomes greater or equal to Vref + ⁇ .
  • the anti-surge switch according to the invention must receive a potential ensuring the blocking of the regulation transistor.
  • Teaching set out in this application thus applies to the realization of a regulator having a transistor NMOS type regulation, to solve the problem reverse, namely the discharge of the grid capacity of the regulating transistor at blocking thereof when the maximum current entering the output stage of the amplifier when it goes to 0 is limited.
  • This potential is for example the mass with a transistor of NMOS regulation.

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  • Electromagnetism (AREA)
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Abstract

La présente invention concerne un régulateur de tension (20) comprenant un transistor MOS de régulation (3) à faible résistance série dont une borne est reliée à une source de tension (1) et dont l'autre borne est reliée à la sortie du régulateur, et un amplificateur (2) dont la sortie pilote la grille du transistor (3) en fonction de l'écart entre une tension de référence (Vref) et une tension de contre-réaction (Vfb). Selon l'invention, le régulateur comprend un interrupteur anti-surtension (4) dont une borne est reliée à la grille du transistor de régulation (3) et l'autre borne est portée à un potentiel (Vbat) de blocage du transistor de régulation (3). Des moyens (5, R21, R22) de commande de l'interrupteur (4) sont agencés pour fermer l'interrupteur (4) lorsque la tension de sortie (Vout) du régulateur est supérieure à un premier seuil supérieur à la valeur nominale de la tension de sortie. <IMAGE>The present invention relates to a voltage regulator (20) comprising a regulating MOS transistor (3) with low series resistance, one terminal of which is connected to a voltage source (1) and the other terminal of which is connected to the output of the regulator. , and an amplifier (2) whose output drives the gate of the transistor (3) as a function of the difference between a reference voltage (Vref) and a feedback voltage (Vfb). According to the invention, the regulator comprises an anti-overvoltage switch (4) one terminal of which is connected to the gate of the regulation transistor (3) and the other terminal is brought to a potential (Vbat) for blocking the regulation transistor. (3). Means (5, R21, R22) for controlling the switch (4) are arranged to close the switch (4) when the output voltage (Vout) of the regulator is greater than a first threshold greater than the nominal value of the output voltage. <IMAGE>

Description

La présente invention concerne les régulateurs linéaires à faible chute de tension série du type LDO (Low Drop Out Regulators).The present invention relates to regulators linear low dropout series LDO type (Low Drop Out Regulators).

De tels régulateurs font l'objet de diverses applications, notamment dans le domaine des téléphones mobiles pour délivrer une tension régulée à des circuits d'émission-réception radio à partir d'une tension d'alimentation fournie par une batterie rechargeable.Such regulators are the subject of various applications, especially in the field of telephones movable to deliver regulated voltage to circuits radio transmission-reception from a voltage power supplied by a rechargeable battery.

A titre d'exemple, la figure 1 représente un régulateur classique 10 dont la sortie délivre une tension régulée Vout à une charge Z. La charge Z représente par exemple divers circuits radio présents dans un téléphone mobile. Le régulateur 10 est alimenté par une tension Vbat, délivrée ici par la batterie 1 du téléphone mobile, et comprend un amplificateur différentiel 2 dont la sortie pilote la grille G d'un transistor de régulation 3 du type PMOS. L'étage de sortie de l'amplificateur 2 comporte une résistance interne Rg représentée en traits pointillés, ou résistance de grille, qui détermine le gain de l'amplificateur 2 et le courant maximal qu'il peut délivrer en sortie. Le transistor 3 reçoit sur sa source S la tension Vbat et son drain D, qui est relié à la sortie du régulateur 10, est connecté à l'anode d'un condensateur Cst de filtrage et de stabilisation de la tension Vout, agencé en parallèle avec la charge Z. L'amplificateur 2 reçoit sur son entrée négative une tension de référence Vref et sur son entrée positive une tension de contre-réaction Vfb (feed-back), par exemple une fraction de la tension Vout ramenée sur l'entrée de l'amplificateur 2 par l'intermédiaire d'un pont diviseur de tension comprenant deux résistances R1, R2. For example, Figure 1 shows a classic regulator 10 whose output delivers a regulated voltage Vout at a load Z. The load Z represents for example various radio circuits present in a mobile phone. Regulator 10 is powered by a voltage Vbat, delivered here by the battery 1 of the mobile phone, and includes an amplifier differential 2 whose output drives the grid G of a PMOS type regulation transistor 3. The floor of amplifier 2 output has a resistor internal Rg shown in dotted lines, or gate resistance, which determines the gain of amplifier 2 and the maximum current it can output. Transistor 3 receives at its source S the voltage Vbat and its drain D, which is connected to the output of regulator 10, is connected to the anode of a filtering and stabilizing capacitor Cst voltage Vout, arranged in parallel with the load Z. Amplifier 2 receives on its negative input a reference voltage Vref and on its positive input a feedback voltage Vfb (feedback), for example a fraction of the voltage Vout brought back to the input of amplifier 2 via a divider bridge voltage comprising two resistors R1, R2.

Le fonctionnement d'un tel régulateur, bien connu de l'homme de l'art, consiste dans une modulation de la tension de grille Vg du transistor 3 par l'amplificateur 2 en fonction de l'écart entre la tension de contre-réaction Vfb et la tension de référence Vref. Lorsque la tension Vg est sensiblement inférieure à Vbat-Vtp le transistor 3 est passant car sa tension grille-source Vgs est sensiblement supérieure à sa tension de seuil Vtp. Lorsque la tension Vg est supérieure à Vbat-Vtp, le transistor 3 est bloqué. Ainsi, en régime stabilisé, la tension Vout est régulée au voisinage de sa valeur nominale Voutnom, qui est ici égale à (R1+R2)Vref/R2.The operation of such a well-known regulator skilled in the art, consists in modulating the gate voltage Vg of transistor 3 by the amplifier 2 depending on the difference between the feedback voltage Vfb and the reference voltage Vref. When the voltage Vg is significantly lower than Vbat-Vtp the transistor 3 is conducting because its gate-source voltage Vgs is significantly higher than its threshold voltage Vtp. When the voltage Vg is greater than Vbat-Vtp, the transistor 3 is blocked. Thus, in steady state, the voltage Vout is regulated near its value nominal Voutnom, which is here equal to (R1 + R2) Vref / R2.

Dans une application telle que l'alimentation électrique des circuits radio d'un téléphone mobile, il est important que l'amplificateur 2 présente une consommation électrique aussi faible que possible afin de préserver l'autonomie de la batterie 1. A cet effet, la résistance de grille Rg de l'étage de sortie de l'amplificateur 2 doit être choisie de forte valeur, par exemple 100KΩ, afin de limiter le courant maximal circulant dans l'étage de sortie à l'état haut.In an application such as food electric radio circuits of a mobile phone it it is important that amplifier 2 has a power consumption as low as possible in order to to preserve the autonomy of the battery 1. To this end, the gate resistance Rg of the output stage of amplifier 2 must be chosen with a high value, for example 100KΩ, in order to limit the maximum current circulating in the output stage in the high state.

D'autre part, le transistor de régulation 3 doit présenter une faible résistance série RdsON à l'état passant (résistance drain-source) pour pouvoir délivrer un courant important sans chute de tension rédhibitoire à ses bornes. Ainsi, le transistor 3 présente classiquement un rapport largeur sur longueur de grille élevé, par exemple une largeur W de grille de 2 105 micromètres pour une longueur L de grille de 0,6 micromètre, ce qui représente un rapport W/L de l'ordre de 3 105 et une largeur de transistor très importante. En raison de sa taille et de son rapport W/L élevé, le transistor 3 présente également une capacité de grille Cg élevée, représentée en traits pointillés sur la figure 1, de l'ordre de 100 à 200 picofarads.On the other hand, the regulation transistor 3 must have a low series resistance RdsON in the on state (drain-source resistance) in order to be able to deliver a large current without an unacceptable drop in voltage across its terminals. Thus, the transistor 3 conventionally has a high width-to-length ratio of the gate, for example a gate width W of 2 10 5 micrometers for a gate length L of 0.6 micrometers, which represents a W / L ratio of l 'order of 3 10 5 and a very large transistor width. Because of its size and its high W / L ratio, the transistor 3 also has a high gate capacity Cg, shown in dotted lines in FIG. 1, of the order of 100 to 200 picofarads.

Bien que ces diverses caractéristiques soient indispensables à l'obtention d'un régulateur à faible consommation et faible chute de tension série, le fait de piloter un transistor de régulation ayant une forte capacité de grille Cg au moyen d'un amplificateur ayant un courant maximal de sortie limité entraíne, dans certaines conditions de fonctionnement, des phénomènes de surtension (overshoot) indésirables à la sortie du régulateur.Although these various characteristics are essential for obtaining a low regulator consumption and low series voltage drop, the fact of drive a regulation transistor having a strong gate capacity Cg by means of an amplifier having a limited maximum output current leads, in certain operating conditions, unwanted overshoot on leaving the regulator.

A titre d'exemple, les figures 2A, 2B, 2C illustrent un phénomène de surtension apparaissant à la sortie du régulateur d'un téléphone mobile lorsque le téléphone émet à intervalles réguliers, par exemple toutes les 4 millisecondes, des salves de données ou "burst GSM". La figure 2A représente la tension de batterie Vbat dont la valeur nominale Vbatnom est ici de 3,5 v. La figure 2B représente la tension de grille Vg dont la valeur oscille au voisinage d'une tension Vgnom égale à Vbat-Vtp lorsque le régulateur est stabilisé, soit ici 2,8 V si la tension de seuil Vtp du transistor est de 0,7 V. Enfin, la figure 2C représente la tension de sortie Vout dont la valeur nominale Voutnom est ici de 2,8 V lorsque le régulateur est stabilisé.For example, Figures 2A, 2B, 2C illustrate a phenomenon of overvoltage appearing at the mobile phone regulator output when the phone transmits at regular intervals, for example every 4 milliseconds, bursts of data or "GSM burst". Figure 2A shows the voltage of Vbat battery whose nominal value Vbatnom is here from 3.5 v. FIG. 2B represents the gate voltage Vg whose value oscillates in the vicinity of a voltage Vgnom equal to Vbat-Vtp when the regulator is stabilized, here 2.8 V if the threshold voltage Vtp of the transistor is 0.7 V. Finally, Figure 2C shows the voltage output Vout whose nominal value Voutnom is here 2.8 V when the regulator is stabilized.

A un instant t1, les circuits radio du téléphone entrent en service pour émettre une salve. Le courant consommé est très important et la tension Vbat chute brutalement en dessous de la valeur nominale Voutnom (fig. 2A) en raison de la résistance interne de la batterie. L'amplificateur 2 est déséquilibré, la tension Vg passe à 0 (fig. 2B), la capacité de grille Cg est entièrement déchargée et le transistor 3 est passant. Le régulateur 10 fonctionne ainsi en mode suiveur, la tension de sortie Vout étant sensiblement égale à la tension Vbat (fig. 2C).At an instant t1, the radio circuits of the telephone enter service to issue a salvo. The flow consumed is very important and the voltage Vbat drops suddenly below the nominal value Voutnom (fig. 2A) due to the internal resistance of the drums. Amplifier 2 is unbalanced, the voltage Vg goes to 0 (fig. 2B), the gate capacity Cg is fully discharged and transistor 3 is on. The regulator 10 thus operates in follower mode, the output voltage Vout being substantially equal to the Vbat voltage (fig. 2C).

A un instant t2, l'émission de la salve est terminée et le courant consommé diminue. La tension de batterie Vbat remonte rapidement (fig. 2A), par exemple en 1 microseconde, jusqu'à sa valeur nominale Vbatnom. La tension de sortie Vout suit la tension Vbat jusqu'à atteindre, à un instant t3, sa valeur nominale Voutnom. A cet instant, l'amplificateur 2 relâche sa sortie de l'état bas vers l'état haut et la grille du transistor 3 se trouve reliée à la tension Vbat par l'intermédiaire de la résistance de grille Rg, ce qui devrait normalement devrait entraíner le blocage immédiat du transistor 3. Toutefois, comme cela est illustré en figure 2B, la tension de grille Vg n'augmente que très lentement en raison de la forte valeur de la résistance de grille Rg, qui limite le courant délivré, et de la forte valeur de la capacité de grille Cg. L'étage de sortie de l'amplificateur 2 est donc dans l'incapacité de charger instantanément la capacité de grille Cg et de bloquer le transistor 3. Ce dernier continue d'être passant et la tension Vout continue de suivre la tension Vbat. Comme illustré en figure 2C, on voit ainsi apparaítre à la sortie du régulateur un pic de tension OS. Ce pic de tension ne peut disparaítre qu'à partir d'un instant t4, quand la tension de grille Vg franchit la valeur Vbat-Vtp assurant le blocage du transistor 3, et à la condition que la charge Z consomme du courant.At an instant t2, the emission of the burst is completed and the current consumed decreases. The tension of Vbat battery goes up quickly (fig. 2A), for example in 1 microsecond, up to its nominal value Vbatnom. The output voltage Vout follows voltage Vbat up to reach, at an instant t3, its nominal value Voutnom. AT this instant, amplifier 2 releases its output from the low state to the high state and the gate of transistor 3 is connected to the voltage Vbat via the gate resistance Rg, which should normally should cause the immediate blocking of transistor 3. However, as illustrated in Figure 2B, the gate voltage Vg increases only very slowly in due to the high value of the gate resistance Rg, which limits the current delivered, and the high value of the grid capacity Cg. The output stage of amplifier 2 is therefore unable to charge instantly the grid capacity Cg and block the transistor 3. The latter continues to be on and the Vout voltage continues to follow Vbat voltage. As illustrated in Figure 2C, we thus see appear at the regulator output OS voltage spike. This peak of tension can disappear only from an instant t4, when the gate voltage Vg crosses the value Vbat-Vtp ensuring the blocking of transistor 3, and on condition that the load Z consumes current.

La présente invention vise à pallier cet inconvénient.The present invention aims to overcome this disadvantage.

Plus particulièrement, un objectif de la présente invention est de supprimer, ou à tout le moins limiter, l'effet de surtension en régime transitoire à la sortie d'un régulateur de tension sans qu'il soit nécessaire de modifier la structure du transistor de régulation pour diminuer sa capacité de grille.More specifically, an objective of this invention is to remove, or at the very least limit, the effect of overvoltage in transient mode at the output a voltage regulator without the need to modify the structure of the regulation transistor to decrease its grid capacity.

Un autre objectif de la présente invention est également de supprimer ou limiter l'effet de surtension en régime transitoire sans qu'il soit nécessaire d'augmenter le courant maximal pouvant être délivré par la sortie de l'amplificateur de régulation.Another object of the present invention is also to suppress or limit the effect of overvoltage transient without the need increase the maximum current that can be delivered by the output of the control amplifier.

Ces objectifs sont atteints par la prévision d'un régulateur de tension comprenant un transistor MOS de régulation à faible résistance série dont une borne reçoit une tension d'alimentation et dont l'autre borne est reliée à la sortie du régulateur, et un amplificateur dont la sortie pilote la grille du transistor en fonction de l'écart entre une tension de référence et une tension de contre-réaction, le régulateur comprenant un interrupteur dont une borne est reliée à la grille du transistor de régulation et l'autre borne est portée à un potentiel de blocage du transistor de régulation, et des moyens de commande de l'interrupteur, surveillant la sortie du régulateur, agencés pour fermer l'interrupteur lorsque la tension de sortie du régulateur est supérieure à un premier seuil supérieur à la valeur nominale de la tension de sortie.These objectives are achieved by forecasting a voltage regulator comprising a MOS transistor low resistance series control including one terminal receives a supply voltage and whose other terminal is connected to the regulator output, and an amplifier whose output drives the gate of the transistor in function the difference between a reference voltage and a voltage feedback, the regulator comprising a switch, one terminal of which is connected to the grid of the regulating transistor and the other terminal is brought to a blocking potential of the regulation transistor, and switch control means, monitoring the regulator output, arranged to close the switch when the regulator output voltage is higher at a first threshold higher than the nominal value of the output voltage.

Selon un mode de réalisation, les moyens de commande de l'interrupteur sont agencés pour comparer la tension de sortie du régulateur ou une tension proportionnelle à la tension de sortie avec la tension de référence.According to one embodiment, the means of switch control are arranged to compare the regulator output voltage or a voltage proportional to the output voltage with the voltage of reference.

Selon un mode de réalisation, les moyens de commande de l'interrupteur comprennent un comparateur dont la sortie délivre un signal de fermeture de l'interrupteur, le comparateur recevant sur une entrée la tension de référence et sur une autre entrée la tension de sortie ou une tension proportionnelle à la tension de sortie.According to one embodiment, the means of switch control include comparator whose output delivers a closing signal of the switch, the comparator receiving on an input the reference voltage and on another input the voltage output or a voltage proportional to the voltage of exit.

Selon un mode de réalisation, le comparateur présente une hystérésis de commutation choisie de manière que l'interrupteur soit réouvert lorsque la tension de sortie devient inférieure à un second seuil inférieur au premier seuil et supérieur à la valeur nominale de la tension de sortie.According to one embodiment, the comparator has a switching hysteresis chosen so that the switch is reopened when the voltage of output becomes less than a second threshold less than first threshold and higher than the nominal value of the output voltage.

Selon un mode de réalisation, le transistor de régulation est un transistor PMOS et le potentiel de blocage est la tension d'alimentation.According to one embodiment, the transistor regulation is a PMOS transistor and the potential for blocking is the supply voltage.

Selon un mode de réalisation, l'amplificateur comprend un étage de sortie comportant une résistance de grille de valeur trop importante pour que le courant traversant la résistance de grille puisse assurer à lui seul un blocage rapide du transistor de régulation lorsque la tension d'alimentation augmente rapidement.According to one embodiment, the amplifier includes an output stage with a resistance of value grid too large for current crossing the grid resistor can assure it only rapid blocking of the regulation transistor when the supply voltage increases rapidly.

Selon un mode de réalisation, l'interrupteur est un transistor PMOS ayant une résistance drain-source à l'état passant très inférieure à la résistance de grille de l'étage de sortie de l'amplificateur.According to one embodiment, the switch is a PMOS transistor having a drain-source resistance at the passing state much lower than the gate resistance of the amplifier output stage.

La présente invention concerne également un téléphone mobile comprenant une batterie et des circuits radio alimentés par la batterie par l'intermédiaire d'un régulateur de tension selon l'invention.The present invention also relates to a mobile phone including battery and circuits radio powered by the battery through a voltage regulator according to the invention.

La présente invention prévoir également un procédé pour empêcher ou limiter l'apparition d'une surtension à la sortie d'un régulateur de tension lorsque la tension d'alimentation du régulateur augmente rapidement, le régulateur comprenant un transistor MOS de régulation à forte capacité de grille dont la grille est pilotée par un amplificateur délivrant un courant à lui seul insuffisant pour assurer un blocage rapide du transistor de régulation, le procédé comprenant une étape consistant à prévoir un interrupteur connecté entre la grille du transistor de régulation et un potentiel de blocage du transistor de régulation, et une étape consistant à fermer l'interrupteur lorsque la tension de sortie du régulateur devient supérieure à un premier seuil supérieur à la valeur nominale de la tension de sortie, de manière à aider temporairement l'amplificateur à bloquer le transistor de régulation.The present invention also provides a method to prevent or limit the occurrence of a surge to the output of a voltage regulator when the voltage the regulator supply increases rapidly, the regulator comprising a regulation MOS transistor with high grid capacity, the grid of which is controlled by an amplifier delivering current alone insufficient to ensure rapid blocking of the transistor regulation, the method comprising a step consisting of to provide a switch connected between the grid of the regulating transistor and a blocking potential of the regulation transistor, and a step consisting in close the switch when the output voltage of the regulator becomes greater than a first threshold higher than the nominal value of the output voltage, so as to temporarily help the amplifier to block the regulating transistor.

Selon un mode de réalisation, le procédé comprend une étape consistant à réouvrir l'interrupteur lorsque la tension de sortie du régulateur devient inférieure à un second seuil compris entre la valeur nominale de la tension de sortie et le premier seuil.According to one embodiment, the method comprises a step of reopening the switch when the regulator output voltage becomes less than one second threshold between the nominal value of the output voltage and the first threshold.

Ces objets, caractéristiques et avantages ainsi que d'autres de la présente invention seront exposés plus en détail dans la description suivante d'un exemple de réalisation d'un régulateur selon l'invention, faite à titre non limitatif en relation avec les figures jointes, parmi lesquelles :

  • la figure 1 précédemment décrite est le schéma électrique d'un régulateur de tension classique,
  • les figures 2A à 2C représentent des signaux électriques qui illustrent le fonctionnement du régulateur classique en régime transitoire,
  • la figure 3 est le schéma électrique d'un régulateur de tension selon l'invention,
  • les figures 4A à 4C représentent des signaux électriques qui illustrent le fonctionnement du régulateur selon l'invention en régime transitoire, et
  • la figure 5 est le schéma électrique d'un amplificateur présent dans le régulateur de la figure 3.
These objects, characteristics and advantages as well as others of the present invention will be explained in more detail in the following description of an exemplary embodiment of a regulator according to the invention, given without limitation in relation to the attached figures. , among :
  • FIG. 1 previously described is the electrical diagram of a conventional voltage regulator,
  • FIGS. 2A to 2C represent electrical signals which illustrate the operation of the conventional regulator in transient mode,
  • FIG. 3 is the electrical diagram of a voltage regulator according to the invention,
  • FIGS. 4A to 4C represent electrical signals which illustrate the operation of the regulator according to the invention in transient conditions, and
  • FIG. 5 is the electrical diagram of an amplifier present in the regulator of FIG. 3.

La figure 3 représente un régulateur 20 selon l'invention, alimenté ici par une tension Vbat fournie par l'anode d'une batterie 1. Le régulateur 20 comprend comme celui de la figure 1 un amplificateur différentiel 2 dont la sortie commande la grille d'un transistor de régulation 3 de type PMOS. Le drain D du transistor 3 est relié en sortie du régulateur 20 à une capacité de stabilisation Cst agencée en parallèle avec une charge Z. Ces divers éléments sont agencés comme décrit au préambule et désignés par les mêmes références. La tension de sortie Vout est ramenée sur l'entrée positive de l'amplificateur 2 par l'intermédiaire d'un pont diviseur comprenant deux résistances R1, R2. La résistance R2 est ici constituée de deux résistances R21, R22 en série. La relation entre la tension de sortie Vout et la tension de contre-réaction Vfb est ainsi la suivante : (1)   Vout = (R1+R2)Vfb/R2 FIG. 3 represents a regulator 20 according to the invention, supplied here by a voltage Vbat supplied by the anode of a battery 1. The regulator 20 comprises, like that of FIG. 1, a differential amplifier 2 whose output controls the gate d 'a PMOS type regulation transistor 3. The drain D of transistor 3 is connected at the output of regulator 20 to a stabilization capacity Cst arranged in parallel with a load Z. These various elements are arranged as described in the preamble and designated by the same references. The output voltage Vout is brought to the positive input of the amplifier 2 via a divider bridge comprising two resistors R1, R2. Resistor R2 here consists of two resistors R21, R22 in series. The relationship between the output voltage Vout and the feedback voltage Vfb is as follows: (1) Vout = (R1 + R2) Vfb / R2

La tension de référence Vref appliquée sur l'entrée négative de l'amplificateur 2 est par exemple une tension dite de band-gap présentant une bonne stabilité en fonction de la température, générée au moyen de diodes à jonction PN et de miroirs de courant. La tension Vref est ainsi indépendante de la tension Vbat, à la condition bien entendu d'être choisie inférieure à la valeur la plus basse de la tension Vbat.The reference voltage Vref applied to the input negative of amplifier 2 is for example a voltage so-called band-gap with good stability in temperature function, generated by means of diodes PN junction and current mirrors. The voltage Vref is thus independent of the voltage Vbat, on the condition of course to be chosen lower than the value the lower voltage Vbat.

Le fonctionnement du régulateur 20 en régime continu est conforme au régulateur classique. L'amplificateur 2 maintient la tension de contre-réaction Vfb égale à la tension de référence Vref et la tension de sortie nominale Voutnom est égale à : (2)   Voutnom = (R1+R2)Vref/R2 The operation of the regulator 20 in continuous mode conforms to the conventional regulator. Amplifier 2 maintains the feedback voltage Vfb equal to the reference voltage Vref and the nominal output voltage Voutnom is equal to: (2) Voutnom = (R1 + R2) Vref / R2

Selon l'invention, le régulateur 20 comprend un interrupteur anti-surtension 4 connecté entre l'anode de la batterie 1 et la grille G du transistor 3. L'interrupteur 4 est ici un transistor du type PMOS dont la source S reçoit la tension Vbat et dont le drain D est connecté à la grille G du transistor 3. Le rapport W/L longueur sur largeur de grille du transistor 4 est choisi de manière que sa résistance série RdsON à l'état passant soit assez faible, de préférence très inférieure à la résistance de grille Rg de l'étage de sortie de l'amplificateur 2.According to the invention, the regulator 20 comprises a anti-overvoltage switch 4 connected between the anode of battery 1 and gate G of transistor 3. Switch 4 is here a PMOS type transistor of which the source S receives the voltage Vbat and whose drain D is connected to gate G of transistor 3. The W / L ratio length over gate width of transistor 4 is chosen so that its RdsON series resistance in the on state is quite low, preferably much lower than the gate resistance Rg of the output stage of amplifier 2.

Selon l'invention toujours, la grille G du transistor 4 est pilotée par un signal Vos délivré par la sortie d'un comparateur 5. Le comparateur 5 est alimenté par la tension Vbat et reçoit sur son entrée positive la tension Vref et sur son entrée négative une tension VA. La tension VA est prélevée au point milieu du pont diviseur constitué par les deux résistance R21, R22 en série et est ainsi égale à : (3)   VA = R22 Vfb/R2 Selon l'invention, la résistance R21 est petite devant la résistance R22 de sorte que la tension VA est très proche de la tension Vfb. On peut ainsi écrire que : (4)   R21 = x R2 (5)   R22 = (1-x) R2 avec "x" compris entre 0 et 1 et proche de 0, x étant par exemple égal à 0,05.Still according to the invention, the gate G of the transistor 4 is controlled by a signal Vos delivered by the output of a comparator 5. The comparator 5 is supplied by the voltage Vbat and receives on its positive input the voltage Vref and on its input negative a VA voltage. The voltage VA is taken at the midpoint of the divider bridge formed by the two resistors R21, R22 in series and is thus equal to: (3) VA = R22 Vfb / R2 According to the invention, the resistor R21 is small compared to the resistor R22 so that the voltage VA is very close to the voltage Vfb. We can thus write that: (4) R21 = x R2 (5) R22 = (1-x) R2 with "x" between 0 and 1 and close to 0, x being for example equal to 0.05.

Lorsque le régulateur est stabilisé, la tension Va est sensiblement inférieure à la tension Vref. En effet, la tension Vfb est dans ce cas sensiblement égale à Vref et la relation (3) devient : (6)   VA = R22 Vref/R2 soit : (7)   VA = (1-x) Vref avec x inférieur à 1 et proche de 0 comme indiqué ci-dessus, et 1-x inférieur à 1 et proche de 1.When the regulator is stabilized, the voltage Va is significantly lower than the voltage Vref. Indeed, the voltage Vfb is in this case substantially equal to Vref and the relation (3) becomes: (6) VA = R22 Vref / R2 is : (7) VA = (1-x) Vref with x less than 1 and close to 0 as indicated above, and 1-x less than 1 and close to 1.

La tension VA étant inférieure à Vref, la sortie du comparateur 5 est à 1. Le signal Vos est ainsi égal à Vbat et le transistor anti-surtension 4 reste dans l'état bloqué, sa tension grille-source Vgs étant nulle.Since the voltage VA is less than Vref, the output of the comparator 5 is 1. The signal Vos is thus equal to Vbat and the overvoltage transistor 4 remains in the state blocked, its gate-source voltage Vgs being zero.

Le comparateur 5 et le transistor 4 anti-surtension deviennent actifs en régime transitoire, lorsque la tension Vbat remonte brutalement après avoir fortement baissé en raison d'un pic de consommation de courant, par exemple dans la situation exposée au préambule, c'est-à-dire après l'émission d'une salve de données par le circuit radio d'un téléphone mobile. Une telle situation est illustrée sur les figures 2A, 4A, 4B, 4C, qui représentent respectivement le profil de la tension de batterie Vbat, la tension Vg délivrée par l'amplificateur 2 sur la grille du transistor de régulation 3, la tension Vout et la tension Vos de commande du transistor anti-surtension 4.Comparator 5 and anti-overvoltage transistor 4 become active on a transitional basis, when the Vbat tension rises sharply after strongly decreased due to a peak in current consumption, by example in the situation described in the preamble, i.e. after the issuance of a data burst by the mobile phone radio circuit. Such a situation is illustrated in Figures 2A, 4A, 4B, 4C, which respectively represent the voltage profile of Vbat battery, the voltage Vg delivered by the amplifier 2 on the gate of the regulation transistor 3, the voltage Vout and control voltage of the anti-overvoltage transistor 4.

Pendant la chute de la tension Vbat, à compter du temps t1, le régulateur 20 est déséquilibré et passe en mode suiveur, la tension de sortie Vout recopiant la tension Vbat. Pendant cette période, la tension VA continue de baisser et reste ainsi inférieure à la tension Vref, le signal Vos à la sortie du comparateur restant à 1 (Vbat).During the fall of Vbat voltage, from time t1, regulator 20 is unbalanced and goes into follower mode, the output voltage Vout copying the Vbat voltage. During this period, the voltage VA continues to fall and thus remains below the voltage Vref, the signal Vos at the output of the comparator remaining at 1 (Vbat).

A l'instant t2, la tension Vbat remonte brutalement et la tension Vout suit la tension Vbat. A l'instant t3, la tension Vout atteint le point de régulation Voutnom et l'amplificateur 2 bascule sa sortie à l'état haut. Toutefois, comme on l'a expliqué au préambule, l'amplificateur est, par sa conception, incapable de délivrer le courant nécessaire à charger immédiatement la capacité de grille Cg du transistor 3. La tension de sortie Vout continue donc de monter après l'instant t3 et de suivre la tension Vbat, le transistor 3 restant passant.At time t2, the voltage Vbat rises sharply and the voltage Vout follows the voltage Vbat. At time t3, the voltage Vout reaches the regulation point Voutnom and amplifier 2 switches its output to the high state. However, as explained in the preamble, the amplifier is, by design, incapable of supply the necessary current to immediately charge the gate capacity Cg of transistor 3. The voltage of exit Vout therefore continues to rise after time t3 and to follow the voltage Vbat, the transistor 3 remaining passerby.

Selon l'invention, à un instant t5 très proche de l'instant t3, la tension Vout atteint une valeur de seuil Vout1 telle que la tension VA à l'entrée du comparateur 5 devient égale à Vref. A cet instant, la sortie du comparateur 5 bascule à 0 (fig. 4C) et le transistor anti-surtension 4 devient passant. La résistance série RdsON à l'état passant du transistor 4 étant faible, la grille G du transistor de régulation 3 reçoit le courant nécessaire pour charger la capacité de grille Cg et le transistor 3 se bloque quasi instantanément. La tension Vout cesse de monter et redescend vers sa valeur nominale Voutnom (fig. 4B). Selon l'invention, on neutralise ainsi l'apparition du pic de tension OS représenté en figure 2C, caractéristique d'un régulateur classique, en aidant l'amplificateur 2 à bloquer le transistor de régulation 3 au moyen du transistor 4. According to the invention, at a time t5 very close to at time t3, the voltage Vout reaches a threshold value Vout1 such that the voltage VA at the input of comparator 5 becomes equal to Vref. At this moment, the exit of the comparator 5 switches to 0 (fig. 4C) and the transistor surge protector 4 turns on. Series resistance RdsON in the on state of transistor 4 being weak, the gate G of the regulation transistor 3 receives the current necessary to charge the grid capacity Cg and the transistor 3 crashes almost instantly. Voltage You stop going up and down to its nominal value Voutnom (fig. 4B). According to the invention, it thus neutralizes the appearance of the OS voltage peak shown in figure 2C, characteristic of a classic regulator, by helping amplifier 2 to block regulation transistor 3 by means of transistor 4.

En pratique, le seuil Vout1 de déclenchement du transistor 4 peut être défini au moyen du paramètre x mentionné plus haut, qui est fonction des résistances R1, R2, R21 et R22. En effet, la relation entre les tensions Vout et VA est la suivante : (8)   Vout = (R1+R2)VA/R22 En combinant les relations (5) et (8), il vient : (9)   Vout = (R1+R2)VA/(1-x)R2 en remplaçant VA par Vref et Vout par Vout1 dans la relation (9), il vient : (10)   Vout1 = (R1+R2)Vref/(1-x)R2 En combinant la relation (10) et la relation (2), il vient : (11)   Vout1 = Voutnom/(1-x) le terme x étant petit, il vient : (12)   Vout1 ≈ Voutnom + x Voutnom soit : (13)   Vout1 ≈ Voutnom + x (R1+R2)Vref/R2 soit : (14)   Vout1 ≈ Voutnom + K K étant une constante déterminée par les résistances R1, R2, R21, R22 et la valeur de Vref. A titre d'exemple numérique, un régulateur présentant les caractéristiques suivantes :

  • R1 = 500 KΩ,
  • R2 = 500 KΩ,
  • R21 = 25 KΩ,
  • R22 = 475 KΩ,
  • x = 0,05
  • Vref = 1,4 V
  • Voutnom = 2,8 V
    • présente un seuil Vout1 de commutation du transistor anti-surtension 4 égal à 2,835 V. En d'autres termes, le phénomène parasite de surtension est limité dans cet exemple à 0,035 V grâce à la présente invention, soit un pic de tension négligeable au regard de la valeur nominale de la tension de sortie.In practice, the threshold Vout1 for triggering transistor 4 can be defined by means of the parameter x mentioned above, which is a function of resistors R1, R2, R21 and R22. Indeed, the relationship between the voltages Vout and VA is as follows: (8) Vout = (R1 + R2) VA / R22 By combining relations (5) and (8), it comes: (9) Vout = (R1 + R2) VA / (1-x) R2 by replacing VA by Vref and Vout by Vout1 in relation (9), it comes: (10) Vout1 = (R1 + R2) Vref / (1-x) R2 By combining relation (10) and relation (2), it comes: (11) Vout1 = Voutnom / (1-x) the term x being small, it comes: (12) Vout1 ≈ Voutnom + x Voutnom is : (13) Vout1 ≈ Voutnom + x (R1 + R2) Vref / R2 is : (14) Vout1 ≈ Voutnom + K K being a constant determined by the resistors R1, R2, R21, R22 and the value of Vref. As a numerical example, a regulator having the following characteristics:
  • R1 = 500 KΩ,
  • R2 = 500 KΩ,
  • R21 = 25 KΩ,
  • R22 = 475 KΩ,
  • x = 0.05
  • Vref = 1.4 V
  • Voutnom = 2.8 V
    • has a threshold Vout1 for switching the anti-overvoltage transistor 4 equal to 2.835 V. In other words, the parasitic overvoltage phenomenon is limited in this example to 0.035 V thanks to the present invention, ie a voltage peak which is negligible with regard to of the nominal value of the output voltage.

    Bien entendu, selon la valeur Voutnom désirée, le régulateur 20 peut comporter une contre-réaction directe de la tension Vout sur l'entrée de l'amplificateur 2. Dans ce cas, les relations mentionnées ci-dessus sont toujours applicables en considérant que R1 = 0.Of course, depending on the desired Voutnom value, the regulator 20 may have a direct feedback of the voltage Vout on the input of amplifier 2. In this case, the relationships mentioned above are always applicable considering that R1 = 0.

    D'autre part, il est avantageux en pratique que le comparateur 5 présente une hystérésis de commutation afin d'éviter une éventuelle instabilité de la tension Vout au voisinage du seuil Vout1. Dans ce cas, la sortie du comparateur 5 passe à 1 lorsque la tension VA atteint une valeur Vref' sensiblement inférieure à Vref. Cette valeur Vref' correspond, à la sortie du régulateur 20, à une tension Vout2 comprise entre Voutnom et Vout1 (fig. 4B et 4C).On the other hand, it is advantageous in practice for the comparator 5 has a switching hysteresis so avoid possible instability of the voltage Vout at neighborhood of the threshold Vout1. In this case, the output of the comparator 5 changes to 1 when the voltage VA reaches a Vref 'value significantly lower than Vref. This value Vref 'corresponds, at the output of regulator 20, to a voltage Vout2 between Voutnom and Vout1 (fig. 4B and 4C).

    La figure 5 représente à titre d'exemple une structure d'amplificateur 2 à faible consommation, ayant un courant de sortie limité. L'amplificateur comprend en entrée un étage différentiel représenté ici sous la forme d'un bloc 30, recevant les tension Vref et Vfb. L'étage différentiel 30 est polarisé par un générateur de courant 31 qui limite sa consommation. La sortie de l'étage différentiel 30 pilote la grille d'un transistor 32 de type NMOS, connecté entre le noeud de sortie de l'amplificateur 2 et la masse. Le transistor 32 est polarisé sur son drain D par un générateur de courant 33 limitant la consommation de l'étage de sortie à l'état bas. On trouve également dans l'amplificateur 2 la résistance de grille Rg, connectée au noeud de sortie de l'amplificateur et recevant à son autre extrémité la tension Vbat. Ainsi, le transistor 32 tire la sortie de l'amplificateur à la masse et la résistance Rg tire la sortie à la tension d'alimentation Vbat selon la valeur du signal délivré par l'étage différentiel 30.Figure 5 shows by way of example a low consumption amplifier structure 2, having limited output current. The amplifier includes input a differential stage represented here in the form of a block 30, receiving the voltages Vref and Vfb. The floor differential 30 is biased by a current generator 31 which limits its consumption. The exit of the floor differential 30 drives the gate of a transistor 32 NMOS type, connected between the output node of amplifier 2 and ground. The transistor 32 is polarized on its drain D by a current generator 33 limiting the consumption of the output stage to the state low. Also found in amplifier 2 is the gate resistor Rg, connected to the output node of the amplifier and receiving at its other end the Vbat voltage. Thus, transistor 32 draws the output of the amplifier to ground and resistance Rg pulls the output at supply voltage Vbat according to the value of the signal delivered by the differential stage 30.

    Bien que cet exemple d'amplificateur différentiel à faible consommation convienne bien à la réalisation d'un régulateur selon l'invention, il va de soi que la présente invention n'est pas limitée à cet exemple et s'applique de façon générale à tout type d'amplificateur de régulation, dans la mesure où la sortie de l'amplificateur est bridée et n'est pas en mesure d'assurer un blocage rapide du transistor de régulation en régime transitoire.Although this example of differential amplifier to low consumption is well suited to achieving a regulator according to the invention, it goes without saying that the present invention is not limited to this example and generally applies to any type of amplifier regulation, insofar as the output of the amplifier is clamped and is not able ensure rapid blocking of the regulation transistor transient.

    Par ailleurs, on voit sur la figure 5 que le transistor anti-surtension 4 peut être modélisé sous la forme d'un interrupteur parfait 4-1 en série avec une résistance 4-2, qui est ici la résistance série RdsON du transistor. En pratique, une résistance externe peut éventuellement être ajoutée à l'interrupteur 4 pour limiter le courant de charge de la capacité de grille Cg tout en conservant un temps de blocage acceptable en régime transitoire.Furthermore, it can be seen in FIG. 5 that the anti-overvoltage transistor 4 can be modeled under the form of a perfect 4-1 switch in series with a resistor 4-2, which is here the RdsON series resistor of the transistor. In practice, an external resistance can possibly be added to switch 4 to limit the charging current of the gate capacity Cg while maintaining an acceptable blocking time in transitional regime.

    Le régulateur selon l'invention est bien entendu susceptible de diverses applications autres que celle exposée au préambule, et de diverses variantes de réalisation et perfectionnements.The regulator according to the invention is of course susceptible of various applications other than that set out in the preamble, and various variants of realization and improvements.

    Ainsi, dans une variante, le pont diviseur formé par les résistances R21, R22 est supprimé et la tension Vfb est directement appliquée sur une entrée du comparateur 5. Dans ce cas, le comparateur 5 est un comparateur à seuil ε. La sortie du comparateur ne passe à 0 qu'à l'instant où la tension Vfb devient supérieure ou égale à Vref + ε.Thus, in a variant, the dividing bridge formed by resistors R21, R22 is deleted and the voltage Vfb is directly applied to an input of the comparator 5. In this case, comparator 5 is a threshold comparator ε. The comparator output does not pass at 0 only at the moment when the voltage Vfb becomes greater or equal to Vref + ε.

    De façon générale, l'interrupteur anti-surtension selon l'invention doit recevoir un potentiel assurant le blocage du transistor de régulation. L'enseignement exposé dans la présente demande s'applique ainsi à la réalisation d'un régulateur ayant un transistor de régulation de type NMOS, pour la résolution du problème inverse, à savoir la décharge de la capacité de grille du transistor de régulation au blocage de celui-ci quand le courant maximal entrant dans l'étage de sortie de l'amplificateur lors de son passage à 0 est limité. Ce potentiel est par exemple la masse avec un transistor de régulation NMOS.Generally speaking, the anti-surge switch according to the invention must receive a potential ensuring the blocking of the regulation transistor. Teaching set out in this application thus applies to the realization of a regulator having a transistor NMOS type regulation, to solve the problem reverse, namely the discharge of the grid capacity of the regulating transistor at blocking thereof when the maximum current entering the output stage of the amplifier when it goes to 0 is limited. This potential is for example the mass with a transistor of NMOS regulation.

    Claims (12)

    Régulateur de tension (20) comprenant un transistor MOS de régulation (3) à faible résistance série dont une borne (S) reçoit une tension d'alimentation (Vbat) et dont l'autre borne (D) est reliée à la sortie du régulateur, et un amplificateur (2) dont la sortie pilote la grille (G) du transistor (3) en fonction de l'écart entre une tension de référence (Vref) et une tension de contre-réaction (Vfb), caractérisé en ce qu'il comprend : un interrupteur (4) dont une borne (D) est reliée à la grille du transistor de régulation (3) et l'autre borne (S) est portée à un potentiel (Vbat) de blocage du transistor de régulation (3), et des moyens (5, R1, R2, R21, R22) de commande de l'interrupteur (4), surveillant la sortie du régulateur, agencés pour fermer l'interrupteur (4) lorsque la tension de sortie (Vout) du régulateur est supérieure à un premier seuil (Vout1) supérieur à la valeur nominale (Voutnom) de la tension de sortie. Voltage regulator (20) comprising a regulating MOS transistor (3) with low series resistance, one terminal (S) of which receives a supply voltage (Vbat) and the other terminal (D) of which is connected to the output of the regulator , and an amplifier (2) whose output drives the gate (G) of the transistor (3) as a function of the difference between a reference voltage (Vref) and a feedback voltage (Vfb), characterized in that '' it includes: a switch (4) one terminal (D) of which is connected to the gate of the regulation transistor (3) and the other terminal (S) is brought to a potential (Vbat) for blocking the regulation transistor (3), and means (5, R1, R2, R21, R22) for controlling the switch (4), monitoring the output of the regulator, arranged to close the switch (4) when the output voltage (Vout) of the regulator is higher at a first threshold (Vout1) greater than the nominal value (Voutnom) of the output voltage. Régulateur selon la revendication 1, dans lequel les moyens de commande (5, R1, R2, R21, R22) de l'interrupteur (4) sont agencés pour comparer la tension de sortie du régulateur (Vout) ou une tension (VA) proportionnelle à la tension de sortie avec la tension de référence (Vref).The regulator of claim 1, wherein the control means (5, R1, R2, R21, R22) of the switch (4) are arranged to compare the voltage output of the regulator (Vout) or a voltage (VA) proportional to the output voltage with the voltage of reference (Vref). Régulateur selon la revendication 2, dans lequel les moyens de commande de l'interrupteur comprennent un comparateur (5) dont la sortie délivre un signal (Vos) de fermeture de l'interrupteur , le comparateur recevant sur une entrée la tension de référence (Vref) et sur une autre entrée la tension de sortie (Vout) ou une tension (VA) proportionnelle à la tension de sortie.The regulator of claim 2, wherein the switch control means include a comparator (5) whose output delivers a signal (Vos) of closing of the switch, the comparator receiving on an input the reference voltage (Vref) and on a other input the output voltage (Vout) or a voltage (VA) proportional to the output voltage. Régulateur selon la revendication 3, dans lequel le comparateur (5) présente une hystérésis de commutation choisie de manière que l'interrupteur (4) soit réouvert lorsque la tension de sortie (Vout) devient inférieure à un second seuil (Vout2) inférieur au premier seuil (Vout1) et supérieur à la valeur nominale (Voutnom) de la tension de sortie.The regulator of claim 3, wherein the comparator (5) has a switching hysteresis chosen so that the switch (4) is reopened when the output voltage (Vout) drops below a second threshold (Vout2) lower than the first threshold (Vout1) and higher than the nominal value (Voutnom) of the output voltage. Régulateur selon l'une des revendications 1 à 4, dans lequel le transistor de régulation (3) est un transistor PMOS et le potentiel de blocage est la tension d'alimentation (Vbat).Regulator according to one of claims 1 to 4, in which the regulating transistor (3) is a PMOS transistor and the blocking potential is the voltage power supply (Vbat). Régulateur selon la revendication 5, dans lequel l'amplificateur (2) comprend un étage de sortie comportant une résistance de grille (Rg) de valeur trop importante pour que le courant traversant la résistance de grille (Rg) puisse assurer à lui seul un blocage rapide du transistor de régulation (3) lorsque la tension d'alimentation (Vbat) augmente rapidement.The regulator of claim 5, wherein the amplifier (2) includes an output stage with a gate resistance (Rg) of too high a value important so that the current passing through the resistance grid (Rg) alone can block fast regulation transistor (3) when the voltage power supply (Vbat) increases rapidly. Régulateur selon la revendication 6, dans lequel l'interrupteur (4) est un transistor PMOS ayant une résistance drain-source (RdsON) à l'état passant très inférieure à la résistance de grille (Rg) de l'étage de sortie de l'amplificateur.The regulator of claim 6, wherein the switch (4) is a PMOS transistor having a drain-source resistance (RdsON) in the very passing state lower than the gate resistance (Rg) of the stage of amplifier output. Téléphone mobile comprenant une batterie (1) et des circuits radio alimentés par la batterie par l'intermédiaire d'un régulateur de tension (20) selon l'une des revendications 1 à 7.Mobile phone including a battery (1) and radio circuits powered by the battery by via a voltage regulator (20) according to one of claims 1 to 7. Procédé pour empêcher ou limiter l'apparition d'une surtension à la sortie d'un régulateur de tension (20) lorsque la tension d'alimentation (Vbat) du régulateur augmente rapidement, le régulateur (20) comprenant un transistor MOS de régulation (3) à forte capacité de grille (Cg) dont la grille est pilotée par un amplificateur (2) délivrant un courant à lui seul insuffisant pour assurer un blocage rapide du transistor de régulation (3), procédé caractérisé en ce qu'il comprend une étape consistant à prévoir un interrupteur (4) connecté entre la grille du transistor de régulation (3) et un potentiel de blocage (Vbat) du transistor de régulation, et une étape consistant à fermer l'interrupteur lorsque la tension de sortie du régulateur devient supérieure à un premier seuil (Vout1) supérieur à la valeur nominale (Voutnom) de la tension de sortie, de manière à aider temporairement l'amplificateur (2) à bloquer le transistor de régulation (3).Method for preventing or limiting the occurrence of an overvoltage at the output of a voltage regulator (20) when the supply voltage (Vbat) of the regulator increases rapidly, the regulator (20) comprising a regulating MOS transistor ( 3) with a high gate capacity (Cg), the gate of which is controlled by an amplifier (2) delivering insufficient current alone to ensure rapid blocking of the regulation transistor (3), a method characterized in that it comprises a step consisting in providing a switch (4) connected between the gate of the regulating transistor (3) and a blocking potential (Vbat) of the regulating transistor, and a step consisting in closing the switch when the output voltage of the regulator becomes greater than a first threshold (Vout1) greater than the nominal value (Voutnom) of the output voltage, so as to temporarily help the amplifier (2) to block the regulation transistor (3). Procédé selon la revendication 9, comprenant une étape consistant à réouvrir l'interrupteur (4) lorsque la tension de sortie du régulateur devient inférieure à un second seuil (Vout2) compris entre la valeur nominale (Voutnom) de la tension de sortie et le premier seuil (Vout1).The method of claim 9, comprising a step consisting in reopening the switch (4) when the regulator output voltage becomes less than a second threshold (Vout2) between the nominal value (Voutnom) of the output voltage and the first threshold (Vout1). Procédé selon l'une des revendications 9 et 10, dans lequel l'interrupteur (4) est piloté par un comparateur (5) recevant en entrée une tension de référence (Vref) du régulateur et une tension (VA) proportionnelle à la tension de sortie (Vout) du régulateur.Method according to one of claims 9 and 10, in which the switch (4) is controlled by a comparator (5) receiving a voltage of regulator reference (Vref) and a voltage (VA) proportional to the output voltage (Vout) of the regulator. Procédé selon l'une des revendications 9 à 11, dans lequel le transistor de régulation (3) est un transistor PMOS et le potentiel de blocage est la tension d'alimentation (Vbat).Method according to one of claims 9 to 11, in which the regulating transistor (3) is a PMOS transistor and the blocking potential is the voltage power supply (Vbat).
    EP01108258A 2000-04-12 2001-03-31 Linear regulator with low over-voltage in transient-state Expired - Lifetime EP1148405B1 (en)

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    EP1148405B1 (en) 2006-06-07
    DE60120270D1 (en) 2006-07-20
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    US6388433B2 (en) 2002-05-14
    FR2807847A1 (en) 2001-10-19

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