EP1083471A1 - Voltage regulator - Google Patents

Voltage regulator Download PDF

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Publication number
EP1083471A1
EP1083471A1 EP00119687A EP00119687A EP1083471A1 EP 1083471 A1 EP1083471 A1 EP 1083471A1 EP 00119687 A EP00119687 A EP 00119687A EP 00119687 A EP00119687 A EP 00119687A EP 1083471 A1 EP1083471 A1 EP 1083471A1
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Prior art keywords
switch
voltage
reg
reference voltage
regulation
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EP00119687A
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German (de)
French (fr)
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EP1083471B1 (en
Inventor
Bruno Gailhard
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STMicroelectronics SA
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STMicroelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor

Definitions

  • the present invention relates to a regulator of voltage including a capacitor delivering on its anode a regulated voltage, a regulation switch to connect the capacitor to a voltage source and regulating means arranged to close the switch when the regulated voltage is less than a first reference voltage.
  • Voltage regulators find various electronics applications, for example example to deliver a regulated voltage used to electrically supply the ports of a microprocessor.
  • FIG. 1 represents a conventional voltage regulator 1, incorporated in a microprocessor 2.
  • the microprocessor 2 is powered by an electric battery 3 of internal resistance r i , delivering a voltage V DD .
  • the regulator 1 comprises an external capacitor C REG delivering on its anode a regulated voltage V REG .
  • the anode of the capacitor C REG is connected to the anode of the battery 3 by means of a regulation switch SW 1 having a series resistance R 1 zero or of low value.
  • the switch SW1 is controlled by the output of a follower circuit CP receiving on its positive input the regulated voltage V REG and on its negative input a reference voltage V REF .
  • the voltage V REF is conventionally a so-called band-gap voltage having good stability as a function of the temperature, generated by means of PN junction diodes and current mirrors.
  • the follower circuit CP is controlled by a PDW (Power-Down) signal and the anode of the capacitor C REG is connected to ground by a switch SW OFF controlled by the PDW signal.
  • PDW Power-Down
  • the follower circuit CP is blocked and the switch SW OFF is closed. Regulator 1 is stopped and capacitor C REG is discharged.
  • the disadvantage of such a regulator is that it has a high current consumption at start-up.
  • the capacitor C REG is discharged and the voltage V REG is zero.
  • the output of the follower circuit CP goes to 0 and the switch SW 1 closes.
  • the application of the voltage V DD on the capacitor C REG causes a strong current draw and a significant drop in the supply voltage V DD of the microprocessor 2, due to the internal resistance r i of the battery 3. If at at the same time other elements of the microprocessor 2 consume a non-negligible current, it may happen that the voltage V DD becomes lower than the minimum operating voltage of the microprocessor 2, so that the microprocessor 2 is blocked.
  • the present invention aims to overcome this disadvantage.
  • the present invention aims to limit the starting current of a regulator without increase the series resistance of the switch regulation.
  • the present invention provides a regulator of the type described above, comprising at least a ballast switch in parallel with the switch regulating device, and means for opening the switch at least the ballast switch during a regulator start-up phase, until the capacitor is at least partially charged.
  • the regulator includes means for opening the switch regulation and close the ballast switch when the regulated voltage is less than a second voltage of reference lower than the first reference voltage.
  • the second voltage reference is a fraction of the first voltage of reference.
  • a common signal of control of the regulation switch and the ballast switch is applied to the regulation via a switch inhibitor.
  • the switch inhibitor is controlled by a signal delivered by a comparator receiving as input the regulated voltage and a second reference voltage lower than the first reference voltage.
  • the regulator includes a follower circuit receiving the input voltage regulated and the first reference voltage, the circuit follower delivering a regulation signal, and a comparator receiving as input the regulated voltage and a second reference voltage lower than the first reference voltage.
  • the regulation signal is applied to the switch control input ballast and is applied to the control input of the regulation switch via a inhibitor switch.
  • the comparator output is applied to the switch control input inhibitor.
  • the switch ballast is a MOS transistor comprising a resistor significant intrinsic.
  • the voltage source is an electric battery.
  • the present invention also relates to a circuit integrated, in particular a microprocessor, comprising a regulator according to the invention.
  • FIG. 2 represents a voltage regulator according to the invention.
  • the regulator 10 conventionally comprises a capacitor C REG whose anode is connected to a voltage source V DD by a regulation switch SW1, here a PMOS transistor, comprising a zero or low value series resistance R1.
  • the anode of the capacitor C REG which delivers a regulated voltage V REG , is connected to ground by a switch SW OFF controlled by a reset signal PDW (Power-Down).
  • a ballast switch SW2 is connected in parallel with the switch SW1.
  • the switch SW2 has a non-negligible series resistance R2, for example of the order of a few hundred ohms.
  • the switch SW2 is here a PMOS transistor and the resistance R2 is the intrinsic resistance of the transistor, that is to say its series resistance (R ON ) with the passing being.
  • the value of the resistance R2 is thus determined by the choice of the ratio W / L between the width W and the length L of the gate of the transistor.
  • the switches SW1, SW2 are controlled by a circuit 11, shown here in the form of a block, controlled by the signal PDW.
  • the circuit 11 receives as input the voltage V REG , a first reference voltage V REF1 and a second reference voltage V REF2 .
  • the voltage V REF2 is less than V REF1 and is for example equal to 0.75 V REF1 .
  • the circuit 11 delivers a signal S1 for controlling the switch SW1 and a signal S2 for controlling the switch SW2 (the signals S1, S2 being applied here to the gates of the PMOS transistors).
  • the circuit 11 When the PDW signal is at 1, the circuit 11 is blocked and the switch SW OFF is closed. The capacitor C REG is discharged and the voltage V REG is zero. When the PDW signal is set to 0, the circuit 11 starts and the capacitor C REG charges.
  • the operation of regulator 10 and circuit 11 is described in table 1 below.
  • the switches SW1, SW2 being here PMOS transistors, the active value of the signals S1, S2 corresponding to the closing of the switches SW1, SW2 (on state) is the value 0 (gate of the transistors to ground). When the signals S1, S2 are at 1 (voltage V DD ), the switches are open (transistors in the off state).
  • V REG S1 SW1 S2 SW2 (E1) V REG ⁇ V REF2 1 open 0 closed (E2) V REF2 ⁇ V REG ⁇ V REF1 0 closed 0 or 1 closed or open (E3) V REG > V REF1 1 open 1 open
  • the capacitor C REG is charged in two periods E1, E2.
  • the ballast switch SW2 is closed and the regulation switch SW1 is open.
  • the capacitor C REG is charged via the ballast switch SW2 and the starting current is limited by the resistor R2. The risk of seeing the supply voltage V DD decrease significantly is thus eliminated, in particular when the voltage V DD is delivered by an electric battery or a voltage generator having a significant internal resistance.
  • the period E2 occurs when the voltage V REG exceeds the threshold V REF2 .
  • the switch SW1 closes and the charge cycle of the capacitor C REG ends quickly since the resistance R1 is zero or of low value.
  • the ballast switch SW2 can, indifferently, be kept open or closed.
  • the regulator 10 When the capacitor C REG is charged, the regulator 10 operates in a conventional manner, the regulation switch SW1 being closed (period E2) or open (period E3) depending on whether the voltage V REG is less than or greater than V REF1 .
  • the voltage V REG is thus controlled in the vicinity of V REF1 with alternation of the periods E2 and E3.
  • the ballast switch SW2 During periods of E3 overshoot, the ballast switch SW2 is always open.
  • FIG. 3 An advantageous embodiment of the circuit 11 is shown in FIG. 3.
  • the regulator 10 is shown incorporated in an integrated circuit 20, for example a microprocessor, and the voltage V DD is delivered by an electric battery 21 of internal resistance r i .
  • the circuit 11 includes an operational amplifier C1 arranged in a follower circuit and a comparator CP2.
  • the follower circuit CP1 and the comparator CP2 are controlled by the signal PDW.
  • the follower circuit CP1 receives on its negative input the voltage V REF1 and on its positive input the regulated voltage V REG .
  • the output of the follower circuit CP1 delivers the signal S2 which is applied to the control input of the switch SW2.
  • the comparator CP2 receives on its positive input the voltage V REF2 and on its negative input the voltage V REG .
  • the voltage V REF2 is obtained here by dividing the voltage V REF1 by means of a divider bridge comprising two resistors r a , r b .
  • the output of the comparator CP2 delivers a signal S3 which is applied to the control input of a switch SW3, here a PMOS transistor, as well as to the input of an inverting gate INV1.
  • the output of gate INV1 is connected to the control input of a switch SW4, here a PMOS transistor.
  • the input of the switch SW4 (source of the transistor) receives the voltage V DD and the input of the switch SW3 receives the signal S2.
  • the outputs of switches SW3 and SW4 are connected together and deliver the signal S1 which is applied to the control input of switch SW1.
  • circuit 11 The operation of circuit 11, described by table 2 below, is equivalent to the operation described by table 1 above.
  • the signal S1 is equal to 0 and the signal S3 equal to 1.
  • the ballast switch SW2 is closed, the switch SW3 open (transistor blocked) and the switch SW4 closed.
  • Signal S1 is at 1 (voltage V DD ) and the regulation switch SW1 is kept open.
  • the signal S2 remains at 0, the signal S3 goes to 0, the switch SW3 closes and the switch SW4 opens.
  • the signal S1 copies the signal S2 via the switch SW3 and the regulation switch SW1 closes.
  • V REG S2 SW2 S3 SW3 SW4 S1 SW1 (E1) V REG ⁇ V REF2 0 closed 1 open closed 1 open (E2) V REF2 ⁇ V REG ⁇ V REF1 0 closed 0 closed open 0 closed (E3) V REG > V REF1 1 open 0 closed open 1 open
  • the switch SW3 is an inhibitor switch allowing, during the first charge period E1, not to transmit to the switch SW1 the regulation signal S2, so that the switch SW1 does not close.
  • the switch SW4 is an auxiliary element to prevent the gate of the switch transistor SW1 be brought to a floating potential (high impedance) when the switch SW3 is open.
  • the operating mode of switches used which may be of the type normally open, normally closed type, or type not accepting an undefined signal on the input of ordered.
  • This embodiment of the circuit 11 can also be the subject of various variants with regard to the control of the inhibitor switch SW3.
  • the signal S3 can be delivered by a timer which is activated at the start of the regulator 10, or be delivered by the microprocessor 20 after execution of a timer program.
  • the regulation switch SW1 remains open until the signal S3 is set to 0 by the timer or the microprocessor.
  • the duration of the time delay must be calculated according to the capacity of the capacitor C REG .
  • This embodiment of the circuit 11 however has the advantage of guaranteeing an automatic commissioning of the regulation switch SW1 when the threshold V REF2 is reached, whatever the capacity C REG and without it being necessary to generate a time delay signal by means of a timer or a program.
  • the signal S3 delivered by the comparator CP2 can be used by the microprocessor to monitor the state of the regulator 10. For example, the change to 1 of the signal S1 during operation is representative of an overload of the regulator.
  • the signal S3 can be logically combined with other signals emitted by the microprocessor before being applied to the inhibitor switch SW3, so that the microprocessor can force in the open or closed state l 'regulator switch SW1 if necessary.
  • the resistance R2 is the intrinsic resistance of the ballast switch SW2
  • ballast switch can designate, in the description and the claims, a switch of zero resistance connected in series with a resistor R2, or an intrinsic resistance switch R2 a connected in series with an additional resistance R2 b .

Abstract

A regulated voltage (Vreg) is delivered by a regulating capacitor (Creg), which is connected to a supply (Vdd) through a main switch (SW1) and a ballast switch (SW2) with resistance (R2). A regulating unit control (11) closes the ballast switch and opens the main switch when the regulated voltage is less than a first lower reference (Vref2). At higher voltages the main switch regulates on the higher reference voltage (Vref1).

Description

La présente invention concerne un régulateur de tension comprenant un condensateur délivrant sur son anode une tension régulée, un interrupteur de régulation pour connecter le condensateur à une source de tension et des moyens de régulation agencés pour fermer l'interrupteur quand la tension régulée est inférieure à une première tension de référence.The present invention relates to a regulator of voltage including a capacitor delivering on its anode a regulated voltage, a regulation switch to connect the capacitor to a voltage source and regulating means arranged to close the switch when the regulated voltage is less than a first reference voltage.

Les régulateurs de tension trouvent diverses applications dans le domaine de l'électronique, par exemple pour délivrer une tension régulée servant à alimenter électriquement les ports d'un microprocesseur.Voltage regulators find various electronics applications, for example example to deliver a regulated voltage used to electrically supply the ports of a microprocessor.

La figure 1 représente un régulateur de tension classique 1, incorporé dans un microprocesseur 2. Le microprocesseur 2 est alimenté par une pile électrique 3 de résistance interne ri, délivrant une tension VDD. Le régulateur 1 comprend un condensateur externe CREG délivrant sur son anode une tension régulée VREG. L'anode du condensateur CREG est reliée à l'anode de la pile 3 par l'intermédiaire d'un interrupteur de régulation SW1 présentant une résistance série R1 nulle ou de faible valeur. L'interrupteur SW1 est piloté par la sortie d'un circuit suiveur CP recevant sur son entrée positive la tension régulée VREG et sur son entrée négative une tension de référence VREF. La tension VREF est classiquement une tension dite de band-gap présentant une bonne stabilité en fonction de la température, générée au moyen de diodes à jonction PN et de miroirs de courant. Le circuit suiveur CP est contrôlé par un signal PDW (Power-Down) et l'anode du condensateur CREG est reliée à la masse par un interrupteur SWOFF piloté par le signal PDW. Lorsque le signal PDW est égal à 1, le circuit suiveur CP est bloqué et l'interrupteur SWOFF est fermé. Le régulateur 1 est à l'arrêt et le condensateur CREG est déchargé.FIG. 1 represents a conventional voltage regulator 1, incorporated in a microprocessor 2. The microprocessor 2 is powered by an electric battery 3 of internal resistance r i , delivering a voltage V DD . The regulator 1 comprises an external capacitor C REG delivering on its anode a regulated voltage V REG . The anode of the capacitor C REG is connected to the anode of the battery 3 by means of a regulation switch SW 1 having a series resistance R 1 zero or of low value. The switch SW1 is controlled by the output of a follower circuit CP receiving on its positive input the regulated voltage V REG and on its negative input a reference voltage V REF . The voltage V REF is conventionally a so-called band-gap voltage having good stability as a function of the temperature, generated by means of PN junction diodes and current mirrors. The follower circuit CP is controlled by a PDW (Power-Down) signal and the anode of the capacitor C REG is connected to ground by a switch SW OFF controlled by the PDW signal. When the PDW signal is equal to 1, the follower circuit CP is blocked and the switch SW OFF is closed. Regulator 1 is stopped and capacitor C REG is discharged.

L'inconvénient d'un tel régulateur est de présenter une forte consommation de courant au démarrage. Ainsi, lorsque le signal PDW est mis à 0, le condensateur CREG est déchargé et la tension VREG est nulle. La sortie du circuit suiveur CP passe à 0 et l'interrupteur SW1 se ferme. L'application de la tension VDD sur le condensateur CREG provoque un fort appel de courant et une chute importante de la tension d'alimentation VDD du microprocesseur 2, en raison de la résistance interne ri de la pile 3. Si au même instant d'autres éléments du microprocesseur 2 consomment un courant non négligeable, il peut se produire que la tension VDD devienne inférieure à la tension minimale de fonctionnement du microprocesseur 2, de sorte que le microprocesseur 2 se bloque.The disadvantage of such a regulator is that it has a high current consumption at start-up. Thus, when the PDW signal is set to 0, the capacitor C REG is discharged and the voltage V REG is zero. The output of the follower circuit CP goes to 0 and the switch SW 1 closes. The application of the voltage V DD on the capacitor C REG causes a strong current draw and a significant drop in the supply voltage V DD of the microprocessor 2, due to the internal resistance r i of the battery 3. If at at the same time other elements of the microprocessor 2 consume a non-negligible current, it may happen that the voltage V DD becomes lower than the minimum operating voltage of the microprocessor 2, so that the microprocessor 2 is blocked.

La présente invention vise à pallier cet inconvénient.The present invention aims to overcome this disadvantage.

Plus particulièrement, la présente invention vise à limiter le courant de démarrage d'un régulateur sans augmenter la résistance série de l'interrupteur de régulation.More particularly, the present invention aims to limit the starting current of a regulator without increase the series resistance of the switch regulation.

A cet effet, la présente invention prévoit un régulateur du type décrit ci-dessus, comprenant au moins un interrupteur ballast en parallèle avec l'interrupteur de régulation, et des moyens pour ouvrir l'interrupteur de régulation et fermer l'interrupteur ballast au moins pendant une phase de démarrage du régulateur, jusqu'à ce que le condensateur soit au moins partiellement chargé.To this end, the present invention provides a regulator of the type described above, comprising at least a ballast switch in parallel with the switch regulating device, and means for opening the switch at least the ballast switch during a regulator start-up phase, until the capacitor is at least partially charged.

Selon un mode de réalisation, le régulateur comprend des moyens pour ouvrir l'interrupteur de régulation et fermer l'interrupteur ballast quand la tension régulée est inférieure à une deuxième tension de référence inférieure à la première tension de référence. According to one embodiment, the regulator includes means for opening the switch regulation and close the ballast switch when the regulated voltage is less than a second voltage of reference lower than the first reference voltage.

Selon un mode de réalisation, la deuxième tension de référence est une fraction de la première tension de référence.According to one embodiment, the second voltage reference is a fraction of the first voltage of reference.

Selon un mode de réalisation, un signal commun de commande de l'interrupteur de régulation et de l'interrupteur ballast est appliqué à l'interrupteur de régulation par l'intermédiaire d'un interrupteur inhibiteur.According to one embodiment, a common signal of control of the regulation switch and the ballast switch is applied to the regulation via a switch inhibitor.

Selon un mode de réalisation, l'interrupteur inhibiteur est piloté par un signal délivré par un comparateur recevant en entrée la tension régulée et une deuxième tension de référence inférieure à la première tension de référence.According to one embodiment, the switch inhibitor is controlled by a signal delivered by a comparator receiving as input the regulated voltage and a second reference voltage lower than the first reference voltage.

Selon un mode de réalisation, le régulateur comprend un circuit suiveur recevant en entrée la tension régulée et la première tension de référence, le circuit suiveur délivrant un signal de régulation, et un comparateur recevant en entrée la tension régulée et une deuxième tension de référence inférieure à la première tension de référence. Le signal de régulation est appliqué sur l'entrée de commande de l'interrupteur ballast et est appliqué sur l'entrée de commande de l'interrupteur de régulation par l'intermédiaire d'un interrupteur inhibiteur. La sortie du comparateur est appliquée sur l'entrée de commande de l'interrupteur inhibiteur.According to one embodiment, the regulator includes a follower circuit receiving the input voltage regulated and the first reference voltage, the circuit follower delivering a regulation signal, and a comparator receiving as input the regulated voltage and a second reference voltage lower than the first reference voltage. The regulation signal is applied to the switch control input ballast and is applied to the control input of the regulation switch via a inhibitor switch. The comparator output is applied to the switch control input inhibitor.

Selon un mode de réalisation, l'interrupteur ballast est un transistor MOS comprenant une résistance intrinsèque non négligeable.According to one embodiment, the switch ballast is a MOS transistor comprising a resistor significant intrinsic.

Selon un mode de réalisation, la source de tension est une pile électrique.According to one embodiment, the voltage source is an electric battery.

La présente invention concerne également un circuit intégré, notamment un microprocesseur, comprenant un régulateur selon l'invention.The present invention also relates to a circuit integrated, in particular a microprocessor, comprising a regulator according to the invention.

Ces objets, caractéristiques et avantages de la présente invention seront exposés plus en détail dans la description suivante d'un régulateur de tension selon l'invention, en relation avec les figures jointes parmi lesquelles :

  • la figure 1 précédemment décrite est le schéma électrique d'un régulateur de tension classique,
  • la figure 2 est le schéma de principe d'un régulateur de tension selon l'invention, et
  • la figure 3 est le schéma électrique d'un mode de réalisation d'un régulateur de tension selon l'invention.
These objects, characteristics and advantages of the present invention will be explained in more detail in the following description of a voltage regulator according to the invention, in relation to the attached figures among which:
  • FIG. 1 previously described is the electrical diagram of a conventional voltage regulator,
  • FIG. 2 is the block diagram of a voltage regulator according to the invention, and
  • Figure 3 is the electrical diagram of an embodiment of a voltage regulator according to the invention.

La figure 2 représente un régulateur de tension selon l'invention. Le régulateur 10 comprend de façon classique un condensateur CREG dont l'anode est reliée à une source de tension VDD par un interrupteur de régulation SW1, ici un transistor PMOS, comportant une résistance série R1 nulle ou de faible valeur. L'anode du condensateur CREG, qui délivre une tension régulée VREG, est reliée à la masse par un interrupteur SWOFF piloté par un signal de remise à zéro PDW (Power-Down).FIG. 2 represents a voltage regulator according to the invention. The regulator 10 conventionally comprises a capacitor C REG whose anode is connected to a voltage source V DD by a regulation switch SW1, here a PMOS transistor, comprising a zero or low value series resistance R1. The anode of the capacitor C REG , which delivers a regulated voltage V REG , is connected to ground by a switch SW OFF controlled by a reset signal PDW (Power-Down).

Selon l'invention, un interrupteur ballast SW2 est connecté en parallèle avec l'interrupteur SW1. L'interrupteur SW2 présente une résistance série R2 non négligeable, par exemple de l'ordre de quelques centaines d'ohms. L'interrupteur SW2 est ici un transistor PMOS et la résistance R2 est la résistance intrinsèque du transistor, c'est-à-dire sa résistance série (RON) à l'étant passant. La valeur de la résistance R2 est ainsi déterminée par le choix du rapport W/L entre la largeur W et la longueur L de la grille du transistor.According to the invention, a ballast switch SW2 is connected in parallel with the switch SW1. The switch SW2 has a non-negligible series resistance R2, for example of the order of a few hundred ohms. The switch SW2 is here a PMOS transistor and the resistance R2 is the intrinsic resistance of the transistor, that is to say its series resistance (R ON ) with the passing being. The value of the resistance R2 is thus determined by the choice of the ratio W / L between the width W and the length L of the gate of the transistor.

Les interrupteurs SW1, SW2 sont pilotés par un circuit 11, représenté ici sous forme de bloc, contrôlé par le signal PDW. Le circuit 11 reçoit en entrée la tension VREG, une première tension de référence VREF1 et une deuxième tension de référence VREF2. La tension VREF2 est inférieure à VREF1 et est par exemple égale à 0,75 VREF1. Le circuit 11 délivre un signal S1 de commande de l'interrupteur SW1 et un signal S2 de commande de l'interrupteur SW2 (les signaux S1, S2 étant ici appliqués sur les grilles des transistors PMOS).The switches SW1, SW2 are controlled by a circuit 11, shown here in the form of a block, controlled by the signal PDW. The circuit 11 receives as input the voltage V REG , a first reference voltage V REF1 and a second reference voltage V REF2 . The voltage V REF2 is less than V REF1 and is for example equal to 0.75 V REF1 . The circuit 11 delivers a signal S1 for controlling the switch SW1 and a signal S2 for controlling the switch SW2 (the signals S1, S2 being applied here to the gates of the PMOS transistors).

Lorsque le signal PDW est à 1, le circuit 11 est bloqué et l'interrupteur SWOFF est fermé. Le condensateur CREG est déchargé et la tension VREG est nulle. Lorsque le signal PDW est mis à 0, le circuit 11 démarre et le condensateur CREG se charge. Le fonctionnement du régulateur 10 et du circuit 11 est décrit par le tableau 1 ci-après. Les interrupteurs SW1, SW2 étant ici des transistors PMOS, la valeur active des signaux S1, S2 correspondant à la fermeture des interrupteurs SW1, SW2 (état passant) est la valeur 0 (grille des transistors à la masse). Lorsque les signaux S1, S2 sont à 1 (tension VDD), les interrupteurs sont ouverts (transistors dans l'état bloqué). VREG S1 SW1 S2 SW2 (E1) VREG < VREF2 1 ouvert 0 fermé (E2) VREF2 < VREG < VREF1 0 fermé 0 ou 1 fermé ou ouvert (E3) VREG > VREF1 1 ouvert 1 ouvert When the PDW signal is at 1, the circuit 11 is blocked and the switch SW OFF is closed. The capacitor C REG is discharged and the voltage V REG is zero. When the PDW signal is set to 0, the circuit 11 starts and the capacitor C REG charges. The operation of regulator 10 and circuit 11 is described in table 1 below. The switches SW1, SW2 being here PMOS transistors, the active value of the signals S1, S2 corresponding to the closing of the switches SW1, SW2 (on state) is the value 0 (gate of the transistors to ground). When the signals S1, S2 are at 1 (voltage V DD ), the switches are open (transistors in the off state). V REG S1 SW1 S2 SW2 (E1) V REG <V REF2 1 open 0 closed (E2) V REF2 <V REG <V REF1 0 closed 0 or 1 closed or open (E3) V REG > V REF1 1 open 1 open

Ainsi, au démarrage du régulateur 10, le condensateur CREG se charge en deux périodes E1, E2. Pendant la période E1, l'interrupteur ballast SW2 est fermé et l'interrupteur de régulation SW1 est ouvert. La charge du condensateur CREG s'effectue par l'intermédiaire de l'interrupteur ballast SW2 et le courant de démarrage est limité par la résistance R2. Le risque de voir la tension d'alimentation VDD diminuer fortement est ainsi supprimé, notamment lorsque la tension VDD est délivrée par une pile électrique ou un générateur de tension ayant une résistance interne non négligeable.Thus, at the start of the regulator 10, the capacitor C REG is charged in two periods E1, E2. During period E1, the ballast switch SW2 is closed and the regulation switch SW1 is open. The capacitor C REG is charged via the ballast switch SW2 and the starting current is limited by the resistor R2. The risk of seeing the supply voltage V DD decrease significantly is thus eliminated, in particular when the voltage V DD is delivered by an electric battery or a voltage generator having a significant internal resistance.

La période E2 intervient quand la tension VREG dépasse le seuil VREF2. L'interrupteur SW1 se ferme et le cycle de charge du condensateur CREG se termine rapidement puisque la résistance R1 est nulle ou de faible valeur. Pendant la période E2, l'interrupteur ballast SW2 peut, indifféremment, être maintenu ouvert ou fermé.The period E2 occurs when the voltage V REG exceeds the threshold V REF2 . The switch SW1 closes and the charge cycle of the capacitor C REG ends quickly since the resistance R1 is zero or of low value. During the period E2, the ballast switch SW2 can, indifferently, be kept open or closed.

Lorsque le condensateur CREG est chargé, le régulateur 10 fonctionne de façon classique, l'interrupteur de régulation SW1 étant fermé (période E2) ou ouvert (période E3) selon que la tension VREG est inférieure ou supérieure à VREF1. La tension VREG est ainsi asservie au voisinage de VREF1 avec alternance des périodes E2 et E3. Pendant les périodes de dépassement E3, l'interrupteur ballast SW2 est toujours ouvert.When the capacitor C REG is charged, the regulator 10 operates in a conventional manner, the regulation switch SW1 being closed (period E2) or open (period E3) depending on whether the voltage V REG is less than or greater than V REF1 . The voltage V REG is thus controlled in the vicinity of V REF1 with alternation of the periods E2 and E3. During periods of E3 overshoot, the ballast switch SW2 is always open.

Un mode de réalisation avantageux du circuit 11 est représenté sur la figure 3. De façon non limitative, le régulateur 10 est représenté incorporé dans un circuit intégré 20, par exemple un microprocesseur, et la tension VDD est délivrée par une pile électrique 21 de résistance interne ri.An advantageous embodiment of the circuit 11 is shown in FIG. 3. In a nonlimiting manner, the regulator 10 is shown incorporated in an integrated circuit 20, for example a microprocessor, and the voltage V DD is delivered by an electric battery 21 of internal resistance r i .

Le circuit 11 comprend un amplificateur opérationnel C1 agencé en circuit suiveur et un comparateur CP2. Le circuit suiveur CP1 et le comparateur CP2 sont contrôlés par le signal PDW. Le circuit suiveur CP1 reçoit sur son entrée négative la tension VREF1 et sur son entrée positive la tension régulée VREG. La sortie du circuit suiveur CP1 délivre le signal S2 qui est appliqué sur l'entrée de commande de l'interrupteur SW2. Le comparateur CP2 reçoit sur son entrée positive la tension VREF2 et sur son entrée négative la tension VREG. La tension VREF2 est obtenue ici par division de la tension VREF1 au moyen d'un pont diviseur comprenant deux résistances ra, rb. La sortie du comparateur CP2 délivre un signal S3 qui est appliqué sur l'entrée de commande d'un interrupteur SW3, ici un transistor PMOS, ainsi qu'à l'entrée d'une porte inverseuse INV1. La sortie de la porte INV1 est connectée à l'entrée de commande d'un interrupteur SW4, ici un transistor PMOS. L'entrée de l'interrupteur SW4 (source du transistor) reçoit la tension VDD et l'entrée de l'interrupteur SW3 reçoit le signal S2. Les sorties des interrupteurs SW3 et SW4 (drains) sont connectées ensemble et délivrent le signal S1 qui est appliqué sur l'entrée de commande de l'interrupteur SW1.The circuit 11 includes an operational amplifier C1 arranged in a follower circuit and a comparator CP2. The follower circuit CP1 and the comparator CP2 are controlled by the signal PDW. The follower circuit CP1 receives on its negative input the voltage V REF1 and on its positive input the regulated voltage V REG . The output of the follower circuit CP1 delivers the signal S2 which is applied to the control input of the switch SW2. The comparator CP2 receives on its positive input the voltage V REF2 and on its negative input the voltage V REG . The voltage V REF2 is obtained here by dividing the voltage V REF1 by means of a divider bridge comprising two resistors r a , r b . The output of the comparator CP2 delivers a signal S3 which is applied to the control input of a switch SW3, here a PMOS transistor, as well as to the input of an inverting gate INV1. The output of gate INV1 is connected to the control input of a switch SW4, here a PMOS transistor. The input of the switch SW4 (source of the transistor) receives the voltage V DD and the input of the switch SW3 receives the signal S2. The outputs of switches SW3 and SW4 (drains) are connected together and deliver the signal S1 which is applied to the control input of switch SW1.

Le fonctionnement du circuit 11, décrit par le tableau 2 ci-après, est équivalent au fonctionnement décrit par le tableau 1 ci-dessus. Pendant la première période E1 de charge du condensateur CREG le signal S1 est égal à 0 et le signal S3 égal à 1. L'interrupteur ballast SW2 est fermé, l'interrupteur SW3 ouvert (transistor bloqué) et l'interrupteur SW4 fermé. Le signal S1 est à 1 (tension VDD) et l'interrupteur de régulation SW1 est maintenu ouvert. Pendant la deuxième période de charge E2, le signal S2 reste à 0, le signal S3 passe à 0, l'interrupteur SW3 se ferme et l'interrupteur SW4 s'ouvre. Le signal S1 recopie le signal S2 par l'intermédiaire de l'interrupteur SW3 et l'interrupteur de régulation SW1 se ferme. VREG S2 SW2 S3 SW3 SW4 S1 SW1 (E1) VREG < VREF2 0 fermé 1 ouvert fermé 1 ouvert (E2) VREF2 < VREG < VREF1 0 fermé 0 fermé ouvert 0 fermé (E3) VREG > VREF1 1 ouvert 0 fermé ouvert 1 ouvert The operation of circuit 11, described by table 2 below, is equivalent to the operation described by table 1 above. During the first period E1 of charging the capacitor C REG, the signal S1 is equal to 0 and the signal S3 equal to 1. The ballast switch SW2 is closed, the switch SW3 open (transistor blocked) and the switch SW4 closed. Signal S1 is at 1 (voltage V DD ) and the regulation switch SW1 is kept open. During the second charging period E2, the signal S2 remains at 0, the signal S3 goes to 0, the switch SW3 closes and the switch SW4 opens. The signal S1 copies the signal S2 via the switch SW3 and the regulation switch SW1 closes. V REG S2 SW2 S3 SW3 SW4 S1 SW1 (E1) V REG <V REF2 0 closed 1 open closed 1 open (E2) V REF2 <V REG <V REF1 0 closed 0 closed open 0 closed (E3) V REG > V REF1 1 open 0 closed open 1 open

On voit dans le tableau 2 que l'interrupteur SW3 est un interrupteur inhibiteur permettant, pendant la première période de charge E1, de ne pas transmettre à l'interrupteur SW1 le signal de régulation S2, de sorte que l'interrupteur SW1 ne se ferme pas. L'interrupteur SW4 est un élément auxiliaire permettant d'éviter que la grille du transistor interrupteur SW1 soit portée à un potentiel flottant (haute impédance) quand l'interrupteur SW3 est ouvert. Bien entendu, diverses variantes sont envisageables selon le mode de fonctionnement des interrupteurs utilisés, qui peuvent être du type normalement ouvert, du type normalement fermé, ou du type n'acceptant pas un signal indéfini sur l'entrée de commande.We see in table 2 that the switch SW3 is an inhibitor switch allowing, during the first charge period E1, not to transmit to the switch SW1 the regulation signal S2, so that the switch SW1 does not close. The switch SW4 is an auxiliary element to prevent the gate of the switch transistor SW1 be brought to a floating potential (high impedance) when the switch SW3 is open. Of course, various variants are possible according to the operating mode of switches used, which may be of the type normally open, normally closed type, or type not accepting an undefined signal on the input of ordered.

Ce mode de réalisation du circuit 11 peut également faire l'objet de diverses variantes en ce qui concerne la commande de l'interrupteur inhibiteur SW3. Par exemple, le signal S3 peut être délivré par une minuterie que l'on active au démarrage du régulateur 10, ou être délivré par le microprocesseur 20 après exécution d'un programme de temporisation. Dans ce cas, l'interrupteur de régulation SW1 reste ouvert jusqu'à ce que le signal S3 soit mis à 0 par la minuterie ou le microprocesseur. En pratique, la durée de la temporisation doit être calculée en fonction de la capacité du condensateur CREG.This embodiment of the circuit 11 can also be the subject of various variants with regard to the control of the inhibitor switch SW3. For example, the signal S3 can be delivered by a timer which is activated at the start of the regulator 10, or be delivered by the microprocessor 20 after execution of a timer program. In this case, the regulation switch SW1 remains open until the signal S3 is set to 0 by the timer or the microprocessor. In practice, the duration of the time delay must be calculated according to the capacity of the capacitor C REG .

Ce mode de réalisation du circuit 11 présente toutefois l'avantage de garantir une mise en service automatique de l'interrupteur de régulation SW1 lorsque le seuil VREF2 est atteint, quelle que soit la capacité CREG et sans qu'il soit nécessaire de générer un signal de temporisation au moyen d'une minuterie ou d'un programme. Comme autre avantage, le signal S3 délivré par le comparateur CP2 peut être utilisé par le microprocesseur pour surveiller l'état du régulateur 10. Par exemple, le passage à 1 du signal S1 en cours de fonctionnement est représentatif d'une surcharge du régulateur. Enfin, dans certaines applications, le signal S3 peut être combiné de façon logique à d'autres signaux émis par le microprocesseur avant d'être appliqué à l'interrupteur inhibiteur SW3, pour que le microprocesseur puisse forcer à l'état ouvert ou fermé l'interrupteur régulateur SW1 si cela s'avère nécessaire.This embodiment of the circuit 11 however has the advantage of guaranteeing an automatic commissioning of the regulation switch SW1 when the threshold V REF2 is reached, whatever the capacity C REG and without it being necessary to generate a time delay signal by means of a timer or a program. As another advantage, the signal S3 delivered by the comparator CP2 can be used by the microprocessor to monitor the state of the regulator 10. For example, the change to 1 of the signal S1 during operation is representative of an overload of the regulator. Finally, in certain applications, the signal S3 can be logically combined with other signals emitted by the microprocessor before being applied to the inhibitor switch SW3, so that the microprocessor can force in the open or closed state l 'regulator switch SW1 if necessary.

Enfin, bien que l'on ait indiqué ci-dessus que la résistance R2 est la résistance intrinsèque de l'interrupteur ballast SW2, il va de soi que le terme "interrupteur ballast" peut désigner, dans la description et les revendications, un interrupteur de résistance nulle connecté en série avec une résistance R2, ou un interrupteur de résistance intrinsèque R2a connecté en série avec une résistance complémentaire R2b.Finally, although it has been indicated above that the resistance R2 is the intrinsic resistance of the ballast switch SW2, it goes without saying that the term "ballast switch" can designate, in the description and the claims, a switch of zero resistance connected in series with a resistor R2, or an intrinsic resistance switch R2 a connected in series with an additional resistance R2 b .

Claims (10)

Régulateur de tension (10) comprenant un condensateur (CREG) délivrant sur son anode une tension régulée (VREG), un interrupteur de régulation (SW1) pour connecter le condensateur (CREG) à une source (21) de tension (VDD), et des moyens de régulation agencés pour fermer l'interrupteur (SW1) quand la tension régulée (VREG) est inférieure à une première tension de référence (VREF1), caractérisé en ce qu'il comprend : au moins un interrupteur ballast (SW2) en parallèle avec l'interrupteur de régulation (SW1), et des moyens (11, CP1, CP2, SW3, SW4) pour ouvrir l'interrupteur de régulation (SW1) et fermer l'interrupteur ballast (SW2) au moins pendant une phase de démarrage du régulateur, jusqu'à ce que le condensateur (CREG) soit au moins partiellement chargé. Voltage regulator (10) comprising a capacitor (C REG ) delivering on its anode a regulated voltage (V REG ), a regulation switch (SW1) for connecting the capacitor (C REG ) to a voltage source (21) DD ), and regulating means arranged to close the switch (SW1) when the regulated voltage (V REG ) is less than a first reference voltage (V REF1 ), characterized in that it comprises: at least one ballast switch (SW2) in parallel with the regulation switch (SW1), and means (11, CP1, CP2, SW3, SW4) for opening the regulation switch (SW1) and closing the ballast switch (SW2) at least during a start-up phase of the regulator, until the capacitor ( C REG ) is at least partially charged. Régulateur selon la revendication 1, caractérisé en ce qu'il comprend des moyens (11, CP1, CP2, SW3, SW4) pour ouvrir l'interrupteur de régulation (SW1) et fermer l'interrupteur ballast (SW2) quand la tension régulée (VREG) est inférieure à une deuxième tension de référence (VREF2) inférieure à la première tension de référence (VREF1).Regulator according to claim 1, characterized in that it comprises means (11, CP1, CP2, SW3, SW4) for opening the regulation switch (SW1) and closing the ballast switch (SW2) when the regulated voltage ( V REG ) is less than a second reference voltage (V REF2 ) less than the first reference voltage (V REF1 ). Régulateur selon la revendication 2, dans lequel la deuxième tension de référence (VREF2) est une fraction de la première tension de référence (VREF1).The regulator of claim 2, wherein the second reference voltage (V REF2 ) is a fraction of the first reference voltage (V REF1 ). Régulateur selon l'une des revendications 1 à 3, dans lequel un signal (S2) commun de commande de l'interrupteur de régulation (SW1) et de l'interrupteur ballast (SW2) est appliqué à l'interrupteur de régulation (SW1) par l'intermédiaire d'un interrupteur inhibiteur (SW3). Regulator according to one of claims 1 to 3, in which a common signal (S2) for controlling the regulation switch (SW1) and the switch ballast (SW2) is applied to the regulation switch (SW1) via an inhibitor switch (SW3). Régulateur selon la revendication 4, dans lequel l'interrupteur inhibiteur (SW3) est piloté par un signal (S3) délivré par un comparateur (CP2) recevant en entrée la tension régulée (VREG) et une deuxième tension de référence (VREF2) inférieure à la première tension de référence (VREF1).Regulator according to claim 4, in which the inhibitor switch (SW3) is controlled by a signal (S3) delivered by a comparator (CP2) receiving as input the regulated voltage (V REG ) and a second reference voltage (V REF2 ) lower than the first reference voltage (V REF1 ). Régulateur selon l'une des revendications 1 à 5, comprenant un circuit suiveur (CP1) et un comparateur (CP2), dans lequel le circuit suiveur (CP1) reçoit en entrée la tension régulée (VREG) et la première tension de référence (VREF1) et délivre un signal de régulation (S2), le comparateur (CP2) reçoit en entrée la tension régulée (VREG) et une deuxième tension de référence (VREF2) inférieure à la première tension de référence (VREF1), le signal de régulation (S2) est appliqué sur l'entrée de commande de l'interrupteur ballast (SW2) et est appliqué sur l'entrée de commande de l'interrupteur de régulation (SW1) par l'intermédiaire d'un interrupteur inhibiteur (SW3), et la sortie du comparateur (CP2) est appliquée sur l'entrée de commande de l'interrupteur inhibiteur (SW3).Regulator according to one of claims 1 to 5, comprising a follower circuit (CP1) and a comparator (CP2), in which the follower circuit (CP1) receives as input the regulated voltage (V REG ) and the first reference voltage ( V REF1 ) and delivers a regulation signal (S2), the comparator (CP2) receives as input the regulated voltage (V REG ) and a second reference voltage (V REF2 ) lower than the first reference voltage (V REF1 ), the regulation signal (S2) is applied to the control input of the ballast switch (SW2) and is applied to the control input of the regulation switch (SW1) via an inhibitor switch (SW3), and the comparator output (CP2) is applied to the control input of the inhibitor switch (SW3). Régulateur selon l'une des revendications 1 à 6, dans lequel l'interrupteur ballast (SW2) est un transistor MOS comprenant une résistance intrinsèque (R2) non négligeable.Regulator according to one of claims 1 to 6, in which the ballast switch (SW2) is a MOS transistor comprising an intrinsic resistance (R2) not negligible. Régulateur selon l'une des revendications 1 à 7, dans lequel la source (21) de tension (VDD) est une pile électrique.Regulator according to one of claims 1 to 7, in which the voltage source (21) (V DD ) is an electric battery. Circuit intégré (20), comprenant un régulateur selon l'une des revendications 1 à 8.Integrated circuit (20), comprising a regulator according to one of claims 1 to 8. Microprocesseur (20), comprenant un régulateur selon l'une des revendications 1 à 8.Microprocessor (20), comprising a regulator according to one of claims 1 to 8.
EP00119687A 1999-09-10 2000-09-08 Voltage regulator Expired - Lifetime EP1083471B1 (en)

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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6501305B2 (en) * 2000-12-22 2002-12-31 Texas Instruments Incorporated Buffer/driver for low dropout regulators
FR2819652B1 (en) * 2001-01-17 2003-05-30 St Microelectronics Sa IMPROVED YIELD VOLTAGE REGULATOR
US6574944B2 (en) * 2001-06-19 2003-06-10 Mars Incorporated Method and system for ultrasonic sealing of food product packaging
US6605982B2 (en) * 2001-06-29 2003-08-12 Stmicroelectronics Inc. Bias circuit for a transistor of a storage cell
US6948079B2 (en) * 2001-12-26 2005-09-20 Intel Corporation Method and apparatus for providing supply voltages for a processor
TWI237168B (en) * 2003-05-20 2005-08-01 Mediatek Inc Low noise fast stable voltage regulator circuit
CN100373281C (en) * 2003-06-05 2008-03-05 联发科技股份有限公司 Low-noise rapid stabilizing stabilized circuit
TWI233543B (en) * 2003-10-01 2005-06-01 Mediatek Inc Fast-disabled voltage regulator circuit with low-noise feedback loop
CN100367142C (en) * 2003-10-21 2008-02-06 联发科技股份有限公司 Low-noise stablized voltage circuit capable of fast stopping working
CN1760782A (en) * 2004-10-13 2006-04-19 鸿富锦精密工业（深圳）有限公司 Motherboard direct current linear stabilized power supply
CN100412753C (en) * 2004-11-20 2008-08-20 鸿富锦精密工业（深圳）有限公司 Circuit for producing operating voltage of host board chip set
JP4757623B2 (en) * 2005-12-21 2011-08-24 パナソニック株式会社 Power circuit
US7705560B2 (en) * 2006-08-15 2010-04-27 N. P. Johnson Family Limited Partnership Voltage controller
JP5143483B2 (en) * 2007-07-03 2013-02-13 ルネサスエレクトロニクス株式会社 Boost circuit and integrated circuit including the boost circuit
US20090079406A1 (en) * 2007-09-26 2009-03-26 Chaodan Deng High-voltage tolerant low-dropout dual-path voltage regulator with optimized regulator resistance and supply rejection
KR100915830B1 (en) * 2008-03-12 2009-09-07 주식회사 하이닉스반도체 Semiconductor integrated circuit
US8729876B2 (en) * 2010-01-24 2014-05-20 Himax Technologies Limited Voltage regulator and related voltage regulating method thereof
US8405457B2 (en) 2010-06-15 2013-03-26 Aeroflex Colorado Springs Inc. Amplitude-stabilized odd order pre-distortion circuit
US20110309808A1 (en) 2010-06-16 2011-12-22 Aeroflex Colorado Springs Inc. Bias-starving circuit with precision monitoring loop for voltage regulators with enhanced stability
RU2467376C1 (en) * 2011-06-08 2012-11-20 Общество с ограниченной ответственностью "Констайлс" (ООО "Констайлс") Voltage regulator
JP2013186721A (en) * 2012-03-08 2013-09-19 Toyota Motor Corp Power supply circuit and electronic control device using the same
US10317921B1 (en) * 2018-04-13 2019-06-11 Nxp Usa, Inc. Effective clamping in power supplies

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0309922A2 (en) * 1987-09-30 1989-04-05 Siemens Aktiengesellschaft Circuit for briefly boosting a regulated power voltage when switching on or in case of a drop in voltage
US5861737A (en) * 1996-07-31 1999-01-19 Data General Corporation Soft-start switch with voltage regulation and current limiting

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0031583B1 (en) * 1979-12-26 1988-08-17 Kabushiki Kaisha Toshiba A driver circuit for charge coupled device
US5001484A (en) * 1990-05-08 1991-03-19 Triquint Semiconductor, Inc. DAC current source bias equalization topology

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0309922A2 (en) * 1987-09-30 1989-04-05 Siemens Aktiengesellschaft Circuit for briefly boosting a regulated power voltage when switching on or in case of a drop in voltage
US5861737A (en) * 1996-07-31 1999-01-19 Data General Corporation Soft-start switch with voltage regulation and current limiting

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KMETZ G L: "SOFT-START REGULATOR STARTS AT OV", EDN ELECTRICAL DESIGN NEWS,US,CAHNERS PUBLISHING CO. NEWTON, MASSACHUSETTS, vol. 41, no. 12, 6 June 1996 (1996-06-06), pages 104,106, XP000622006, ISSN: 0012-7515 *

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FR2798480A1 (en) 2001-03-16
FR2798480B1 (en) 2001-10-26

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