EP1083471A1 - Spannungsregler - Google Patents

Spannungsregler Download PDF

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Publication number
EP1083471A1
EP1083471A1 EP00119687A EP00119687A EP1083471A1 EP 1083471 A1 EP1083471 A1 EP 1083471A1 EP 00119687 A EP00119687 A EP 00119687A EP 00119687 A EP00119687 A EP 00119687A EP 1083471 A1 EP1083471 A1 EP 1083471A1
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EP
European Patent Office
Prior art keywords
switch
voltage
reg
reference voltage
regulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP00119687A
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English (en)
French (fr)
Other versions
EP1083471B1 (de
Inventor
Bruno Gailhard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
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STMicroelectronics SA
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Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of EP1083471A1 publication Critical patent/EP1083471A1/de
Application granted granted Critical
Publication of EP1083471B1 publication Critical patent/EP1083471B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor

Definitions

  • the present invention relates to a regulator of voltage including a capacitor delivering on its anode a regulated voltage, a regulation switch to connect the capacitor to a voltage source and regulating means arranged to close the switch when the regulated voltage is less than a first reference voltage.
  • Voltage regulators find various electronics applications, for example example to deliver a regulated voltage used to electrically supply the ports of a microprocessor.
  • FIG. 1 represents a conventional voltage regulator 1, incorporated in a microprocessor 2.
  • the microprocessor 2 is powered by an electric battery 3 of internal resistance r i , delivering a voltage V DD .
  • the regulator 1 comprises an external capacitor C REG delivering on its anode a regulated voltage V REG .
  • the anode of the capacitor C REG is connected to the anode of the battery 3 by means of a regulation switch SW 1 having a series resistance R 1 zero or of low value.
  • the switch SW1 is controlled by the output of a follower circuit CP receiving on its positive input the regulated voltage V REG and on its negative input a reference voltage V REF .
  • the voltage V REF is conventionally a so-called band-gap voltage having good stability as a function of the temperature, generated by means of PN junction diodes and current mirrors.
  • the follower circuit CP is controlled by a PDW (Power-Down) signal and the anode of the capacitor C REG is connected to ground by a switch SW OFF controlled by the PDW signal.
  • PDW Power-Down
  • the follower circuit CP is blocked and the switch SW OFF is closed. Regulator 1 is stopped and capacitor C REG is discharged.
  • the disadvantage of such a regulator is that it has a high current consumption at start-up.
  • the capacitor C REG is discharged and the voltage V REG is zero.
  • the output of the follower circuit CP goes to 0 and the switch SW 1 closes.
  • the application of the voltage V DD on the capacitor C REG causes a strong current draw and a significant drop in the supply voltage V DD of the microprocessor 2, due to the internal resistance r i of the battery 3. If at at the same time other elements of the microprocessor 2 consume a non-negligible current, it may happen that the voltage V DD becomes lower than the minimum operating voltage of the microprocessor 2, so that the microprocessor 2 is blocked.
  • the present invention aims to overcome this disadvantage.
  • the present invention aims to limit the starting current of a regulator without increase the series resistance of the switch regulation.
  • the present invention provides a regulator of the type described above, comprising at least a ballast switch in parallel with the switch regulating device, and means for opening the switch at least the ballast switch during a regulator start-up phase, until the capacitor is at least partially charged.
  • the regulator includes means for opening the switch regulation and close the ballast switch when the regulated voltage is less than a second voltage of reference lower than the first reference voltage.
  • the second voltage reference is a fraction of the first voltage of reference.
  • a common signal of control of the regulation switch and the ballast switch is applied to the regulation via a switch inhibitor.
  • the switch inhibitor is controlled by a signal delivered by a comparator receiving as input the regulated voltage and a second reference voltage lower than the first reference voltage.
  • the regulator includes a follower circuit receiving the input voltage regulated and the first reference voltage, the circuit follower delivering a regulation signal, and a comparator receiving as input the regulated voltage and a second reference voltage lower than the first reference voltage.
  • the regulation signal is applied to the switch control input ballast and is applied to the control input of the regulation switch via a inhibitor switch.
  • the comparator output is applied to the switch control input inhibitor.
  • the switch ballast is a MOS transistor comprising a resistor significant intrinsic.
  • the voltage source is an electric battery.
  • the present invention also relates to a circuit integrated, in particular a microprocessor, comprising a regulator according to the invention.
  • FIG. 2 represents a voltage regulator according to the invention.
  • the regulator 10 conventionally comprises a capacitor C REG whose anode is connected to a voltage source V DD by a regulation switch SW1, here a PMOS transistor, comprising a zero or low value series resistance R1.
  • the anode of the capacitor C REG which delivers a regulated voltage V REG , is connected to ground by a switch SW OFF controlled by a reset signal PDW (Power-Down).
  • a ballast switch SW2 is connected in parallel with the switch SW1.
  • the switch SW2 has a non-negligible series resistance R2, for example of the order of a few hundred ohms.
  • the switch SW2 is here a PMOS transistor and the resistance R2 is the intrinsic resistance of the transistor, that is to say its series resistance (R ON ) with the passing being.
  • the value of the resistance R2 is thus determined by the choice of the ratio W / L between the width W and the length L of the gate of the transistor.
  • the switches SW1, SW2 are controlled by a circuit 11, shown here in the form of a block, controlled by the signal PDW.
  • the circuit 11 receives as input the voltage V REG , a first reference voltage V REF1 and a second reference voltage V REF2 .
  • the voltage V REF2 is less than V REF1 and is for example equal to 0.75 V REF1 .
  • the circuit 11 delivers a signal S1 for controlling the switch SW1 and a signal S2 for controlling the switch SW2 (the signals S1, S2 being applied here to the gates of the PMOS transistors).
  • the circuit 11 When the PDW signal is at 1, the circuit 11 is blocked and the switch SW OFF is closed. The capacitor C REG is discharged and the voltage V REG is zero. When the PDW signal is set to 0, the circuit 11 starts and the capacitor C REG charges.
  • the operation of regulator 10 and circuit 11 is described in table 1 below.
  • the switches SW1, SW2 being here PMOS transistors, the active value of the signals S1, S2 corresponding to the closing of the switches SW1, SW2 (on state) is the value 0 (gate of the transistors to ground). When the signals S1, S2 are at 1 (voltage V DD ), the switches are open (transistors in the off state).
  • V REG S1 SW1 S2 SW2 (E1) V REG ⁇ V REF2 1 open 0 closed (E2) V REF2 ⁇ V REG ⁇ V REF1 0 closed 0 or 1 closed or open (E3) V REG > V REF1 1 open 1 open
  • the capacitor C REG is charged in two periods E1, E2.
  • the ballast switch SW2 is closed and the regulation switch SW1 is open.
  • the capacitor C REG is charged via the ballast switch SW2 and the starting current is limited by the resistor R2. The risk of seeing the supply voltage V DD decrease significantly is thus eliminated, in particular when the voltage V DD is delivered by an electric battery or a voltage generator having a significant internal resistance.
  • the period E2 occurs when the voltage V REG exceeds the threshold V REF2 .
  • the switch SW1 closes and the charge cycle of the capacitor C REG ends quickly since the resistance R1 is zero or of low value.
  • the ballast switch SW2 can, indifferently, be kept open or closed.
  • the regulator 10 When the capacitor C REG is charged, the regulator 10 operates in a conventional manner, the regulation switch SW1 being closed (period E2) or open (period E3) depending on whether the voltage V REG is less than or greater than V REF1 .
  • the voltage V REG is thus controlled in the vicinity of V REF1 with alternation of the periods E2 and E3.
  • the ballast switch SW2 During periods of E3 overshoot, the ballast switch SW2 is always open.
  • FIG. 3 An advantageous embodiment of the circuit 11 is shown in FIG. 3.
  • the regulator 10 is shown incorporated in an integrated circuit 20, for example a microprocessor, and the voltage V DD is delivered by an electric battery 21 of internal resistance r i .
  • the circuit 11 includes an operational amplifier C1 arranged in a follower circuit and a comparator CP2.
  • the follower circuit CP1 and the comparator CP2 are controlled by the signal PDW.
  • the follower circuit CP1 receives on its negative input the voltage V REF1 and on its positive input the regulated voltage V REG .
  • the output of the follower circuit CP1 delivers the signal S2 which is applied to the control input of the switch SW2.
  • the comparator CP2 receives on its positive input the voltage V REF2 and on its negative input the voltage V REG .
  • the voltage V REF2 is obtained here by dividing the voltage V REF1 by means of a divider bridge comprising two resistors r a , r b .
  • the output of the comparator CP2 delivers a signal S3 which is applied to the control input of a switch SW3, here a PMOS transistor, as well as to the input of an inverting gate INV1.
  • the output of gate INV1 is connected to the control input of a switch SW4, here a PMOS transistor.
  • the input of the switch SW4 (source of the transistor) receives the voltage V DD and the input of the switch SW3 receives the signal S2.
  • the outputs of switches SW3 and SW4 are connected together and deliver the signal S1 which is applied to the control input of switch SW1.
  • circuit 11 The operation of circuit 11, described by table 2 below, is equivalent to the operation described by table 1 above.
  • the signal S1 is equal to 0 and the signal S3 equal to 1.
  • the ballast switch SW2 is closed, the switch SW3 open (transistor blocked) and the switch SW4 closed.
  • Signal S1 is at 1 (voltage V DD ) and the regulation switch SW1 is kept open.
  • the signal S2 remains at 0, the signal S3 goes to 0, the switch SW3 closes and the switch SW4 opens.
  • the signal S1 copies the signal S2 via the switch SW3 and the regulation switch SW1 closes.
  • V REG S2 SW2 S3 SW3 SW4 S1 SW1 (E1) V REG ⁇ V REF2 0 closed 1 open closed 1 open (E2) V REF2 ⁇ V REG ⁇ V REF1 0 closed 0 closed open 0 closed (E3) V REG > V REF1 1 open 0 closed open 1 open
  • the switch SW3 is an inhibitor switch allowing, during the first charge period E1, not to transmit to the switch SW1 the regulation signal S2, so that the switch SW1 does not close.
  • the switch SW4 is an auxiliary element to prevent the gate of the switch transistor SW1 be brought to a floating potential (high impedance) when the switch SW3 is open.
  • the operating mode of switches used which may be of the type normally open, normally closed type, or type not accepting an undefined signal on the input of ordered.
  • This embodiment of the circuit 11 can also be the subject of various variants with regard to the control of the inhibitor switch SW3.
  • the signal S3 can be delivered by a timer which is activated at the start of the regulator 10, or be delivered by the microprocessor 20 after execution of a timer program.
  • the regulation switch SW1 remains open until the signal S3 is set to 0 by the timer or the microprocessor.
  • the duration of the time delay must be calculated according to the capacity of the capacitor C REG .
  • This embodiment of the circuit 11 however has the advantage of guaranteeing an automatic commissioning of the regulation switch SW1 when the threshold V REF2 is reached, whatever the capacity C REG and without it being necessary to generate a time delay signal by means of a timer or a program.
  • the signal S3 delivered by the comparator CP2 can be used by the microprocessor to monitor the state of the regulator 10. For example, the change to 1 of the signal S1 during operation is representative of an overload of the regulator.
  • the signal S3 can be logically combined with other signals emitted by the microprocessor before being applied to the inhibitor switch SW3, so that the microprocessor can force in the open or closed state l 'regulator switch SW1 if necessary.
  • the resistance R2 is the intrinsic resistance of the ballast switch SW2
  • ballast switch can designate, in the description and the claims, a switch of zero resistance connected in series with a resistor R2, or an intrinsic resistance switch R2 a connected in series with an additional resistance R2 b .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
EP00119687A 1999-09-10 2000-09-08 Spannungsregler Expired - Lifetime EP1083471B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9911492 1999-09-10
FR9911492A FR2798480B1 (fr) 1999-09-10 1999-09-10 Regulateur de tension

Publications (2)

Publication Number Publication Date
EP1083471A1 true EP1083471A1 (de) 2001-03-14
EP1083471B1 EP1083471B1 (de) 2004-11-17

Family

ID=9549834

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00119687A Expired - Lifetime EP1083471B1 (de) 1999-09-10 2000-09-08 Spannungsregler

Country Status (4)

Country Link
US (1) US6362609B1 (de)
EP (1) EP1083471B1 (de)
DE (1) DE60015882T2 (de)
FR (1) FR2798480B1 (de)

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Publication number Priority date Publication date Assignee Title
US6501305B2 (en) * 2000-12-22 2002-12-31 Texas Instruments Incorporated Buffer/driver for low dropout regulators
FR2819652B1 (fr) * 2001-01-17 2003-05-30 St Microelectronics Sa Regulateur de tension a rendement ameliore
US6574944B2 (en) * 2001-06-19 2003-06-10 Mars Incorporated Method and system for ultrasonic sealing of food product packaging
US6605982B2 (en) * 2001-06-29 2003-08-12 Stmicroelectronics Inc. Bias circuit for a transistor of a storage cell
US6948079B2 (en) * 2001-12-26 2005-09-20 Intel Corporation Method and apparatus for providing supply voltages for a processor
TWI237168B (en) * 2003-05-20 2005-08-01 Mediatek Inc Low noise fast stable voltage regulator circuit
CN100373281C (zh) * 2003-06-05 2008-03-05 联发科技股份有限公司 低噪声快速稳定的稳压电路
TWI233543B (en) * 2003-10-01 2005-06-01 Mediatek Inc Fast-disabled voltage regulator circuit with low-noise feedback loop
CN100367142C (zh) * 2003-10-21 2008-02-06 联发科技股份有限公司 可快速终止工作的低噪声稳压电路
CN1760782A (zh) * 2004-10-13 2006-04-19 鸿富锦精密工业（深圳）有限公司 主机板直流线性稳压电源
CN100412753C (zh) * 2004-11-20 2008-08-20 鸿富锦精密工业（深圳）有限公司 主机板芯片组工作电压产生电路
JP4757623B2 (ja) * 2005-12-21 2011-08-24 パナソニック株式会社 電源回路
US7705560B2 (en) * 2006-08-15 2010-04-27 N. P. Johnson Family Limited Partnership Voltage controller
JP5143483B2 (ja) * 2007-07-03 2013-02-13 ルネサスエレクトロニクス株式会社 昇圧回路、およびその昇圧回路を備える集積回路
US20090079406A1 (en) * 2007-09-26 2009-03-26 Chaodan Deng High-voltage tolerant low-dropout dual-path voltage regulator with optimized regulator resistance and supply rejection
KR100915830B1 (ko) * 2008-03-12 2009-09-07 주식회사 하이닉스반도체 반도체 집적 회로
US8729876B2 (en) * 2010-01-24 2014-05-20 Himax Technologies Limited Voltage regulator and related voltage regulating method thereof
US8405457B2 (en) 2010-06-15 2013-03-26 Aeroflex Colorado Springs Inc. Amplitude-stabilized odd order pre-distortion circuit
US20110309808A1 (en) 2010-06-16 2011-12-22 Aeroflex Colorado Springs Inc. Bias-starving circuit with precision monitoring loop for voltage regulators with enhanced stability
RU2467376C1 (ru) * 2011-06-08 2012-11-20 Общество с ограниченной ответственностью "Констайлс" (ООО "Констайлс") Регулятор напряжения
JP2013186721A (ja) * 2012-03-08 2013-09-19 Toyota Motor Corp 電源回路とそれを用いた電子制御装置
US10317921B1 (en) * 2018-04-13 2019-06-11 Nxp Usa, Inc. Effective clamping in power supplies

Citations (2)

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Publication number Priority date Publication date Assignee Title
EP0309922A2 (de) * 1987-09-30 1989-04-05 Siemens Aktiengesellschaft Schaltung zur kurzzeitigen Erhöhung einer geregelten Betriebsspannung beim Einschalten und bei Spannungseinbrüchen
US5861737A (en) * 1996-07-31 1999-01-19 Data General Corporation Soft-start switch with voltage regulation and current limiting

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DE3072118D1 (en) * 1979-12-26 1988-09-22 Toshiba Kk A driver circuit for charge coupled device
US5001484A (en) * 1990-05-08 1991-03-19 Triquint Semiconductor, Inc. DAC current source bias equalization topology

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0309922A2 (de) * 1987-09-30 1989-04-05 Siemens Aktiengesellschaft Schaltung zur kurzzeitigen Erhöhung einer geregelten Betriebsspannung beim Einschalten und bei Spannungseinbrüchen
US5861737A (en) * 1996-07-31 1999-01-19 Data General Corporation Soft-start switch with voltage regulation and current limiting

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KMETZ G L: "SOFT-START REGULATOR STARTS AT OV", EDN ELECTRICAL DESIGN NEWS,US,CAHNERS PUBLISHING CO. NEWTON, MASSACHUSETTS, vol. 41, no. 12, 6 June 1996 (1996-06-06), pages 104,106, XP000622006, ISSN: 0012-7515 *

Also Published As

Publication number Publication date
FR2798480A1 (fr) 2001-03-16
FR2798480B1 (fr) 2001-10-26
US6362609B1 (en) 2002-03-26
EP1083471B1 (de) 2004-11-17
DE60015882T2 (de) 2005-12-08
DE60015882D1 (de) 2004-12-23

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