EP1083471B1 - Spannungsregler - Google Patents

Spannungsregler Download PDF

Info

Publication number
EP1083471B1
EP1083471B1 EP00119687A EP00119687A EP1083471B1 EP 1083471 B1 EP1083471 B1 EP 1083471B1 EP 00119687 A EP00119687 A EP 00119687A EP 00119687 A EP00119687 A EP 00119687A EP 1083471 B1 EP1083471 B1 EP 1083471B1
Authority
EP
European Patent Office
Prior art keywords
switch
voltage
reg
reference voltage
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP00119687A
Other languages
English (en)
French (fr)
Other versions
EP1083471A1 (de
Inventor
Bruno Gailhard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of EP1083471A1 publication Critical patent/EP1083471A1/de
Application granted granted Critical
Publication of EP1083471B1 publication Critical patent/EP1083471B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor

Definitions

  • the present invention relates to a regulator of voltage comprising a capacitor delivering on its anode a regulated voltage, a regulation switch to connect the capacitor to a voltage source and regulating means arranged to close the switch when the regulated voltage is lower than a first reference voltage.
  • Voltage regulators find various applications in the field of electronics, by example to deliver a regulated voltage used to electrically powering the ports of a microprocessor.
  • FIG. 1 represents a conventional voltage regulator 1, incorporated in a microprocessor 2.
  • the microprocessor 2 is powered by an electric battery 3 of internal resistance r i , delivering a voltage V DD .
  • the regulator 1 comprises an external capacitor C REG delivering on its anode a regulated voltage V REG .
  • the anode of the capacitor C REG is connected to the anode of the cell 3 via a regulating switch SW 1 having a null or low value series resistor R 1 .
  • the switch SW1 is controlled by the output of a follower circuit CP receiving on its positive input the regulated voltage V REG and on its negative input a reference voltage V REF .
  • the voltage V REF is conventionally a so-called band gap voltage having good stability as a function of temperature, generated by means of PN junction diodes and current mirrors.
  • the follower circuit CP is controlled by a PDW signal (Power-Down) and the anode of the capacitor C REG is connected to ground by a switch SW OFF controlled by the signal PDW.
  • PDW Power-Down
  • the switch SW OFF is closed. Regulator 1 is stopped and capacitor C REG is discharged.
  • the disadvantage of such a regulator is to have a high power consumption at startup.
  • the capacitor C REG is discharged and the voltage V REG is zero.
  • the output of the follower circuit CP goes to 0 and the switch SW 1 closes.
  • the application of the voltage V DD on the capacitor C REG causes a strong current draw and a significant drop in the supply voltage V DD of the microprocessor 2, because of the internal resistance r i of the battery 3. If at At the same time other elements of the microprocessor 2 consume a significant current, it may happen that the voltage V DD becomes lower than the minimum operating voltage of the microprocessor 2, so that the microprocessor 2 is blocked.
  • the present invention aims to overcome this disadvantage.
  • US Patent 5,861,737 describes a regulator in which the current supplied to a load is limited by adequate control of the grid voltage applied to a MOSFET regulating transistor arranged between the source voltage and charge. This MOSFET transistor presents thus a series resistance of variable value allowing to limit the starting current.
  • the present invention aims to limit the starting current of a regulator without increase the series resistance of the switch .regulation.
  • the present invention also relates to a circuit integrated circuit, in particular a microprocessor, comprising a regulator according to the invention.
  • FIG. 2 represents a voltage regulator according to the invention.
  • the regulator 10 conventionally comprises a capacitor C REG whose anode is connected to a voltage source V DD by a regulating switch SW1, here a PMOS transistor, having a null or low value series resistor R1.
  • the anode of the capacitor C REG which delivers a regulated voltage V REG , is connected to ground by a switch SW OFF controlled by a reset signal PDW (Power-Down).
  • a ballast switch SW2 is connected in parallel with the switch SW1.
  • Switch SW2 has a significant resistance R2 series, for example of the order of a few hundred ohms.
  • the switch SW2 is here a PMOS transistor and the resistor R2 is the intrinsic resistance of the transistor, that is to say its series resistance (R ON ) to the passing being.
  • the value of the resistance R2 is thus determined by the choice of the ratio W / L between the width W and the length L of the gate of the transistor.
  • the switches SW1, SW2 are controlled by a circuit 11, represented here in the form of a block, controlled by the signal PDW.
  • the circuit 11 receives as input the voltage V REG , a first reference voltage V REF1 and a second reference voltage V REF2 .
  • the voltage V REF2 is less than V REF1 and is for example equal to 0.75 V REF1 .
  • the circuit 11 delivers a signal S1 for controlling the switch SW1 and a signal S2 for controlling the switch SW2 (the signals S1, S2 being here applied to the gates of the PMOS transistors).
  • the circuit 11 When the signal PDW is at 1, the circuit 11 is blocked and the switch SW OFF is closed. The capacitor C REG is discharged and the voltage V REG is zero. When the signal PDW is set to 0, the circuit 11 starts and the capacitor C REG is charged.
  • the operation of the regulator 10 and the circuit 11 is described in Table 1 below.
  • the switches SW1, SW2 being here PMOS transistors, the active value of the signals S1, S2 corresponding to the closing of the switches SW1, SW2 (conducting state) is the value 0 (gate of the transistors to ground). When the signals S1, S2 are at 1 (voltage V DD ), the switches are open (transistors in the off state).
  • V REG S1 SW1 S2 SW2 (E1) V REG ⁇ V REF2 1 open 0 closed (E2) REF2 V ⁇ V REG ⁇ V REF1 0 closed 0 or 1 closed or open (E3) V REG > V REF1 1 open 1 open
  • the capacitor C REG is charged in two periods E1, E2.
  • the ballast switch SW2 is closed and the regulation switch SW1 is open.
  • the charge of the capacitor C REG is carried out via the ballast switch SW2 and the starting current is limited by the resistor R2. The risk of seeing the supply voltage V DD greatly decrease is thus eliminated, especially when the voltage V DD is delivered by an electric battery or a voltage generator having a significant internal resistance.
  • the period E2 occurs when the voltage V REG exceeds the threshold V REF2 .
  • the switch SW1 closes and the charging cycle of the capacitor C REG terminates rapidly since the resistor R1 is zero or of low value.
  • the ballast switch SW2 can indifferently be kept open or closed.
  • the regulator 10 When the capacitor C REG is charged, the regulator 10 operates in a conventional manner, the control switch SW1 being closed (period E2) or open (period E3) depending on whether the voltage V REG is lower or higher than V REF1 .
  • the voltage V REG is thus enslaved in the vicinity of V REF1 with alternating periods E2 and E3.
  • the SW2 ballast switch is always open.
  • FIG. 3 An advantageous embodiment of the circuit 11 is shown in FIG. 3.
  • the regulator 10 is shown incorporated in an integrated circuit 20, for example a microprocessor, and the voltage V DD is delivered by an electric battery 21 of internal resistance r i .
  • the circuit 11 comprises an operational amplifier CP1 arranged in follower circuit and a comparator CP2.
  • the follower circuit CP1 and the comparator CP2 are controlled by the signal PDW.
  • the follower circuit CP1 receives on its negative input the voltage V REF1 and on its positive input the regulated voltage V REG .
  • the output of the follower circuit CP1 delivers the signal S2 which is applied to the control input of the switch SW2.
  • the comparator CP2 receives on its positive input the voltage V REF2 and on its negative input the voltage V REG .
  • the voltage V REF2 is obtained here by dividing the voltage V REF1 by means of a divider bridge comprising two resistors r a , r b .
  • the output of the comparator CP2 delivers a signal S3 which is applied to the control input of a switch SW3, here a PMOS transistor, and to the input of an inverting gate INV1.
  • the output of the gate INV1 is connected to the control input of a switch SW4, here a PMOS transistor.
  • the input of the switch SW4 (source of the transistor) receives the voltage V DD and the input of the switch SW3 receives the signal S2.
  • the outputs of the switches SW3 and SW4 drains are connected together and deliver the signal S1 which is applied to the control input of the switch SW1.
  • circuit 11 The operation of circuit 11, described in Table 2 below, is equivalent to the operation described in Table 1 above.
  • the signal S2 is equal to 0 and the signal S3 equal to 1.
  • the ballast switch SW2 is closed, the switch SW3 is open (transistor blocked) and the switch SW4 is closed.
  • the signal S1 is at 1 (voltage V DD ) and the regulation switch SW1 is kept open.
  • the signal S2 remains at 0, the signal S3 goes to 0, the switch SW3 closes and the switch SW4 opens.
  • the signal S1 copies the signal S2 via the switch SW3 and the control switch SW1 closes.
  • V REG S2 SW2 S3 SW3 SW4 S1 SW1 (E1) V REG ⁇ V REF2 0 closed 1 open closed 1 open (E2) V REF2 ⁇ V REG ⁇ V REF1 0 closed 0 closed open 0 closed (E3) V REG > V REF1 1 open 0 closed open 1 open
  • the switch SW3 is an inhibiting switch allowing, during the first charging period E1, not to transmit to the switch SW1 the regulation signal S2, so that switch SW1 does not close.
  • the switch SW4 is an auxiliary element to prevent the switch transistor gate SW1 is brought to a floating potential (high impedance) when the switch SW3 is open.
  • various variants are possible depending on the mode of operation of the used switches, which may be of the type normally open, normally closed type, or type not accepting an undefined signal on the input of ordered.
  • This embodiment of the circuit 11 can also be the subject of various variants with respect to the control of the inhibit switch SW3.
  • the signal S3 can be delivered by a timer that is activated at the start of the regulator 10, or be delivered by the microprocessor 20 after execution of a timing program.
  • the control switch SW1 remains open until the signal S3 is set to 0 by the timer or the microprocessor.
  • the duration of the delay must be calculated according to the capacity of the capacitor C REG .
  • this embodiment of the circuit 11 has the advantage of guaranteeing an automatic commissioning of the regulation switch SW1 when the threshold V REF2 is reached, regardless of the capacity C REG and without it being necessary to generate a timer signal by means of a timer or program.
  • the signal S3 delivered by the comparator CP2 can be used by the microprocessor to monitor the state of the regulator 10. For example, the transition to 1 of the signal S1 during operation is representative of an overload of the regulator.
  • the signal S3 can be logically combined with other signals emitted by the microprocessor before being applied to the inhibit switch SW3, so that the microprocessor can force the open or closed state SW1 regulator switch if necessary.
  • the resistor R2 is the intrinsic resistance of the ballast switch SW2
  • ballast switch can designate, in the description and the claims, a switch zero resistance connected in series with a resistor R2, or intrinsic resistance switch R2 connected in series with an additional resistor R2 b.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Claims (10)

  1. Spannungsregler (10), einen Kondensator (CREG) umfassend, der an seiner Anode eine geregelte Spannung (VREG) liefert, einen Regelschalter (SW1), um den Kondensator (CREG) an eine Quelle (21) von Spannung (VDD) anzuschließen, und Regelungsmittel, die ausgestaltet sind, um den Schalter (SW1) zu schließen, wenn die geregelte Spannung (VREG) niedriger ist als eine erste Referenzspannung ((VREF1), dadurch gekennzeichnet, dass er umfasst:
    mindestens einen Ballastschalter (SW2) parallel zu dem Regelschalter (SW1), wobei der Ballastschalter (SW2) einen Serienwiderstand (R2, R2a, R2b) aufweist, der höher ist als ein Serienwiderstand (R1) des Regelschalters (SW1), und
    Mittel (11, CP1, CP2, SW3, SW4), um den Regelschalter (SW1) zu öffnen und den Ballastschalter (SW2) zu schließen, mindestens während einer Anlaufphase des Reglers, bis der Kondensator (CREG) mindestens teilweise aufgeladen ist.
  2. Regler nach Anspruch 1, dadurch gekennzeichnet, dass er Mittel (11, CP1, CP2, SW3, SW4) umfasst, um den Regelschalter (SW1) zu öffnen und den Ballastschalter (SW2) zu schließen, wenn die geregelte Spannung (VREG) niedriger ist als eine zweite Referenzspannung (VREF2), die niedriger ist als die erste Referenzspannung (VREF1).
  3. Regler nach Anspruch 2, wobei die zweite Referenzspannung (VREF2) einen Bruchteil der ersten Referenzspannung (VREF1) ausmacht.
  4. Regler nach einem der Ansprüche 1 bis 3, wobei ein gemeinsames Signal (S2) zur Steuerung des Regelschalters (SW1) und des Ballastschalters (SW2) auf den Regelschalter (SW1) mittels eines Verzögerungsschalters (SW3) angelegt wird.
  5. Regler nach Anspruch 4, wobei der Verzögerungsschalter (SW3) durch ein Signal (S3) gesteuert wird, das durch eine Vergleichsschaltung (CP2) geliefert wird, welche die geregelte Spannung (VREG) am Eingang empfängt und eine zweite Referenzspannung (VREF2), die niedriger ist als die erste Referenzspannung (VREF1).
  6. Regler nach einem der Ansprüche 1 bis 5, eine Nachlaufschaltung (CP1) und eine Vergleichsschaltung (CP2) umfassend, bei welchem die Nachlaufschaltung (CP1) die geregelte Spannung (VREG) und die erste Referenzspannung (VREF1) am Eingang empfängt, und ein Regelsignal (S2) liefert, wobei die Vergleichsschaltung (CP2) die geregelte Spannung (VREG) und eine zweite Referenzspannung (VREF2) am Eingang empfängt, die niedriger ist als die erste Referenzspannung (VREF1), das Regelsignal (S2) an den Eingang der Steuerung des Ballastschalters (SW2) angelegt wird und mittels eines Verzögerungsschalters (SW3) an den Eingang der Steuerung des Regelschalters (SW1) angelegt wird, und der Ausgang der Vergleichsschaltung (CP2) an den Eingang der Steuerung des Verzögerungsschalters (SW3) angelegt wird.
  7. Regler nach einem der Ansprüche 1 bis 6, bei welchem der Ballastschalter (SW2) aus einem MOS-Transistor besteht, der einen eigenen nicht zu vernachlässigenden Widerstand (R2, R2a) umfasst, der den ganzen Serienwiderstand des Ballastschalters oder einen Teil davon ausbildet.
  8. Regler nach einem der Ansprüche 1 bis 7, bei welchem die Quelle (21) der Spannung (VDD) aus einer elektrischen Batterie besteht.
  9. Integrierte Schaltung (20), einen Regler nach einem der Ansprüche 1 bis 8 umfassend.
  10. Mikroprozessor (20), einen Regler nach einem der Ansprüche 1 bis 8 umfassend.
EP00119687A 1999-09-10 2000-09-08 Spannungsregler Expired - Lifetime EP1083471B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9911492 1999-09-10
FR9911492A FR2798480B1 (fr) 1999-09-10 1999-09-10 Regulateur de tension

Publications (2)

Publication Number Publication Date
EP1083471A1 EP1083471A1 (de) 2001-03-14
EP1083471B1 true EP1083471B1 (de) 2004-11-17

Family

ID=9549834

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00119687A Expired - Lifetime EP1083471B1 (de) 1999-09-10 2000-09-08 Spannungsregler

Country Status (4)

Country Link
US (1) US6362609B1 (de)
EP (1) EP1083471B1 (de)
DE (1) DE60015882T2 (de)
FR (1) FR2798480B1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6501305B2 (en) * 2000-12-22 2002-12-31 Texas Instruments Incorporated Buffer/driver for low dropout regulators
FR2819652B1 (fr) * 2001-01-17 2003-05-30 St Microelectronics Sa Regulateur de tension a rendement ameliore
US6574944B2 (en) * 2001-06-19 2003-06-10 Mars Incorporated Method and system for ultrasonic sealing of food product packaging
US6605982B2 (en) * 2001-06-29 2003-08-12 Stmicroelectronics Inc. Bias circuit for a transistor of a storage cell
US6948079B2 (en) * 2001-12-26 2005-09-20 Intel Corporation Method and apparatus for providing supply voltages for a processor
TWI237168B (en) * 2003-05-20 2005-08-01 Mediatek Inc Low noise fast stable voltage regulator circuit
CN100373281C (zh) * 2003-06-05 2008-03-05 联发科技股份有限公司 低噪声快速稳定的稳压电路
TWI233543B (en) * 2003-10-01 2005-06-01 Mediatek Inc Fast-disabled voltage regulator circuit with low-noise feedback loop
CN100367142C (zh) * 2003-10-21 2008-02-06 联发科技股份有限公司 可快速终止工作的低噪声稳压电路
CN1760782A (zh) * 2004-10-13 2006-04-19 鸿富锦精密工业（深圳）有限公司 主机板直流线性稳压电源
CN100412753C (zh) * 2004-11-20 2008-08-20 鸿富锦精密工业（深圳）有限公司 主机板芯片组工作电压产生电路
JP4757623B2 (ja) * 2005-12-21 2011-08-24 パナソニック株式会社 電源回路
US7705560B2 (en) * 2006-08-15 2010-04-27 N. P. Johnson Family Limited Partnership Voltage controller
JP5143483B2 (ja) * 2007-07-03 2013-02-13 ルネサスエレクトロニクス株式会社 昇圧回路、およびその昇圧回路を備える集積回路
US20090079406A1 (en) * 2007-09-26 2009-03-26 Chaodan Deng High-voltage tolerant low-dropout dual-path voltage regulator with optimized regulator resistance and supply rejection
KR100915830B1 (ko) * 2008-03-12 2009-09-07 주식회사 하이닉스반도체 반도체 집적 회로
US8729876B2 (en) * 2010-01-24 2014-05-20 Himax Technologies Limited Voltage regulator and related voltage regulating method thereof
US8405457B2 (en) 2010-06-15 2013-03-26 Aeroflex Colorado Springs Inc. Amplitude-stabilized odd order pre-distortion circuit
US20110309808A1 (en) 2010-06-16 2011-12-22 Aeroflex Colorado Springs Inc. Bias-starving circuit with precision monitoring loop for voltage regulators with enhanced stability
RU2467376C1 (ru) * 2011-06-08 2012-11-20 Общество с ограниченной ответственностью "Констайлс" (ООО "Констайлс") Регулятор напряжения
JP2013186721A (ja) * 2012-03-08 2013-09-19 Toyota Motor Corp 電源回路とそれを用いた電子制御装置
US10317921B1 (en) * 2018-04-13 2019-06-11 Nxp Usa, Inc. Effective clamping in power supplies

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3072118D1 (en) * 1979-12-26 1988-09-22 Toshiba Kk A driver circuit for charge coupled device
DE3876923D1 (de) * 1987-09-30 1993-02-04 Siemens Ag Schaltung zur kurzzeitigen erhoehung einer geregelten betriebsspannung beim einschalten und bei spannungseinbruechen.
US5001484A (en) * 1990-05-08 1991-03-19 Triquint Semiconductor, Inc. DAC current source bias equalization topology
US5698973A (en) * 1996-07-31 1997-12-16 Data General Corporation Soft-start switch with voltage regulation and current limiting

Also Published As

Publication number Publication date
EP1083471A1 (de) 2001-03-14
FR2798480B1 (fr) 2001-10-26
DE60015882D1 (de) 2004-12-23
US6362609B1 (en) 2002-03-26
DE60015882T2 (de) 2005-12-08
FR2798480A1 (fr) 2001-03-16

Similar Documents

Publication Publication Date Title
EP1083471B1 (de) Spannungsregler
EP0110775B1 (de) Regulierungseinrichtung mit kleiner Verlustspannung
EP1366402B1 (de) Spannungsregler mit kurzschlussschutz
EP0462023B1 (de) Statischer Schalter
EP1079525B1 (de) System zur Steuerung eines Zweirichtungs-Schalters mit zwei Transistoren
EP1148405A1 (de) Linearer Regler mit niedriger Überspannung im Übergangszustand
FR2737058A1 (fr) Combinaison de batteries et d'un controleur dans un vehicule
EP0847124B1 (de) Notstromversorgungseinrichtung zur provisorischen Stromversorgung im Falle eines Versagens der Hauptstromversorgung
FR2893770A1 (fr) Dispositif de gestion d'alimentation d'un reseau de consommateurs pour vehicule automobile
EP1093044A1 (de) Linearer Regler mit niedrigem seriellen Spannungsabfall
FR2908943A1 (fr) Circuit d'alimentation d'amplification de commutation
EP1089154A1 (de) Linearer Regler mit Ausgangsspannungauswahl
EP1274105A1 (de) Verfahren und Vorrichtung zum Ausbalancieren von Superkapazitäten
WO2005074109A1 (fr) Gestion du court-circuit dans une inductance d'un convertisseur elevateur de tension
EP0710052B1 (de) Elektronische Startschaltung für eine Leuchtstofflampe
FR2791193A1 (fr) Procede de controle du fonctionnement d'une pompe de charge capacitive et dispositif de pompe de charge capacitive correspondant
FR2786623A1 (fr) Procede de commande de charge et de decharge
EP0307325B1 (de) Steuerungskreis für eine Zündung
EP0551053B1 (de) Vorrichtung zum Anhalten einer einphasigen Asynchronmaschine mit Kondensator
FR2818761A1 (fr) Dispositif et procede de regulation de tension
EP0837545B1 (de) Nullspannungssteuerschaltung für einen Triac
EP1701531B1 (de) Unterspannungsunterdrückungsschaltung
EP3883105A1 (de) Vorrichtung zum entladen eines kondesators
EP1848087B1 (de) Vorrichtung und Verfahren zur Selbstregulierung der Ladung eines elektrochemischen Generators
WO2021250254A1 (fr) Convertisseur de tension dc/dc avec dispositif de precharge

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

17P Request for examination filed

Effective date: 20010709

AKX Designation fees paid

Free format text: DE FR GB IT

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: STMICROELECTRONICS S.A.

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: STMICROELECTRONICS SA

17Q First examination report despatched

Effective date: 20030424

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20041117

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REF Corresponds to:

Ref document number: 60015882

Country of ref document: DE

Date of ref document: 20041223

Kind code of ref document: P

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 20050322

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20050818

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 17

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 18

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20190820

Year of fee payment: 20

Ref country code: FR

Payment date: 20190820

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20190820

Year of fee payment: 20

REG Reference to a national code

Ref country code: DE

Ref legal event code: R071

Ref document number: 60015882

Country of ref document: DE

REG Reference to a national code

Ref country code: GB

Ref legal event code: PE20

Expiry date: 20200907

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20200907