EP1148404B1 - Voltage regulator with low power consumption - Google Patents

Voltage regulator with low power consumption Download PDF

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Publication number
EP1148404B1
EP1148404B1 EP01108243A EP01108243A EP1148404B1 EP 1148404 B1 EP1148404 B1 EP 1148404B1 EP 01108243 A EP01108243 A EP 01108243A EP 01108243 A EP01108243 A EP 01108243A EP 1148404 B1 EP1148404 B1 EP 1148404B1
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Prior art keywords
amplifier
voltage
regulator
transistor
output
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German (de)
French (fr)
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EP1148404A1 (en
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Nicolas Marty
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STMicroelectronics SA
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STMicroelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the amplifier includes low-voltage current sources current when the amplifier is paused.
  • FIG. 4 represents a regulator 20 according to the invention, powered here by a voltage Vbat supplied by a battery 21.
  • the regulator 20 includes as that of Figure 1 a differential amplifier 22 whose output controls the gate of a transistor of regulation 23 of PMOS type. Drain D of transistor 23 is connected to the output of the regulator 20 and is connected to a Cst stabilization capability in parallel with a load Z, these various elements being arranged as described in the preamble.
  • the output voltage Vout is brought back to the positive input of amplifier 2 by via a divider bridge comprising two resistors R1, R2.
  • the resistance R1 can be zero in the case of a direct feedback of the voltage of output Vout on the input of the amplifier 22, the R2 resistance being in this case mathematically infinite.
  • the reference voltage Vref applied to the input negative of the amplifier 2 is for example a voltage so-called band gap with good stability in temperature function, generated by means of diodes at PN junction and current mirrors.
  • the voltage Vref is thus independent of the voltage Vbat, provided to be lower than the lowest value of the voltage Vbat.
  • the amplifier 22 has a "normal" operating mode and a “sleep” mode and toggle from one to the other according to the value of a signal Vlc applied to an LCIN input provided for this purpose.
  • Setting in standby of the amplifier 22 consists, according to the invention, in placing the amplifier in a state of low power consumption while now the grid voltage Vg to a potential ensuring the maintenance of the regulating transistor 23 in the passing state.
  • the amplifier switches to standby mode when the signal Vlc goes to 1.
  • the signal Vlc is delivered by a comparator 24 receiving on its positive input the output voltage Vout and on its negative input the supply voltage Vbat, the comparator 24 being powered by the voltage Vbat.
  • the comparator 24 is a threshold comparator Vd1 and here puts its output at 1 (signal Vlc) when the voltage differential Vd seen on its inputs, equal to the difference between the voltage Vbat and the voltage Vout, becomes lower than the threshold Vd1.
  • comparator 24 presents also preferably a switching hysteresis and resets its output to 0 when the differential voltage Vd goes up and becomes greater than a higher threshold Vd2 at Vd1.
  • the thresholds Vd1, Vd2 are for example equal to 100 mV and 120mV, respectively.
  • the amplifier 22 switches to sleep mode while maintaining the regulating transistor 23 in the on state, when the regulator 20 operates in follower mode due to a voltage drop Vbat power below the nominal value Voutnom of the output voltage.
  • the differential voltage Vd reaches a minimum value Vdmin which corresponds to the fall of voltage at the terminals of the regulating transistor 23.
  • This voltage drop Vdmin is in principle very low, by example 50 mV because the regulating transistor of a LDO type regulator typically presents a drain-source resistor VdsON in the very on-state low. From the instant t2, the voltage Vout begins to decrease and follows the voltage Vbat, the offset near the voltage Vdmin.
  • the transition to follower mode is detected by the comparator 24 at a time t1 preceding t2 but very close to t2, when the voltage differential Vd reaches the threshold Vd1 mentioned more high, chosen very close to the minimum Vdmin. So, at the time t1, the signal Vlc goes to 1 (FIG 5C) and amplifier 2 is put on standby.
  • the logical "1" of the signal Vlc is here the voltage Vbat, which feeds the comparator 24.
  • the voltage Vbat then goes back to its nominal value, for example after recharging the battery 21 or regeneration natural of it when the current consumed decreases.
  • the voltage Vbat exceeds the value Voutnom.
  • the voltage differential Vd exceeds threshold Vd2 and the amplifier 22 switches to its normal operating mode, the voltage Vout returning to its nominal value Voutnom.
  • the transistor 27 pulls the amplifier output at 0 (voltage Vg) to maintain the regulating transistor 23 in the on state.
  • This embodiment 22c is therefore different from previous 22a, 22b by the fact that in standby mode the voltage of gate Vg is not grounded by the transistor NMOS 2 of the output stage of amplifier 2, which is off but by the additional transistor 27 meant for that purpose.
  • the amplifier 22d shown in FIG. 9 comprises also the amplifier 2 and the transistor 26 assuring turning off the amplifier 2 when the Vlc signal is at 1.
  • the low-pull transistor 27 (pull down) at the output of the amplifier 22c is replaced by a more advanced polarization stage 30 that keeps the output of the amplifier 2 at a voltage Vg greater than the mass when it is off.
  • This voltage Vg is chosen so that the voltage gate-source Vgs of the regulating transistor 23 is maintained in the vicinity of the threshold voltage Vtp of the transistor 23.
  • the polarization step 30 comprises for example a first PMOS transistor 31 receiving the voltage Vbat on its source, connected by its drain to the source of a second PMOS transistor 32 whose drain is connected to the output node of the amplifier 22d.
  • Transistors 31, 32 are arranged in diodes, each having its gate connected to its drain.
  • the bias stage 30 includes a resistor 33 high value in series with an NMOS transistor 34 driven by the signal Vlc.
  • the signal Vlc is at 0 and the transistor 34 is also blocked.
  • the amplifier 2 works as if the polarization stage 30 did not exist not.
  • the voltage Vg tends to 0, the signal Vlc goes to 1 and the amplifier 2 is turned off.
  • the two diode transistors 31, 32 become passersby and each impose a voltage Vtp to their terminals, so that the gate voltage Vg is in this case equal to [Vbat - (2Vtp)].
  • the voltage Vgs of regulation transistor 23 is thus equal to 2Vtp in absolute value and is close to Vtp (at the Vtp value near, of the order of 0.7 V). Other methods are good heard conceivable to maintain the voltage Vg still closer to the threshold voltage Vtp.
  • each of the amplifiers 22a to 22d may be provided for making other variants of production.
  • the polarization stage 30 of the amplifier 22d can be incorporated into the amplifiers 22a, 22b. It is also within the reach of those skilled in the art of applying the principles and solutions exposed above to amplifier structures known other than that of the amplifier 2 chosen here for example.
  • the examples which have just been described relate to a regulator having a PMOS type control transistor, it enters as part of this application and he is at the reach of the skilled person to transpose teaching of the present invention to regulators having a NMOS-type control transistor.

Description

La présente invention concerne les régulateurs de tension linéaires du type LDO (Low Drop Out Regulators), c'est-à-dire à faible chute de tension série.The present invention relates to regulators of linear voltage of the type LDO (Low Drop Out Regulators), i.e. low series voltage drop.

De tels régulateurs font l'objet de diverses applications, notamment dans le domaine des téléphones mobiles pour délivrer une tension régulée à des circuits d'émission-réception radio à partir d'une tension d'alimentation fournie par une batterie.Such regulators are subject to various applications, especially in the field of telephones mobile devices to deliver regulated voltage to circuits radio transmission-reception from a voltage power supply provided by a battery.

A titre d'exemple, la figure 1 représente un régulateur linéaire classique 10 dont la sortie délivre une tension régulée Vout à une charge Z. La charge Z représente par exemple divers circuits radio présents dans un téléphone mobile. Le régulateur 10 est alimenté électriquement par une tension Vbat délivrée par une batterie 1 et comprend un amplificateur différentiel 2 dont la sortie pilote la grille G d'un transistor de régulation 3 du type PMOS. Le transistor 3 est généralement un transistor à faible résistance série à l'état passant (résistance drain-source RdsON) et reçoit sur sa source S la tension Vbat. Son drain D, relié à la sortie du régulateur 10, est connecté à l'anode d'un condensateur Cst de filtrage et de stabilisation de la tension Vout, agencé en parallèle avec la charge Z. L'amplificateur 2 reçoit sur son entrée négative une tension de référence Vref et sur son entrée positive une tension de contre-réaction Vfb (feed-back). La tension Vfb est une fraction de la tension Vout ramenée sur l'entrée de l'amplificateur 2 par l'intermédiaire d'un pont diviseur comprenant deux résistances R1, R2.By way of example, FIG. conventional linear regulator 10 whose output delivers a regulated voltage Vout at a load Z. The load Z represents for example various radio circuits present in a mobile phone. The regulator 10 is powered electrically by a voltage Vbat delivered by a battery 1 and includes a differential amplifier 2 whose output drives the gate G of a transistor of regulation 3 of the PMOS type. The transistor 3 is generally a low resistance transistor series to the passing state (drain-source resistance RdsON) and receives on its source S the voltage Vbat. Its drain D, connected to the output of regulator 10, is connected to the anode of a capacitor Cst filtering and stabilizing the voltage Vout, arranged in parallel with the load Z. The amplifier 2 receives on its negative input a reference voltage Vref and on its positive input a feedback voltage Vfb (feedback). Voltage Vfb is a fraction of the voltage Vout brought back on the input of the amplifier 2 via a divider bridge comprising two resistors R1, R2.

Le fonctionnement d'un tel régulateur, bien connu de l'homme de l'art, consiste dans une modulation de la tension de grille Vg du transistor 3 par l'amplificateur en fonction de l'écart entre la tension Vfb et la tension de référence Vref, que l'amplificateur maintient au voisinage de 0. Lorsque la tension Vg est inférieure à la valeur [Vbat - Vtp], le transistor 3 est passant car sa tension grille-source Vgs est supérieure à sa tension de seuil Vtp. Lorsque la tension Vg est supérieure à [Vbat - Vtp], le transistor est bloqué. En régime stabilisé, la tension Vout est régulée au voisinage de sa valeur nominale Voutnom, égale à [(R1+R2)Vref/R2].The operation of such a regulator, well known of those skilled in the art, consists in a modulation of the gate voltage Vg of transistor 3 by the amplifier according to the difference between the voltage Vfb and the voltage Vref reference, which the amplifier maintains at neighborhood of 0. When the voltage Vg is lower than the value [Vbat - Vtp], the transistor 3 is passing because its gate-source voltage Vgs is greater than its voltage of threshold Vtp. When the voltage Vg is greater than [Vbat - Vtp], the transistor is blocked. In regime stabilized, the voltage Vout is regulated in the vicinity of its nominal value Voutnom, equal to [(R1 + R2) Vref / R2].

La figure 2 représente un mode de réalisation classique de l'amplificateur 2. Celui-ci comprend un étage différentiel représenté sous la forme d'un bloc 5, recevant en entrée les tensions Vref et Vfb et polarisé par un générateur de courant 6. La sortie de l'étage différentiel 5 pilote la grille d'un transistor 7 de type NMOS connecté entre le noeud de sortie de l'amplificateur 2 et la masse. Le transistor 7 est polarisé sur son drain D par un générateur de courant 8. Le noeud de sortie de l'amplificateur est relié à la tension d'alimentation Vbat par une résistance de grille Rg, qui détermine le gain de l'amplificateur et le courant maximal qu'il peut délivrer en sortie. Ainsi, selon la valeur du signal délivré par l'étage différentiel 5, le transistor 7 tire la sortie de l'amplificateur vers la masse ou la résistance Rg tire la sortie vers le haut, c'est-à-dire la tension Vbat.FIG. 2 represents an embodiment classic amplifier 2. This includes a differential stage represented in the form of a block 5, receiving as input the Vref and Vfb voltages and polarized by a current generator 6. The output of the floor differential 5 drives the gate of a transistor 7 type NMOS connected between the output node of the amplifier 2 and the mass. The transistor 7 is biased on its drain D by a current generator 8. The output node of the amplifier is connected to the supply voltage Vbat by a gate resistance Rg, which determines the gain of the amplifier and the maximum current that it can to deliver in output. So, depending on the signal value delivered by the differential stage 5, the transistor 7 pulls the output of the amplifier to the ground or the resistance Rg pulls the output upwards, that is to say the voltage Vbat.

Dans une application telle que l'alimentation électrique d'un téléphone mobile, il est important que l'amplificateur de régulation présente une consommation électrique aussi faible que possible afin de préserver l'autonomie de la batterie. A cet effet, la résistance de grille Rg est choisie de forte valeur, par exemple 100KΩ, afin de limiter le courant circulant dans l'étage de sortie. Egalement, les courants délivrés par les générateurs 6, 8 sont calibrés de façon adéquate. De façon générale, le choix de la résistance Rg et des courants de polarisation est le résultat d'un compromis entre la nécessité de piloter efficacement le transistor 3, qui présente généralement une capacité parasite de grille élevée, et la recherche d'une faible consommation.In an application such as food electric of a mobile phone, it is important that the regulation amplifier has a consumption as low as possible in order to preserve the battery life. For this purpose, the resistance of Rg grid is chosen high value, for example 100KΩ, to limit the current flowing in the floor Release. Also, the currents delivered by generators 6, 8 are suitably calibrated. Of generally, the choice of resistance Rg and polarization currents is the result of a compromise between the need to effectively steer the transistor 3, which generally has a capacitance high grid parasite, and looking for a weak consumption.

Bien que cette consommation, typiquement de l'ordre de 50 à 200 microampères, soit en soi acceptable lorsque la batterie est bien chargée et que le régulateur fonctionne en régime stabilisé, la présente invention se fonde sur le postulat que cette consommation doit par contre être considérée trop élevée lorsque la tension de batterie Vbat devient faible et inférieure à la valeur nominale Voutnom de la tension de sortie. Une telle chute de la tension Vbat en dessous de la tension nominale Voutnom peut être temporaire et due à une forte consommation de courant, ou être due au fait que la batterie est déchargée.Although this consumption, typically of the order from 50 to 200 microamperes, which is in itself acceptable when the battery is well charged and that the regulator operating in steady state, the present invention is based on the assumption that this consumption against being considered too high when the tension of Vbat battery becomes low and lower than the value nominal Voutnom of the output voltage. Such a fall the voltage Vbat below the rated voltage Voutnom can be temporary and due to a strong current consumption, or be due to the fact that the battery is discharged.

En effet, selon des constatations et conclusions faisant partie intégrante de la présente invention, illustrées sur les figures 3A, 3B, et 3C, le passage de la tension Vbat en dessous de la valeur Voutnom à un instant tA (fig. 3A) fait que la tension de contre-réaction Vfb devient inférieure à Vref à l'entrée de l'amplificateur 2. Ce dernier est déséquilibré et fait baisser jusqu'à la masse la tension de grille Vg pour rattraper le déséquilibre (fig. 3B). Le transistor de régulation 3 est continuellement passant, la tension Vout devient sensiblement égale à la tension Vbat (fig. 3C) et le régulateur 10 fonctionne en mode "suiveur". Le noeud de sortie de l'amplificateur 2 étant à la masse, on voit en figure 2 que la consommation dans la résistance de grille Rg est maximale.Indeed, according to findings and conclusions integral part of the present invention, illustrated in FIGS. 3A, 3B, and 3C, the passage of the voltage Vbat below the value Voutnom to a moment tA (Fig. 3A) causes the feedback voltage Vfb becomes lower than Vref at the input of amplifier 2. The latter is unbalanced and down to ground the gate voltage Vg for to make up for the imbalance (Fig. 3B). The transistor of regulation 3 is continuously passing, voltage Vout becomes substantially equal to the voltage Vbat (FIG 3C) and the regulator 10 operates in "follower" mode. The node of output of amplifier 2 being grounded, we see figure 2 that consumption in the gate resistor Rg is maximal.

Ainsi, l'amplificateur consomme inutilement du courant lorsque le régulateur fonctionne en mode suiveur, puisque le transistor de régulation est continuellement dans l'état passant et qu'une régulation de la tension de sortie Vout n'est plus possible. Thus, the amplifier consumes unnecessarily current when the controller is operating in follower mode, since the regulating transistor is continuously in the on state and that a regulation of the voltage of Exit Vout is no longer possible.

Pour pallier cet inconvénient, l'idée de la présente invention est de faire basculer l'amplificateur de régulation dans un mode de veille à faible consommation tout en maintenant dans l'état passant le transistor de régulation.To overcome this drawback, the idea of present invention is to switch the amplifier control in a low sleep mode consumption while maintaining in the passing state the regulating transistor.

Plus particulièrement, la présente invention prévoit un régulateur de tension selon la revendication 1.More particularly, the present invention provides a voltage regulator according to claim 1.

Selon un mode de réalisation, le régulateur comprend un comparateur agencé pour comparer la tension d'alimentation et la tension de sortie du régulateur, et délivrer à l'amplificateur un signal de mise en veille lorsque l'écart entre la tension d'alimentation et la tension de sortie du régulateur est inférieur au premier seuil.According to one embodiment, the regulator comprises a comparator arranged to compare the voltage power supply and the output voltage of the regulator, and deliver to the amplifier a sleep signal when the difference between the supply voltage and the regulator output voltage is lower than the first threshold.

Selon un mode de réalisation, le comparateur présente une hystérésis de commutation et annule le signal de mise en veille de l'amplificateur lorsque l'écart entre la tension d'alimentation et la tension de sortie du régulateur est supérieur à un second seuil supérieur au premier seuil.According to one embodiment, the comparator has a switching hysteresis and cancels the signal of standby of the amplifier when the difference between the supply voltage and the voltage of regulator output is greater than a second threshold greater than the first threshold.

Selon un mode de réalisation, l'amplificateur comprend une résistance reliant la sortie de l'amplificateur à la tension d'alimentation, un interrupteur est agencé en série avec la résistance, l'interrupteur en série avec la résistance est ouvert lorsque l'amplificateur est mis en veille et fermé dans le cas contraire.According to one embodiment, the amplifier includes a resistor connecting the output of the amplifier to the supply voltage, a switch is arranged in series with the resistor, the switch in series with the resistor is open when the amplifier is paused and closed in the opposite case.

Selon un mode de réalisation, l'amplificateur comprend des sources de courant basculant en mode faible courant lorsque l'amplificateur est mis en veille.According to one embodiment, the amplifier includes low-voltage current sources current when the amplifier is paused.

Selon un mode de réalisation, l'amplificateur comprend un interrupteur piloté par un signal de mise en veille pour connecter la grille du transistor de régulation à un potentiel électrique rendant le transistor passant lorsque l'amplificateur est mis en veille.According to one embodiment, the amplifier includes a switch controlled by a setting signal standby to connect the transistor gate of regulation to an electrical potential making the transistor going on when the amplifier is put in Eve.

Selon un mode de réalisation, l'amplificateur comprend un étage de polarisation de la grille du transistor de régulation, agencé pour appliquer sur la grille du transistor de régulation, lorsque l'amplificateur est mis en veille, une tension qui est déterminée de manière que la tension grille-source du transistor de régulation soit proche de la tension de seuil du transistor de régulation.According to one embodiment, the amplifier includes a polarization stage of the gate of regulating transistor, arranged to apply on the gate of the regulating transistor, when the amplifier is put to sleep, a voltage that is determined so that the gate-source voltage of the regulating transistor is close to the voltage of threshold of the regulating transistor.

Selon un mode de réalisation, l'alimentation électrique de l'amplificateur est supprimée en mode veille par un interrupteur.According to one embodiment, the power supply electrical amplifier is removed in mode watch by a switch.

La présente invention concerne également un téléphone mobile comprenant une batterie et des circuits radio alimentés par l'intermédiaire d'un régulateur selon l'invention.The present invention also relates to a mobile phone including a battery and circuits radio powered through a regulator according to the invention.

La présente invention prévoit également un procédé de gestion de l'énergie disponible dans une batterie selon la revendication 10. The present invention also provides a method for management of energy available in a battery according to claim 10.

Selon un mode de réalisation, on réactive l'amplificateur lorsque l'écart entre la tension d'alimentation et la tension de sortie du régulateur est supérieur à un second seuil supérieur au premier seuil.According to one embodiment, one reactivates the amplifier when the gap between the voltage power supply and the output voltage of the regulator is greater than a second threshold greater than the first threshold.

La consommation de l'amplificateur peut être réduite en mode veille en déconnectant le noeud de sortie de l'amplificateur de la tension d'alimentation, en diminuant le courant délivré par des sources de courant internes à l'amplificateur, ou en supprimant l'application de la tension d'alimentation.The power consumption of the amplifier can be reduced in standby mode by disconnecting the output node of the supply voltage amplifier, in decreasing the current delivered by current sources internal to the amplifier, or removing the application of the supply voltage.

Lorsque l'amplificateur est mis en veille, il est avantageux d'appliquer sur la grille du transistor de régulation une tension de grille qui est déterminée de manière que la tension grille-source du transistor de régulation soit proche de sa tension de seuil.When the amplifier is paused, it is advantageous to apply to the gate of the transistor of regulating a gate voltage which is determined from way that the gate-source voltage of the transistor of regulation is close to its threshold voltage.

Ces objets, caractéristiques et avantages ainsi que d'autres de la présente invention seront exposés plus en détail dans la description suivante d'un exemple de réalisation d'un régulateur selon l'invention, faite à titre non limitatif en relation avec les figures jointes, parmi lesquelles :

  • la figure 1 précédemment décrite est le schéma électrique d'un régulateur de tension classique,
  • la figure 2 précédemment décrite est le schéma électrique d'un amplificateur présent dans le régulateur de la figure 1,
  • les figures 3A à 3C représentent des signaux électriques et illustrent le fonctionnement du régulateur de tension lorsque la tension d'alimentation chute en dessous de la valeur nominale de la tension de sortie,
  • la figure 4 est le schéma électrique d'un régulateur de tension selon l'invention,
  • les figures 5A à 5C représentent des signaux électriques et illustrent le fonctionnement du régulateur selon l'invention en mode suiveur, et
  • les figures 6 à 9 sont des schémas électriques de quatre variantes de réalisation d'un amplificateur selon l'invention présent dans le régulateur de la figure 4.
These and other objects, features and advantages of the present invention will be set out in more detail in the following description of an exemplary embodiment of a regulator according to the invention, given in a non-limiting manner in relation to the accompanying figures. , among :
  • FIG. 1 previously described is the electrical diagram of a conventional voltage regulator,
  • FIG. 2 previously described is the circuit diagram of an amplifier present in the regulator of FIG. 1,
  • FIGS. 3A to 3C show electrical signals and illustrate the operation of the voltage regulator when the supply voltage drops below the nominal value of the output voltage,
  • FIG. 4 is the electrical diagram of a voltage regulator according to the invention,
  • FIGS. 5A to 5C represent electrical signals and illustrate the operation of the regulator according to the invention in follower mode, and
  • FIGS. 6 to 9 are electrical diagrams of four alternative embodiments of an amplifier according to the invention present in the regulator of FIG. 4.

La figure 4 représente un régulateur 20 selon l'invention, alimenté ici par une tension Vbat fournie par une batterie 21. Le régulateur 20 comprend comme celui de la figure 1 un amplificateur différentiel 22 dont la sortie commande la grille d'un transistor de régulation 23 de type PMOS. Le drain D du transistor 23 est relié à la sortie du régulateur 20 et est connecté à une capacité de stabilisation Cst en parallèle avec une charge Z, ces divers éléments étant agencés comme décrit au préambule. La tension de sortie Vout est ramenée sur l'entrée positive de l'amplificateur 2 par l'intermédiaire d'un pont diviseur comprenant deux résistances R1, R2. La résistance R1 peut être nulle dans le cas d'une contre-réaction directe de la tension de sortie Vout sur l'entrée de l'amplificateur 22, la résistance R2 étant dans ce cas mathématiquement infinie. La tension de référence Vref appliquée sur l'entrée négative de l'amplificateur 2 est par exemple une tension dite de band-gap présentant une bonne stabilité en fonction de la température, générée au moyen de diodes à jonction PN et de miroirs de courant. La tension Vref est ainsi indépendante de la tension Vbat, à la condition d'être inférieure à la plus basse valeur de la tension Vbat.FIG. 4 represents a regulator 20 according to the invention, powered here by a voltage Vbat supplied by a battery 21. The regulator 20 includes as that of Figure 1 a differential amplifier 22 whose output controls the gate of a transistor of regulation 23 of PMOS type. Drain D of transistor 23 is connected to the output of the regulator 20 and is connected to a Cst stabilization capability in parallel with a load Z, these various elements being arranged as described in the preamble. The output voltage Vout is brought back to the positive input of amplifier 2 by via a divider bridge comprising two resistors R1, R2. The resistance R1 can be zero in the case of a direct feedback of the voltage of output Vout on the input of the amplifier 22, the R2 resistance being in this case mathematically infinite. The reference voltage Vref applied to the input negative of the amplifier 2 is for example a voltage so-called band gap with good stability in temperature function, generated by means of diodes at PN junction and current mirrors. The voltage Vref is thus independent of the voltage Vbat, provided to be lower than the lowest value of the voltage Vbat.

Le fonctionnement du régulateur 20 en régime stabilisé est en soi classique et ne sera pas à nouveau décrit. L'amplificateur 2 maintient la tension de contre-réaction Vfb égale à la tension de référence Vref et la tension de sortie nominale Voutnom est égale à [(R1+R2)Vref/R2].The operation of the regulator 20 in regime stabilized is in itself classic and will not be again described. Amplifier 2 maintains the feedback voltage Vfb equal to the reference voltage Vref and the rated output voltage Voutnom is equal to [(R1 + R2) Vref / R2].

Selon l'invention, l'amplificateur 22 présente un mode de fonctionnement "normal" et un mode "veille" et bascule de l'un à l'autre selon la valeur d'un signal Vlc appliqué sur une entrée LCIN prévue à cet effet. La mise en veille de l'amplificateur 22 consiste, selon l'invention, dans le fait de placer l'amplificateur dans un état de faible consommation électrique tout en maintenant la tension de grille Vg à un potentiel assurant le maintient du transistor de régulation 23 dans l'état passant. Divers exemples de réalisation de l'amplificateur 22 seront décrits plus loin. On considèrera par convention, dans ce qui suit, que l'amplificateur bascule en mode veille lorsque le signal Vlc passe à 1.According to the invention, the amplifier 22 has a "normal" operating mode and a "sleep" mode and toggle from one to the other according to the value of a signal Vlc applied to an LCIN input provided for this purpose. Setting in standby of the amplifier 22 consists, according to the invention, in placing the amplifier in a state of low power consumption while now the grid voltage Vg to a potential ensuring the maintenance of the regulating transistor 23 in the passing state. Various examples of realization of the amplifier 22 will be described later. We consider by convention, in the following, that the amplifier switches to standby mode when the signal Vlc goes to 1.

Le signal Vlc est délivré par un comparateur 24 recevant sur son entrée positive la tension de sortie Vout et sur son entrée négative la tension d'alimentation Vbat, le comparateur 24 étant alimenté par la tension Vbat. Le comparateur 24 est un comparateur à seuil Vd1 et met ici sa sortie à 1 (signal Vlc) lorsque la tension différentielle Vd vue sur ses entrées, égale à la différence entre la tension Vbat et la tension Vout, devient inférieure au seuil Vd1. Pour des raisons de stabilité de sa sortie, le comparateur 24 présente également, de préférence, une hystérésis de commutation et remet sa sortie à 0 lorsque la tension différentielle Vd remonte et devient supérieure à un seuil Vd2 supérieur à Vd1. Les seuils Vd1, Vd2 sont par exemple égaux à 100 mV et 120mV, respectivement.The signal Vlc is delivered by a comparator 24 receiving on its positive input the output voltage Vout and on its negative input the supply voltage Vbat, the comparator 24 being powered by the voltage Vbat. The comparator 24 is a threshold comparator Vd1 and here puts its output at 1 (signal Vlc) when the voltage differential Vd seen on its inputs, equal to the difference between the voltage Vbat and the voltage Vout, becomes lower than the threshold Vd1. For reasons of stability of its output, comparator 24 presents also preferably a switching hysteresis and resets its output to 0 when the differential voltage Vd goes up and becomes greater than a higher threshold Vd2 at Vd1. The thresholds Vd1, Vd2 are for example equal to 100 mV and 120mV, respectively.

Ainsi, comme on va le voir plus en détail dans ce qui suit, l'amplificateur 22 bascule dans le mode veille tout en maintenant le transistor de régulation 23 dans l'état passant, lorsque le régulateur 20 fonctionne en mode suiveur en raison d'une chute de la tension d'alimentation Vbat en dessous de la valeur nominale Voutnom de la tension de sortie.So, as we will see in more detail in this following, the amplifier 22 switches to sleep mode while maintaining the regulating transistor 23 in the on state, when the regulator 20 operates in follower mode due to a voltage drop Vbat power below the nominal value Voutnom of the output voltage.

Les figures 5A, 5B, 5C illustrent le fonctionnement du régulateur 20 en mode suiveur et représentent respectivement les tensions Vbat et Vout, la tension différentielle Vd et le signal Vlc. Sur les figures 5A et 5B, on voit qu'une diminution de la tension Vbat à partir de sa valeur nominale Vbatnom n'a pas de conséquence sur la tension régulée Vout, qui demeure égale à Voutnom, tant que la tension Vbat reste supérieure à Voutnom. La tension différentielle Vd diminue proportionnellement à la tension Vbat jusqu'à un instant t2 où la tension Vbat devient sensiblement égale à Voutnom et entraíne la tension Vout dans sa chute, le régulateur étant alors déséquilibré et fonctionnant en mode suiveur. A cet instant t2, la tension différentielle Vd atteint une valeur minimale Vdmin qui correspond à la chute de tension aux bornes du transistor de régulation 23. Cette chute de tension Vdmin est en principe très faible, par exemple 50 mV, car le transistor de régulation d'un régulateur de type LDO présente généralement une résistance drain-source VdsON dans l'état passant très faible. A compter de l'instant t2, la tension Vout commence à diminuer et suit la tension Vbat, au décalage près de la tension Vdmin.Figures 5A, 5B, 5C illustrate the operation of the regulator 20 in follower mode and represent respectively the voltages Vbat and Vout, the voltage differential Vd and signal Vlc. In FIGS. 5A and 5B, we see that a decrease in the voltage Vbat from of its nominal value Vbatnom has no consequence on the regulated voltage Vout, which remains equal to Voutnom, as long as the voltage Vbat remains higher than Voutnom. The differential voltage Vd decreases proportionally to the voltage Vbat up to a time t2 where the voltage Vbat becomes substantially equal to Voutnom and drives the voltage Vout in its fall, the regulator being then unbalanced and operating in follower mode. In this moment t2, the differential voltage Vd reaches a minimum value Vdmin which corresponds to the fall of voltage at the terminals of the regulating transistor 23. This voltage drop Vdmin is in principle very low, by example 50 mV because the regulating transistor of a LDO type regulator typically presents a drain-source resistor VdsON in the very on-state low. From the instant t2, the voltage Vout begins to decrease and follows the voltage Vbat, the offset near the voltage Vdmin.

Selon l'invention, le passage en mode suiveur est détecté par le comparateur 24 à un instant t1 précédant t2 mais très proche de t2, lorsque la tension différentielle Vd atteint le seuil Vd1 mentionné plus haut, choisi très proche du minimum Vdmin. Ainsi, à l'instant t1, le signal Vlc passe à 1 (fig. 5C) et l'amplificateur 2 est mis en veille. Le "1" logique du signal Vlc est ici la tension Vbat, qui alimente le comparateur 24.According to the invention, the transition to follower mode is detected by the comparator 24 at a time t1 preceding t2 but very close to t2, when the voltage differential Vd reaches the threshold Vd1 mentioned more high, chosen very close to the minimum Vdmin. So, at the time t1, the signal Vlc goes to 1 (FIG 5C) and amplifier 2 is put on standby. The logical "1" of the signal Vlc is here the voltage Vbat, which feeds the comparator 24.

Sur les figures 5A à 5C, ont voit que la tension Vbat remonte ensuite vers sa valeur nominale, par exemple après rechargement de la batterie 21 ou régénération naturelle de celle-ci lorsque le courant consommé diminue. A un instant t3, la tension Vbat dépasse la valeur Voutnom. A un instant t4, la tension différentielle Vd dépasse le seuil Vd2 et l'amplificateur 22 bascule dans son mode de fonctionnement normal, la tension Vout revenant à sa valeur nominale Voutnom.In FIGS. 5A to 5C, have seen that the voltage Vbat then goes back to its nominal value, for example after recharging the battery 21 or regeneration natural of it when the current consumed decreases. At a time t3, the voltage Vbat exceeds the value Voutnom. At a time t4, the voltage differential Vd exceeds threshold Vd2 and the amplifier 22 switches to its normal operating mode, the voltage Vout returning to its nominal value Voutnom.

On va maintenant décrire à titre non limitatif divers modes de réalisation de l'amplificateur 22, obtenus à partir de la structure de l'amplificateur 2 décrit au préambule en relation avec la figure 2.We will now describe without limitation various embodiments of the amplifier 22, obtained from the structure of the amplifier 2 described in the preamble in relation to FIG.

L'amplificateur 22a illustré en figure 6 est d'une structure semblable à celle de l'amplificateur 2. On y retrouve l'étage différentiel 5 polarisé par le générateur de courant 6, dont la sortie pilote le transistor NMOS 7 polarisé sur son drain par le générateur de courant 8, ainsi que la résistance Rg reliant le noeud de sortie de l'amplificateur 22a à la tension Vbat. Selon l'invention, un interrupteur 25, ici un transistor PMOS, est agencé en série avec la résistance Rg. Le transistor 25 reçoit sur sa grille le signal Vlc et est ainsi en permanence dans l'état passant lorsque le régulateur fonctionne en régime stabilisé, le signal Vlc étant à 0 comme indiqué plus haut. Lorsque le régulateur fonctionne en mode suiveur et que la tension Vg sur le noeud de sortie est tirée vers la masse par le transistor NMOS 7, le signal Vlc passe à 1, le transistor 25 se bloque et aucun courant ne passe dans la résistance Rg. En coupant ainsi le chemin reliant le noeud de sortie de l'amplificateur 22a à la tension Vbat, l'économie en consommation de courant peut être substantielle et de l'ordre de 80%.The amplifier 22a illustrated in FIG. structure similar to that of amplifier 2. There found the differential stage 5 polarized by the current generator 6, whose output drives the NMOS transistor 7 biased on its drain by the current generator 8, as well as the resistance Rg connecting the output node of the amplifier 22a to the voltage Vbat. According to the invention, a switch 25, here a PMOS transistor is arranged in series with the resistance Rg. The transistor 25 receives on its gate the signal Vlc and is thus permanently in the passing state when the regulator operates in steady state, the signal Vlc being at 0 as indicated above. When the regulator operates in follower mode and that the voltage Vg on the output node is pulled to the ground by the NMOS transistor 7, the signal Vlc goes to 1, the transistor 25 hangs and no current flows into the resistor Rg. By thus cutting the path connecting the output node from the amplifier 22a to the voltage Vbat, the economy in current consumption can be substantial and the order of 80%.

L'amplificateur 22b représenté en figure 7 est quasiment identique à l'amplificateur 22a. Toutefois, les générateurs de courant 6, 8 ont été remplacés par des générateurs de courant 6', 8' qui sont commandés par le signal Vlc et qui délivrent des courants différents selon la valeur du signal Vlc. Les courants respectifs I1', I2' délivrés lorsque le signal Vlc est à 1 sont par exemple égaux à la moitié des courants I1, I2 délivrés lorsque le signal Vlc est à 0. Les courants I1', I2' sont par exemple de 10 microampères et les courants I1, I2 de 20 microampères. La réalisation de tels générateurs 6', 8' à deux courants de fonctionnement est en soi à la portée de l'homme de l'art, par exemple en agençant en parallèle, dans des miroirs de courants, des transistors de même structure, et en bloquant un transistor sur deux lorsque le signal Vlc est à 1. On économise ainsi, par cet arrangement, quelques dizaines de microampères supplémentaires.The amplifier 22b shown in FIG. almost identical to the amplifier 22a. However, current generators 6, 8 have been replaced by current generators 6 ', 8' which are controlled by the signal Vlc and which deliver different currents according to the value of the signal Vlc. The respective currents I1 ', I2' delivered when the signal Vlc is at 1 are for example equal to half of the currents I1, I2 delivered when the signal Vlc is 0. The currents I1 ', I2' are example of 10 microamperes and currents I1, I2 of 20 microamperes. The realization of such generators 6 ', 8' to two operating currents is in itself within reach of those skilled in the art, for example by arranging in parallel, in current mirrors, transistors likewise structure, and blocking one transistor out of two when the signal Vlc is at 1. It saves thus, by this arrangement, a few dozen microamperes additional.

L'amplificateur 22c de la figure 8 est réalisé à partir de l'amplificateur 2 de la figure 2, que l'on n'a pas modifié dans sa structure interne. Toutefois, la tension Vbat est appliquée sur l'entrée d'alimentation de l'amplificateur 2 par l'intermédiaire d'un transistor PMOS 26 piloté par le signal Vlc. De plus, un transistor NMOS 27 piloté par le signal Vlc est ajouté entre la sortie de l'amplificateur 2 et la masse. Ainsi, lorsque le signal Vlc est à 0 (régulateur équilibré), le transistor 26 est passant et le transistor 27 est bloqué. L'amplificateur 2 fonctionne comme si ces deux éléments n'existaient pas. Lorsque le signal Vlc est à 1 (régulateur en mode suiveur), le transistor 26 est bloqué et le transistor 27 est passant. L'amplificateur 2 ne reçoit plus la tension d'alimentation Vbat et est complètement hors tension. Le transistor 27 tire la sortie de l'amplificateur à 0 (tension Vg) pour maintenir le transistor de régulation 23 dans l'état passant. Ce mode de réalisation 22c se distingue donc des précédents 22a, 22b par le fait qu'en mode veille la tension de grille Vg n'est pas tirée à la masse par le transistor NMOS 2 de l'étage de sortie de l'amplificateur 2, qui est hors service, mais par le transistor supplémentaire 27 prévu à cet effet. The amplifier 22c of FIG. from amplifier 2 of Figure 2, which we did not not modified in its internal structure. However, Vbat voltage is applied on the power input of the amplifier 2 via a transistor PMOS 26 controlled by the signal Vlc. In addition, a transistor NMOS 27 driven by signal Vlc is added between the amplifier 2 output and ground. So when the signal Vlc is at 0 (balanced regulator), the transistor 26 is on and transistor 27 is off. Amplifier 2 works as if these two elements did not exist. When the signal Vlc is 1 (regulator in follower mode), the transistor 26 is blocked and the transistor 27 is passing. Amplifier 2 does not receives more the supply voltage Vbat and is completely off. The transistor 27 pulls the amplifier output at 0 (voltage Vg) to maintain the regulating transistor 23 in the on state. This embodiment 22c is therefore different from previous 22a, 22b by the fact that in standby mode the voltage of gate Vg is not grounded by the transistor NMOS 2 of the output stage of amplifier 2, which is off but by the additional transistor 27 meant for that purpose.

L'amplificateur 22d représenté en figure 9 comprend également l'amplificateur 2 et le transistor 26 assurant la mise hors tension de l'amplificateur 2 lorsque le signal Vlc est à 1. Le transistor tire-bas 27 (pull down) à la sortie de l'amplificateur 22c est remplacé par un étage de polarisation 30 plus perfectionné qui maintient la sortie de l'amplificateur 2 à une tension Vg supérieure à la masse quand celui-ci est hors tension. Cette tension Vg est choisie de manière que la tension grille-source Vgs du transistor de régulation 23 soit maintenue au voisinage de la tension de seuil Vtp du transistor 23.The amplifier 22d shown in FIG. 9 comprises also the amplifier 2 and the transistor 26 assuring turning off the amplifier 2 when the Vlc signal is at 1. The low-pull transistor 27 (pull down) at the output of the amplifier 22c is replaced by a more advanced polarization stage 30 that keeps the output of the amplifier 2 at a voltage Vg greater than the mass when it is off. This voltage Vg is chosen so that the voltage gate-source Vgs of the regulating transistor 23 is maintained in the vicinity of the threshold voltage Vtp of the transistor 23.

L'étape de polarisation 30 comprend par exemple un premier transistor PMOS 31 recevant la tension Vbat sur sa source, connecté par son drain à la source d'un deuxième transistor PMOS 32 dont le drain est connecté au noeud de sortie de l'amplificateur 22d. Les transistors 31, 32 sont agencés en diodes, chacun ayant sa grille connectée à son drain. Entre le noeud de sortie et la masse, l'étage de polarisation 30 comprend une résistance 33 de forte valeur en série avec un transistor NMOS 34 piloté par le signal Vlc. Lorsque le régulateur fonctionne en régime stabilisé, la tension Vg est maintenue autour de la valeur [Vbat - Vtp] par la sortie de l'amplificateur 2, Vtp étant la tension de seuil d'un transistor PMOS, de sorte que les deux transistors-diodes 31, 32 sont bloqués. De plus, le signal Vlc est à 0 et le transistor 34 est également bloqué. L'amplificateur 2 fonctionne comme si l'étage de polarisation 30 n'existait pas. Lorsque régulateur est déséquilibré, la tension Vg tend vers 0, le signal Vlc passe à 1 et l'amplificateur 2 est mis hors tension. Les deux transistors-diodes 31, 32 deviennent passants et imposent chacun une tension Vtp à leurs bornes, de sorte que la tension de grille Vg est dans ce cas égale à [Vbat - (2Vtp)]. La tension Vgs du transistor de régulation 23 est ainsi égale à 2Vtp en valeur absolue et est proche de Vtp (à la valeur Vtp près, de l'ordre de 0,7 V). D'autres méthodes sont bien entendu envisageables pour maintenir la tension Vg encore plus proche de la tension de seuil Vtp.The polarization step 30 comprises for example a first PMOS transistor 31 receiving the voltage Vbat on its source, connected by its drain to the source of a second PMOS transistor 32 whose drain is connected to the output node of the amplifier 22d. Transistors 31, 32 are arranged in diodes, each having its gate connected to its drain. Between the exit node and the mass, the bias stage 30 includes a resistor 33 high value in series with an NMOS transistor 34 driven by the signal Vlc. When the regulator operates in steady state, the voltage Vg is kept around the value [Vbat - Vtp] by the exit of the amplifier 2, Vtp being the threshold voltage of a PMOS transistor, so that the two transistors-diodes 31, 32 are blocked. In addition, the signal Vlc is at 0 and the transistor 34 is also blocked. The amplifier 2 works as if the polarization stage 30 did not exist not. When regulator is unbalanced, the voltage Vg tends to 0, the signal Vlc goes to 1 and the amplifier 2 is turned off. The two diode transistors 31, 32 become passersby and each impose a voltage Vtp to their terminals, so that the gate voltage Vg is in this case equal to [Vbat - (2Vtp)]. The voltage Vgs of regulation transistor 23 is thus equal to 2Vtp in absolute value and is close to Vtp (at the Vtp value near, of the order of 0.7 V). Other methods are good heard conceivable to maintain the voltage Vg still closer to the threshold voltage Vtp.

L'avantage de ce mode de réalisation est de ne pas décharger entièrement la capacité parasite de grille Cg du transistor de régulation 23, représentée en traits pointillés, qui est généralement de forte valeur (100-200 picofarads) avec un transistor de régulation à faible résistance série RdsON. En effet, lorsque la tension Vg est portée à la masse, la capacité Cg est entièrement déchargée pendant le mode veille. Si la tension Vbat remonte brutalement, un retard à la fermeture du transistor 23 (blocage du transistor) se produit lors du retour au mode régulé en raison du temps de charge de la capacité Cg. Un tel retard à la fermeture fait apparaítre une surtension à la sortie du régulateur, car la tension Vout continue de suivre la tension Vbat au-delà de sa valeur nominale Voutnom. En maintenant la tension Vg non nulle pendant le mode veille, la capacité de grille Cg ne se décharge pas entièrement et le basculement du mode veille au mode régulé se fait rapidement, avec une nette atténuation du phénomène de surtension.The advantage of this embodiment is not to completely discharge the parasitic capacitance of grid Cg of the regulating transistor 23, shown in phantom dotted, which is usually of high value (100-200 picofarads) with a low regulation transistor RdsON series resistance. Indeed, when the voltage Vg is brought to the ground, the capacitance Cg is entirely discharged during sleep mode. If the voltage Vbat goes back suddenly, a delay in closing the transistor 23 (transistor blocking) occurs during the back to the regulated mode due to the charging time of the Cg capacity. Such a delay in closing reveals a surge at the output of the regulator because the voltage Vout continues to follow the Vbat voltage beyond his nominal value Voutnom. By maintaining the voltage Vg no when idle mode, the grid capacity Cg does not fully discharge and the mode switchover the regulated mode is done quickly, with a clear attenuation of the overvoltage phenomenon.

Bien entendu, diverses combinaisons des caractéristiques de chacun des amplificateurs 22a à 22d peuvent être prévues, pour réaliser d'autres variantes de réalisation. Notamment, l'étage de polarisation 30 de l'amplificateur 22d peut être incorporé dans les amplificateurs 22a, 22b. Il est également à la portée de l'homme de l'art d'appliquer les principes et solutions exposés ci-dessus à des structures d'amplificateur connues autres que celle de l'amplificateur 2 choisi ici à titre d'exemple. Par ailleurs, bien que les exemples qui viennent d'être décrits se rapportent à un régulateur ayant un transistor de régulation de type PMOS, il entre dans le cadre de la présente demande et il est à la portée de l'homme de l'art de transposer l'enseignement de la présente invention aux régulateurs ayant un transistor de régulation de type NMOS.Of course, various combinations of characteristics of each of the amplifiers 22a to 22d may be provided for making other variants of production. In particular, the polarization stage 30 of the amplifier 22d can be incorporated into the amplifiers 22a, 22b. It is also within the reach of those skilled in the art of applying the principles and solutions exposed above to amplifier structures known other than that of the amplifier 2 chosen here for exemple. Moreover, although the examples which have just been described relate to a regulator having a PMOS type control transistor, it enters as part of this application and he is at the reach of the skilled person to transpose teaching of the present invention to regulators having a NMOS-type control transistor.

Enfin, bien que le problème résolu par la présente invention ait été décrit en relation avec les téléphones portables, il va de soi qu'un régulateur selon l'invention est susceptible de diverses autres applications, notamment dans le cas où la tension d'alimentation est fournie par une batterie dont on veut préserver l'autonomie.Finally, although the problem solved by this invention has been described in relation to telephones portable, it goes without saying that a regulator the invention is susceptible of various other applications, especially in the case where the power is provided by a battery that we want preserve the autonomy.

Claims (15)

  1. Voltage regulator (20) comprising:
    a MOS transistor of regulation (23) provided with a first conduction terminal (S) receiving a supply voltage (Vbat) and a second conduction terminal (D) linked to the output of the regulator, and
    an amplifier (22, 22a-22d) which output drives the gate of the regulation transistor (23) according to the difference between a reference voltage (Vref) and a feedback voltage (Vfb),
    characterised in that it comprises means (6', 7', 24, 25, 27, 30) of switching the amplifier to a standby mode with low current consumption when the difference (Vd) between the supply voltage (Vbat) and the output voltage (Vout) of the regulator is below a first threshold (Vd1), while maintaining, at the gate of the regulation transistor (23), an electrical potential enabling the regulation transistor to stay in conducting state.
  2. Regulator according to claim 1, comprising a comparator (24) arranged to compare the supply voltage (Vbat) and the output voltage (Vout) of the regulator, and deliver a standby signal (Vlc=1) to the amplifier (22) when the difference (Vd) between the supply voltage and the output voltage of the regulator is below the first threshold (Vd1).
  3. Regulator according to claim 2, characterised in that the comparator (24) has a switch hysteresis and cancels the standby signal of the amplifier (Vlc=0) when the difference (Vd) between the supply voltage and the output voltage of the regulator is higher than a second threshold (Vd2) superior to the first threshold (Vd1).
  4. Regulator according to one of the claims 1 to 3, wherein the amplifier (22a, 22b) comprises a resistor (Rg) connecting the output of the amplifier to the supply voltage (Vbat), characterised in that a switch (25) is arranged in series with the resistor (Rg) and in that the said switch arranged in series with the resistor is open when the amplifier goes into standby, and otherwise closed.
  5. Regulator according to one of the claims 1 to 4, wherein the amplifier (22b) comprises current sources (6', 8') switching to low-current mode when the amplifier goes into standby.
  6. Regulator according to one of the claims 1 to 5, wherein the amplifier comprises a switch (27) driven by a standby signal (Vlc) to connect the gate of the regulation transistor (23) at an electrical potential switching the transistor to a conductive state when the amplifier goes into standby.
  7. Regulator according to one of the claims 1 to 6, wherein the amplifier (22d) comprises a stage (30) to bias the gate of the regulation transistor (23), arranged to apply, to the gate of the regulation transistor, when the amplifier is in standby, a voltage (Vg) which is determined so that the gate-source voltage (Vgs) of the regulation transistor is close to the threshold voltage (Vtp) of the regulation transistor.
  8. Regulator according to one of the claims 6 and 7, wherein, in standby mode, the power supply of the amplifier (22c, 22d) is suppressed by a switch (26).
  9. Mobile telephone comprising a battery and radio circuits powered by means of a regulator (20) according to the one of the claims 1 to 8.
  10. Method for the management of the energy available in a battery (21) powering a load (Z) by means of a voltage regulator (20), the regulator comprising a regulation MOS transistor (23) provided with a first conduction terminal (S) receiving a supply voltage (Vbat) and a second conduction terminal (D) linked to the output of the regulator, and an amplifier (22) which output drives the gate of the regulation transistor (23) according to the difference between the reference voltage (Vref) and a feedback voltage (Vfb), method characterised in that it comprises a step of monitoring the difference (Vd) between the supply voltage (Vbat) and the output voltage (Vout) of the regulator, and a step of switching the amplifier (22) to a standby mode with low current consumption when the difference (Vd) between the supply voltage (Vbat) and the output voltage (Vout) of the regulator is below a first threshold (Vd1), while maintaining the gate of the regulation transistor (23) at a potential enabling the regulation transistor to stay in conductive state.
  11. Method according to claim 10, characterised in that the amplifier (20) is reactivated when the difference (Vd) between the supply voltage and the output voltage of the regulator is higher than a second threshold (Vd2) superior to the first threshold (Vd1).
  12. Method according to one of the claims 10 and 11, wherein the consumption of the amplifier (22, 22a, 22b) in standby mode is reduced by disconnecting (25, Vlc=1) the output node of the amplifier from the supply voltage (Vbat).
  13. Method according to one of the claims 10 to 12, wherein the consumption of the amplifier (22, 22b) in standby mode is reduced by diminishing the current delivered by current sources (6', 8') internal to the amplifier.
  14. Method according to one of the claims 10 and 11, wherein the supply voltage is not applied to the amplifier in standby mode.
  15. Method according to one of the claims 10 to 14, wherein, when the amplifier goes into standby, the gate of the regulation transistor (23) receives a voltage (Vg) which is determined so that the gate-source voltage (Vgs) of the regulation transistor is close to the threshold voltage (Vtp) of the regulation transistor.
EP01108243A 2000-04-12 2001-03-31 Voltage regulator with low power consumption Expired - Lifetime EP1148404B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0004675 2000-04-12
FR0004675A FR2807846A1 (en) 2000-04-12 2000-04-12 LOW POWER CONSUMPTION VOLTAGE REGULATOR

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EP1148404A1 EP1148404A1 (en) 2001-10-24
EP1148404B1 true EP1148404B1 (en) 2005-11-02

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FR2807846A1 (en) 2001-10-19
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US20010030530A1 (en) 2001-10-18
US6501253B2 (en) 2002-12-31

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