EP1148404A1 - Voltage regulator with low power consumption - Google Patents

Voltage regulator with low power consumption Download PDF

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Publication number
EP1148404A1
EP1148404A1 EP01108243A EP01108243A EP1148404A1 EP 1148404 A1 EP1148404 A1 EP 1148404A1 EP 01108243 A EP01108243 A EP 01108243A EP 01108243 A EP01108243 A EP 01108243A EP 1148404 A1 EP1148404 A1 EP 1148404A1
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EP
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Prior art keywords
voltage
amplifier
regulator
transistor
regulation
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EP01108243A
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German (de)
French (fr)
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EP1148404B1 (en
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Nicolas Marty
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STMicroelectronics SA
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STMicroelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to regulators of LDO type linear voltages (Low Drop Out Regulators), that is to say at low series voltage drop.
  • Such regulators are the subject of various applications, especially in the field of telephones movable to deliver regulated voltage to circuits radio transmission-reception from a voltage power supplied by a battery.
  • Figure 1 shows a classic linear regulator 10 whose output delivers a regulated voltage Vout at a load Z.
  • the load Z represents for example various radio circuits present in a mobile phone.
  • Regulator 10 is powered electrically by a voltage Vbat delivered by a battery 1 and includes a differential amplifier 2 whose output drives the gate G of a transistor PMOS type regulation 3.
  • Transistor 3 is typically a low resistance transistor series to the on state (drain-source resistance RdsON) and receives on its source S the voltage Vbat. Its drain D, connected to the output of regulator 10, is connected to the anode of a filtering and stabilizing capacitor Cst voltage Vout, arranged in parallel with the load Z.
  • Amplifier 2 receives on its negative input a reference voltage Vref and on its positive input a feedback voltage Vfb (feedback). Voltage Vfb is a fraction of the voltage Vout brought back on the input of amplifier 2 via a divider bridge comprising two resistors R1, R2.
  • FIG. 2 represents an embodiment classic amplifier 2.
  • This includes a differential stage represented in the form of a block 5, receiving as input the voltages Vref and Vfb and polarized by a current generator 6.
  • the output of the floor differential 5 drives the gate of a transistor 7 of the type NMOS connected between the amplifier output node 2 and the mass.
  • Transistor 7 is polarized on its drain D by a current generator 8.
  • the output node of the amplifier is connected to the supply voltage Vbat by a gate resistance Rg, which determines the amplifier gain and the maximum current it can output. So depending on the signal value delivered by the differential stage 5, the transistor 7 draws amplifier output to ground or the resistance Rg pulls the output upwards, i.e. the voltage Vbat.
  • the control amplifier In an application such as food mobile phone, it is important that the control amplifier has a consumption as low as possible in order to preserve battery life.
  • the resistance of grid Rg is chosen to be of high value, for example 100K ⁇ , to limit the current flowing in the stage Release.
  • the currents delivered by the generators 6, 8 are adequately calibrated.
  • the choice of resistance Rg and bias currents is the result of a compromise between the need to effectively pilot the transistor 3, which generally has a capacitance high grid parasite, and looking for a low consumption.
  • this consumption typically of the order from 50 to 200 microamps, which is in itself acceptable when the battery is fully charged and the regulator operates in a steady state
  • the present invention is is based on the premise that this consumption must by against being considered too high when the voltage of Vbat battery becomes weak and below the value nominal Voutnom of the output voltage. Such a fall of the voltage Vbat below the nominal voltage Voutnom can be temporary and due to a strong current consumption, or be due to the fact that the battery is discharged.
  • the amplifier unnecessarily consumes current when the regulator operates in follower mode, since the regulating transistor is continuously in the on state and that a voltage regulation of Vout exit is no longer possible.
  • the idea of present invention is to rock the amplifier regulation in a low standby mode consumption while maintaining in the state passing the regulating transistor.
  • the present invention provides a voltage regulator comprising a transistor Regulation MOS and an amplifier whose output controls the gate of the regulation transistor as a function the difference between a reference voltage and a voltage feedback, the regulator comprising means to toggle the amplifier in a mode of ensures low current consumption when the deviation between supply voltage and output voltage of the regulator is less than a first threshold, while now on the gate of the regulating transistor a electrical potential to maintain the regulation transistor in the on state.
  • the regulator includes a comparator arranged to compare the voltage supply and the regulator output voltage, and provide a standby signal to the amplifier when the difference between the supply voltage and the regulator output voltage is less than first threshold.
  • the comparator has a switching hysteresis and cancels the amplifier standby signal when the difference between the supply voltage and the regulator output is above a second threshold greater than the first threshold.
  • the amplifier includes a resistor connecting the output of the amplifier at the supply voltage, a switch is arranged in series with the resistor, the switch in series with the resistor is open when the amplifier is put on standby and closed in the opposite case.
  • the amplifier includes current sources toggling in low mode current when the amplifier is put on standby.
  • the amplifier includes a switch controlled by an activation signal standby to connect the gate of the transistor regulation at an electrical potential making the transistor on when the amplifier is turned on standby.
  • the amplifier includes a stage of polarization of the grid of the regulating transistor, arranged to apply to the gate of the regulation transistor, when the amplifier is put on standby, a voltage which is determined so that the gate-source voltage of the regulating transistor be close to the voltage of threshold of the regulation transistor.
  • the power supply amplifier power is removed in mode standby by a switch.
  • the present invention also relates to a mobile phone including battery and circuits radio powered by a regulator according to the invention.
  • the present invention also provides a method for managing the energy available in a battery feeding a load via a regulator voltage, the regulator comprising a MOS transistor regulation and an amplifier whose output controls the gate of the regulation transistor as a function of the difference between a reference voltage and a feedback voltage, process comprising a step consisting of monitor the difference between the supply voltage and the regulator output voltage, and a step consisting to switch the amplifier to a standby mode at low current consumption when the gap between the supply voltage and the output voltage of the regulator is less than a first threshold, while now the gate of the regulating transistor at a potential to maintain the transistor regulation in the on state.
  • the consumption of the amplifier can be reduced in standby mode by disconnecting the output node of the supply voltage amplifier, reducing the current delivered by current sources internal to the amplifier, or removing the application of the supply voltage.
  • FIG. 4 represents a regulator 20 according to the invention, supplied here by a voltage Vbat supplied by a battery 21.
  • the regulator 20 includes as that of FIG. 1 a differential amplifier 22 whose output controls the gate of a transistor PMOS type regulation 23.
  • the drain D of transistor 23 is connected to the output of regulator 20 and is connected to a stabilization capacity Cst in parallel with a load Z, these various elements being arranged as described in the preamble.
  • the output voltage Vout is brought back to the positive input of amplifier 2 by via a divider bridge comprising two resistors R1, R2.
  • the resistance R1 can be zero in the case of a direct feedback of the voltage of output Vout on the input of amplifier 22, the resistance R2 in this case being mathematically infinite.
  • the reference voltage Vref applied to the input negative of amplifier 2 is for example a voltage so-called band-gap with good stability in temperature function, generated by means of diodes PN junction and current mirrors.
  • the voltage Vref is thus independent of the voltage Vbat, on the condition to be less than the lowest voltage value Vbat.
  • Amplifier 2 maintains the feedback voltage Vfb equal to the reference voltage Vref and the nominal output voltage Voutnom is equal to [(R1 + R2) Vref / R2].
  • the amplifier 22 has a "normal" operating mode and a “standby” mode and switches from one to the other according to the value of a signal Vlc applied to an LCIN input provided for this purpose.
  • Setting standby amplifier 22 consists, according to the invention, in placing the amplifier in a state of low power consumption while now the gate voltage Vg at a potential maintaining the regulation transistor 23 in the passing state.
  • Various examples of realization of the amplifier 22 will be described later. We will consider by convention, in what follows, that the amplifier switches to standby mode when the signal Vlc goes to 1.
  • the signal Vlc is delivered by a comparator 24 receiving on its positive input the output voltage Vout and on its negative input the supply voltage Vbat, the comparator 24 being supplied by the voltage Vbat.
  • Comparator 24 is a threshold comparator Vd1 and here sets its output to 1 (signal Vlc) when the voltage differential Vd seen on its inputs, equal to the difference between the voltage Vbat and the voltage Vout, becomes below the threshold Vd1.
  • comparator 24 has also, preferably, a switching hysteresis and resets its output to 0 when the differential voltage Vd goes up and becomes higher than a higher threshold Vd2 to Vd1.
  • the thresholds Vd1, Vd2 are for example equal to 100 mV and 120mV, respectively.
  • amplifier 22 switches to standby mode while holding the regulating transistor 23 in the on state, when the regulator 20 operates in follower mode due to voltage drop Vbat power supply below the nominal value Voutnom of the output voltage.
  • FIGs 5A, 5B, 5C illustrate the operation of regulator 20 in follower mode and represent the voltages Vbat and Vout respectively, the voltage differential Vd and the signal Vlc.
  • a decrease in the voltage Vbat from of its nominal value Vbatnom has no consequence on the regulated voltage Vout, which remains equal to Voutnom, as long as the voltage Vbat remains greater than Voutnom.
  • the differential voltage Vd decreases in proportion to the voltage Vbat until an instant t2 where the voltage Vbat becomes substantially equal to Voutnom and causes the voltage Vout in its fall, the regulator then being unbalanced and operating in follower mode.
  • the differential voltage Vd reaches a minimum value Vdmin which corresponds to the fall of voltage across the regulation transistor 23.
  • This voltage drop Vdmin is in principle very small, by example 50 mV, because the regulating transistor of a LDO type regulator usually has a VdsON drain-source resistance in the very on state low. From time t2, the voltage Vout begins to decrease and follows the voltage Vbat, at the offset near the voltage Vdmin.
  • the transition to follower mode is detected by comparator 24 at a time t1 preceding t2 but very close to t2, when the voltage differential Vd reaches the threshold Vd1 mentioned more high, chosen very close to the minimum Vdmin. So at at time t1, the signal Vlc goes to 1 (fig. 5C) and amplifier 2 is put on standby.
  • the logical "1" of signal Vlc here is the voltage Vbat, which supplies the comparator 24.
  • the voltage Vbat then goes back up to its nominal value, for example after recharging the battery 21 or regenerating natural of it when the current consumed decreases.
  • the voltage Vbat exceeds the Voutnom value.
  • the voltage differential Vd exceeds the threshold Vd2 and the amplifier 22 switches to its normal operating mode, the voltage Vout returning to its nominal value Voutnom.
  • the amplifier 22a illustrated in FIG. 6 is of a structure similar to that of amplifier 2.
  • the differential stage 5 polarized by the current generator 6, the output of which controls the NMOS transistor 7 polarized on its drain by the current generator 8, as well as the resistance Rg connecting the output node of amplifier 22a to the Vbat voltage.
  • a switch 25, here a PMOS transistor is arranged in series with the resistance Rg.
  • the transistor 25 receives on its gate the signal Vlc and is thus permanently in the on state when the regulator is operating in steady state, the signal Vlc being at 0 as indicated above.
  • the amplifier 22b shown in FIG. 7 is almost identical to amplifier 22a.
  • current generators 6, 8 have been replaced by current generators 6 ', 8' which are controlled by the signal Vlc and which deliver different currents according to the value of the signal Vlc.
  • the respective currents I1 ', I2' delivered when the signal Vlc is at 1 are for example equal to half of the currents I1, I2 delivered when the signal Vlc is at 0.
  • the currents I1 ', I2' are by example of 10 microamps and the currents I1, I2 of 20 microamps.
  • the amplifier 22c of FIG. 8 is produced at starting from the amplifier 2 of FIG. 2, which we have not changed in its internal structure.
  • the Vbat voltage is applied to the power input of amplifier 2 via a transistor PMOS 26 controlled by the Vlc signal.
  • a transistor NMOS 27 driven by the Vlc signal is added between the amplifier 2 output and ground. So when signal Vlc is at 0 (balanced regulator), the transistor 26 is on and transistor 27 is blocked. Amplifier 2 works as if these two elements did not exist. When the signal Vlc is at 1 (regulator in follower mode), transistor 26 is blocked and transistor 27 is on. Amplifier 2 does not no longer receives the supply voltage Vbat and is completely off.
  • the transistor 27 draws the amplifier output at 0 (voltage Vg) to maintain the regulating transistor 23 in the on state.
  • This embodiment 22c therefore differs from the preceding 22a, 22b by the fact that in standby mode the voltage of gate Vg is not grounded by the transistor NMOS 2 of the output stage of amplifier 2, which is out of service, but by the additional transistor 27 meant for that purpose.
  • the amplifier 22d represented in FIG. 9 comprises also amplifier 2 and transistor 26 ensuring switching off amplifier 2 when the signal Vlc is at 1.
  • the pull-down transistor 27 (pull down) at the output of amplifier 22c is replaced by a 30 more advanced bias stage which maintains the output of amplifier 2 at a voltage Vg greater than ground when it is off.
  • This voltage Vg is chosen so that the voltage source gate Vgs of the regulation transistor 23 or maintained in the vicinity of the threshold voltage Vtp of the transistor 23.
  • the polarization step 30 comprises for example a first PMOS transistor 31 receiving the voltage Vbat on its source, connected by its drain to the source of a second PMOS transistor 32 whose drain is connected to the amplifier output node 22d.
  • Transistors 31, 32 are arranged in diodes, each having its grid connected to its drain.
  • the bias stage 30 includes a resistor 33 of high value in series with an NMOS transistor 34 driven by the Vlc signal.
  • the signal Vlc is at 0 and the transistor 34 is also blocked.
  • Amplifier 2 operates as if bias stage 30 did not exist not.
  • the voltage Vg tends to 0
  • signal Vlc goes to 1 and amplifier 2 is turned off.
  • the two diode transistors 31, 32 become passers-by and each impose a voltage Vtp at their terminals, so the gate voltage Vg is in this case equal to [Vbat - (2Vtp)].
  • the voltage Vgs of regulation transistor 23 is thus equal to 2Vtp in absolute value and is close to Vtp (at the value Vtp close, of the order of 0.7 V). Other methods are good heard possible to maintain the voltage Vg still closer to the threshold voltage Vtp.
  • the advantage of this embodiment is that it does not fully discharge the stray capacitance of grid Cg of the regulation transistor 23, shown in lines dotted, which is usually of high value (100-200 picofarads) with a low regulation transistor resistance RdsON series. Indeed, when the voltage Vg is brought to ground, the Cg capacity is fully discharged during standby mode. If the voltage Vbat goes up suddenly, a delay in closing the transistor 23 (transistor blocking) occurs during return to regulated mode due to the charging time of the capacity Cg. Such a delay in closing reveals an overvoltage at the regulator output, because the voltage Vout continues to follow Vbat voltage beyond its nominal value Voutnom. Maintaining the voltage Vg no zero during standby mode, the grid capacity Cg does not not fully discharging and switching the mode Standby in regulated mode is done quickly, with a clear attenuation of the overvoltage phenomenon.
  • each of the amplifiers 22a to 22d can be provided, to make other variants of production.
  • the bias stage 30 of the 22d amplifier can be incorporated in the amplifiers 22a, 22b. It is also within reach of those skilled in the art of applying the principles and solutions exposed above to amplifier structures known other than that of amplifier 2 chosen here for example.
  • the examples which have just been described relate to a regulator having a PMOS type regulation transistor, it enters as part of this application and it is at the scope of the skilled person to transpose the teaching of the present invention to regulators having a NMOS type regulation transistor.

Abstract

L'invention concerne un régulateur de tension (20) comprenant un transistor MOS de régulation (23) et un amplificateur (22) dont la sortie pilote la grille du transistor de régulation en fonction de l'écart entre une tension de référence (Vref) et une tension de contre-réaction (Vfb). Selon l'invention, le régulateur comprend des moyens (24) pour faire basculer l'amplificateur dans un mode de veille à faible consommation de courant lorsque l'écart (Vd) entre la tension d'alimentation (Vbat) et la tension de sortie (Vout) du régulateur est inférieur à un premier seuil, tout en maintenant sur la grille du transistor de régulation (23) un potentiel électrique permettant de maintenir le transistor de régulation dans l'état passant. Application notamment à la gestion d'alimentation dans les téléphones portables. <IMAGE>The invention relates to a voltage regulator (20) comprising a regulating MOS transistor (23) and an amplifier (22), the output of which controls the gate of the regulating transistor as a function of the difference between a reference voltage (Vref). and a feedback voltage (Vfb). According to the invention, the regulator comprises means (24) for switching the amplifier into a standby mode with low current consumption when the difference (Vd) between the supply voltage (Vbat) and the output voltage (Vout) of the regulator is less than a first threshold, while maintaining on the gate of the regulating transistor (23) an electrical potential making it possible to maintain the regulating transistor. Application in particular to power management in mobile phones. <IMAGE>

Description

La présente invention concerne les régulateurs de tension linéaires du type LDO (Low Drop Out Regulators), c'est-à-dire à faible chute de tension série.The present invention relates to regulators of LDO type linear voltages (Low Drop Out Regulators), that is to say at low series voltage drop.

De tels régulateurs font l'objet de diverses applications, notamment dans le domaine des téléphones mobiles pour délivrer une tension régulée à des circuits d'émission-réception radio à partir d'une tension d'alimentation fournie par une batterie.Such regulators are the subject of various applications, especially in the field of telephones movable to deliver regulated voltage to circuits radio transmission-reception from a voltage power supplied by a battery.

A titre d'exemple, la figure 1 représente un régulateur linéaire classique 10 dont la sortie délivre une tension régulée Vout à une charge Z. La charge Z représente par exemple divers circuits radio présents dans un téléphone mobile. Le régulateur 10 est alimenté électriquement par une tension Vbat délivrée par une batterie 1 et comprend un amplificateur différentiel 2 dont la sortie pilote la grille G d'un transistor de régulation 3 du type PMOS. Le transistor 3 est généralement un transistor à faible résistance série à l'état passant (résistance drain-source RdsON) et reçoit sur sa source S la tension Vbat. Son drain D, relié à la sortie du régulateur 10, est connecté à l'anode d'un condensateur Cst de filtrage et de stabilisation de la tension Vout, agencé en parallèle avec la charge Z. L'amplificateur 2 reçoit sur son entrée négative une tension de référence Vref et sur son entrée positive une tension de contre-réaction Vfb (feed-back). La tension Vfb est une fraction de la tension Vout ramenée sur l'entrée de l'amplificateur 2 par l'intermédiaire d'un pont diviseur comprenant deux résistances R1, R2.For example, Figure 1 shows a classic linear regulator 10 whose output delivers a regulated voltage Vout at a load Z. The load Z represents for example various radio circuits present in a mobile phone. Regulator 10 is powered electrically by a voltage Vbat delivered by a battery 1 and includes a differential amplifier 2 whose output drives the gate G of a transistor PMOS type regulation 3. Transistor 3 is typically a low resistance transistor series to the on state (drain-source resistance RdsON) and receives on its source S the voltage Vbat. Its drain D, connected to the output of regulator 10, is connected to the anode of a filtering and stabilizing capacitor Cst voltage Vout, arranged in parallel with the load Z. Amplifier 2 receives on its negative input a reference voltage Vref and on its positive input a feedback voltage Vfb (feedback). Voltage Vfb is a fraction of the voltage Vout brought back on the input of amplifier 2 via a divider bridge comprising two resistors R1, R2.

Le fonctionnement d'un tel régulateur, bien connu de l'homme de l'art, consiste dans une modulation de la tension de grille Vg du transistor 3 par l'amplificateur en fonction de l'écart entre la tension Vfb et la tension de référence Vref, que l'amplificateur maintient au voisinage de 0. Lorsque la tension Vg est inférieure à la valeur [Vbat - Vtp], le transistor 3 est passant car sa tension grille-source Vgs est supérieure à sa tension de seuil Vtp. Lorsque la tension Vg est supérieure à [Vbat - Vtp], le transistor est bloqué. En régime stabilisé, la tension Vout est régulée au voisinage de sa valeur nominale Voutnom, égale à [(R1+R2)Vref/R2].The operation of such a well-known regulator skilled in the art, consists in modulating the gate voltage Vg of transistor 3 by the amplifier as a function of the difference between the voltage Vfb and the voltage Vref, which the amplifier maintains at neighborhood of 0. When the voltage Vg is less than the value [Vbat - Vtp], transistor 3 is on because its gate-source voltage Vgs is greater than its voltage of threshold Vtp. When the voltage Vg is greater than [Vbat - Vtp], the transistor is blocked. In regime stabilized, the voltage Vout is regulated in the vicinity of its nominal value Voutnom, equal to [(R1 + R2) Vref / R2].

La figure 2 représente un mode de réalisation classique de l'amplificateur 2. Celui-ci comprend un étage différentiel représenté sous la forme d'un bloc 5, recevant en entrée les tensions Vref et Vfb et polarisé par un générateur de courant 6. La sortie de l'étage différentiel 5 pilote la grille d'un transistor 7 de type NMOS connecté entre le noeud de sortie de l'amplificateur 2 et la masse. Le transistor 7 est polarisé sur son drain D par un générateur de courant 8. Le noeud de sortie de l'amplificateur est relié à la tension d'alimentation Vbat par une résistance de grille Rg, qui détermine le gain de l'amplificateur et le courant maximal qu'il peut délivrer en sortie. Ainsi, selon la valeur du signal délivré par l'étage différentiel 5, le transistor 7 tire la sortie de l'amplificateur vers la masse ou la résistance Rg tire la sortie vers le haut, c'est-à-dire la tension Vbat.FIG. 2 represents an embodiment classic amplifier 2. This includes a differential stage represented in the form of a block 5, receiving as input the voltages Vref and Vfb and polarized by a current generator 6. The output of the floor differential 5 drives the gate of a transistor 7 of the type NMOS connected between the amplifier output node 2 and the mass. Transistor 7 is polarized on its drain D by a current generator 8. The output node of the amplifier is connected to the supply voltage Vbat by a gate resistance Rg, which determines the amplifier gain and the maximum current it can output. So depending on the signal value delivered by the differential stage 5, the transistor 7 draws amplifier output to ground or the resistance Rg pulls the output upwards, i.e. the voltage Vbat.

Dans une application telle que l'alimentation électrique d'un téléphone mobile, il est important que l'amplificateur de régulation présente une consommation électrique aussi faible que possible afin de préserver l'autonomie de la batterie. A cet effet, la résistance de grille Rg est choisie de forte valeur, par exemple 100KΩ, afin de limiter le courant circulant dans l'étage de sortie. Egalement, les courants délivrés par les générateurs 6, 8 sont calibrés de façon adéquate. De façon générale, le choix de la résistance Rg et des courants de polarisation est le résultat d'un compromis entre la nécessité de piloter efficacement le transistor 3, qui présente généralement une capacité parasite de grille élevée, et la recherche d'une faible consommation.In an application such as food mobile phone, it is important that the control amplifier has a consumption as low as possible in order to preserve battery life. To this end, the resistance of grid Rg is chosen to be of high value, for example 100KΩ, to limit the current flowing in the stage Release. Also, the currents delivered by the generators 6, 8 are adequately calibrated. Of in general, the choice of resistance Rg and bias currents is the result of a compromise between the need to effectively pilot the transistor 3, which generally has a capacitance high grid parasite, and looking for a low consumption.

Bien que cette consommation, typiquement de l'ordre de 50 à 200 microampères, soit en soi acceptable lorsque la batterie est bien chargée et que le régulateur fonctionne en régime stabilisé, la présente invention se fonde sur le postulat que cette consommation doit par contre être considérée trop élevée lorsque la tension de batterie Vbat devient faible et inférieure à la valeur nominale Voutnom de la tension de sortie. Une telle chute de la tension Vbat en dessous de la tension nominale Voutnom peut être temporaire et due à une forte consommation de courant, ou être due au fait que la batterie est déchargée.Although this consumption, typically of the order from 50 to 200 microamps, which is in itself acceptable when the battery is fully charged and the regulator operates in a steady state, the present invention is is based on the premise that this consumption must by against being considered too high when the voltage of Vbat battery becomes weak and below the value nominal Voutnom of the output voltage. Such a fall of the voltage Vbat below the nominal voltage Voutnom can be temporary and due to a strong current consumption, or be due to the fact that the battery is discharged.

En effet, selon des constatations et conclusions faisant partie intégrante de la présente invention, illustrées sur les figures 3A, 3B, et 3C, le passage de la tension Vbat en dessous de la valeur Voutnom à un instant tA (fig. 3A) fait que la tension de contre-réaction Vfb devient inférieure à Vref à l'entrée de l'amplificateur 2. Ce dernier est déséquilibré et fait baisser jusqu'à la masse la tension de grille Vg pour rattraper le déséquilibre (fig. 3B). Le transistor de régulation 3 est continuellement passant, la tension Vout devient sensiblement égale à la tension Vbat (fig. 3C) et le régulateur 10 fonctionne en mode "suiveur". Le noeud de sortie de l'amplificateur 2 étant à la masse, on voit en figure 2 que la consommation dans la résistance de grille Rg est maximale.Indeed, according to findings and conclusions forming an integral part of the present invention, illustrated in FIGS. 3A, 3B, and 3C, the passage of the voltage Vbat below the value Voutnom at one instant tA (fig. 3A) causes the feedback voltage Vfb becomes less than Vref at the entry of amplifier 2. The latter is unbalanced and makes lower the gate voltage Vg to ground compensate for the imbalance (fig. 3B). The transistor regulation 3 is continuously on, the voltage Vout becomes substantially equal to the voltage Vbat (fig. 3C) and regulator 10 operates in "follower" mode. The knot of amplifier 2 output being grounded, we see in Figure 2 that consumption in the grid resistor Rg is maximum.

Ainsi, l'amplificateur consomme inutilement du courant lorsque le régulateur fonctionne en mode suiveur, puisque le transistor de régulation est continuellement dans l'état passant et qu'une régulation de la tension de sortie Vout n'est plus possible. Thus, the amplifier unnecessarily consumes current when the regulator operates in follower mode, since the regulating transistor is continuously in the on state and that a voltage regulation of Vout exit is no longer possible.

Pour pallier cet inconvénient, l'idée de la présente invention est de faire basculer l'amplificateur de régulation dans un mode de veille à faible consommation tout en maintenant dans l'état passant le transistor de régulation.To overcome this drawback, the idea of present invention is to rock the amplifier regulation in a low standby mode consumption while maintaining in the state passing the regulating transistor.

Plus particulièrement, la présente invention prévoit un régulateur de tension comprenant un transistor MOS de régulation et un amplificateur dont la sortie pilote la grille du transistor de régulation en fonction de l'écart entre une tension de référence et une tension de contre-réaction, le régulateur comprenant des moyens pour faire basculer l'amplificateur dans un mode de veille à faible consommation de courant lorsque l'écart entre la tension d'alimentation et la tension de sortie du régulateur est inférieur à un premier seuil, tout en maintenant sur la grille du transistor de régulation un potentiel électrique permettant de maintenir le transistor de régulation dans l'état passant.More particularly, the present invention provides a voltage regulator comprising a transistor Regulation MOS and an amplifier whose output controls the gate of the regulation transistor as a function the difference between a reference voltage and a voltage feedback, the regulator comprising means to toggle the amplifier in a mode of ensures low current consumption when the deviation between supply voltage and output voltage of the regulator is less than a first threshold, while now on the gate of the regulating transistor a electrical potential to maintain the regulation transistor in the on state.

Selon un mode de réalisation, le régulateur comprend un comparateur agencé pour comparer la tension d'alimentation et la tension de sortie du régulateur, et délivrer à l'amplificateur un signal de mise en veille lorsque l'écart entre la tension d'alimentation et la tension de sortie du régulateur est inférieur au premier seuil.According to one embodiment, the regulator includes a comparator arranged to compare the voltage supply and the regulator output voltage, and provide a standby signal to the amplifier when the difference between the supply voltage and the regulator output voltage is less than first threshold.

Selon un mode de réalisation, le comparateur présente une hystérésis de commutation et annule le signal de mise en veille de l'amplificateur lorsque l'écart entre la tension d'alimentation et la tension de sortie du régulateur est supérieur à un second seuil supérieur au premier seuil.According to one embodiment, the comparator has a switching hysteresis and cancels the amplifier standby signal when the difference between the supply voltage and the regulator output is above a second threshold greater than the first threshold.

Selon un mode de réalisation, l'amplificateur comprend une résistance reliant la sortie de l'amplificateur à la tension d'alimentation, un interrupteur est agencé en série avec la résistance, l'interrupteur en série avec la résistance est ouvert lorsque l'amplificateur est mis en veille et fermé dans le cas contraire.According to one embodiment, the amplifier includes a resistor connecting the output of the amplifier at the supply voltage, a switch is arranged in series with the resistor, the switch in series with the resistor is open when the amplifier is put on standby and closed in the opposite case.

Selon un mode de réalisation, l'amplificateur comprend des sources de courant basculant en mode faible courant lorsque l'amplificateur est mis en veille.According to one embodiment, the amplifier includes current sources toggling in low mode current when the amplifier is put on standby.

Selon un mode de réalisation, l'amplificateur comprend un interrupteur piloté par un signal de mise en veille pour connecter la grille du transistor de régulation à un potentiel électrique rendant le transistor passant lorsque l'amplificateur est mis en veille.According to one embodiment, the amplifier includes a switch controlled by an activation signal standby to connect the gate of the transistor regulation at an electrical potential making the transistor on when the amplifier is turned on standby.

Selon un mode de réalisation, l'amplificateur comprend un étage de polarisation de la grille du transistor de régulation, agencé pour appliquer sur la grille du transistor de régulation, lorsque l'amplificateur est mis en veille, une tension qui est déterminée de manière que la tension grille-source du transistor de régulation soit proche de la tension de seuil du transistor de régulation.According to one embodiment, the amplifier includes a stage of polarization of the grid of the regulating transistor, arranged to apply to the gate of the regulation transistor, when the amplifier is put on standby, a voltage which is determined so that the gate-source voltage of the regulating transistor be close to the voltage of threshold of the regulation transistor.

Selon un mode de réalisation, l'alimentation électrique de l'amplificateur est supprimée en mode veille par un interrupteur.According to one embodiment, the power supply amplifier power is removed in mode standby by a switch.

La présente invention concerne également un téléphone mobile comprenant une batterie et des circuits radio alimentés par l'intermédiaire d'un régulateur selon l'invention.The present invention also relates to a mobile phone including battery and circuits radio powered by a regulator according to the invention.

La présente invention prévoit également un procédé de gestion de l'énergie disponible dans une batterie alimentant une charge par l'intermédiaire d'un régulateur de tension, le régulateur comprenant un transistor MOS de régulation et un amplificateur dont la sortie pilote la grille du transistor de régulation en fonction de l'écart entre une tension de référence et une tension de contre-réaction, procédé comprenant une étape consistant à surveiller l'écart entre la tension d'alimentation et la tension de sortie du régulateur, et une étape consistant à faire basculer l'amplificateur dans un mode veille à faible consommation de courant lorsque l'écart entre la tension d'alimentation et la tension de sortie du régulateur est inférieur à un premier seuil, tout en maintenant la grille du transistor de régulation à un potentiel permettant de maintenir le transistor de régulation dans l'état passant.The present invention also provides a method for managing the energy available in a battery feeding a load via a regulator voltage, the regulator comprising a MOS transistor regulation and an amplifier whose output controls the gate of the regulation transistor as a function of the difference between a reference voltage and a feedback voltage, process comprising a step consisting of monitor the difference between the supply voltage and the regulator output voltage, and a step consisting to switch the amplifier to a standby mode at low current consumption when the gap between the supply voltage and the output voltage of the regulator is less than a first threshold, while now the gate of the regulating transistor at a potential to maintain the transistor regulation in the on state.

Selon un mode de réalisation, on réactive l'amplificateur lorsque l'écart entre la tension d'alimentation et la tension de sortie du régulateur est supérieur à un second seuil supérieur au premier seuil.According to one embodiment, we reactivate the amplifier when the difference between the voltage power supply and the output voltage of the regulator is greater than a second threshold greater than the first threshold.

La consommation de l'amplificateur peut être réduite en mode veille en déconnectant le noeud de sortie de l'amplificateur de la tension d'alimentation, en diminuant le courant délivré par des sources de courant internes à l'amplificateur, ou en supprimant l'application de la tension d'alimentation.The consumption of the amplifier can be reduced in standby mode by disconnecting the output node of the supply voltage amplifier, reducing the current delivered by current sources internal to the amplifier, or removing the application of the supply voltage.

Lorsque l'amplificateur est mis en veille, il est avantageux d'appliquer sur la grille du transistor de régulation une tension de grille qui est déterminée de manière que la tension grille-source du transistor de régulation soit proche de sa tension de seuil.When the amplifier is put on standby, it is advantageous to apply on the gate of the transistor regulates a gate voltage which is determined by so that the gate-source voltage of the transistor regulation is close to its threshold voltage.

Ces objets, caractéristiques et avantages ainsi que d'autres de la présente invention seront exposés plus en détail dans la description suivante d'un exemple de réalisation d'un régulateur selon l'invention, faite à titre non limitatif en relation avec les figures jointes, parmi lesquelles :

  • la figure 1 précédemment décrite est le schéma électrique d'un régulateur de tension classique,
  • la figure 2 précédemment décrite est le schéma électrique d'un amplificateur présent dans le régulateur de la figure 1,
  • les figures 3A à 3C représentent des signaux électriques et illustrent le fonctionnement du régulateur de tension lorsque la tension d'alimentation chute en dessous de la valeur nominale de la tension de sortie,
  • la figure 4 est le schéma électrique d'un régulateur de tension selon l'invention,
  • les figures 5A à 5C représentent des signaux électriques et illustrent le fonctionnement du régulateur selon l'invention en mode suiveur, et
  • les figures 6 à 9 sont des schémas électriques de quatre variantes de réalisation d'un amplificateur selon l'invention présent dans le régulateur de la figure 4.
These objects, characteristics and advantages as well as others of the present invention will be explained in more detail in the following description of an exemplary embodiment of a regulator according to the invention, given without limitation in relation to the attached figures. , among :
  • FIG. 1 previously described is the electrical diagram of a conventional voltage regulator,
  • FIG. 2 previously described is the electrical diagram of an amplifier present in the regulator of FIG. 1,
  • FIGS. 3A to 3C represent electrical signals and illustrate the operation of the voltage regulator when the supply voltage drops below the nominal value of the output voltage,
  • FIG. 4 is the electrical diagram of a voltage regulator according to the invention,
  • FIGS. 5A to 5C represent electrical signals and illustrate the operation of the regulator according to the invention in follower mode, and
  • FIGS. 6 to 9 are electrical diagrams of four alternative embodiments of an amplifier according to the invention present in the regulator of FIG. 4.

La figure 4 représente un régulateur 20 selon l'invention, alimenté ici par une tension Vbat fournie par une batterie 21. Le régulateur 20 comprend comme celui de la figure 1 un amplificateur différentiel 22 dont la sortie commande la grille d'un transistor de régulation 23 de type PMOS. Le drain D du transistor 23 est relié à la sortie du régulateur 20 et est connecté à une capacité de stabilisation Cst en parallèle avec une charge Z, ces divers éléments étant agencés comme décrit au préambule. La tension de sortie Vout est ramenée sur l'entrée positive de l'amplificateur 2 par l'intermédiaire d'un pont diviseur comprenant deux résistances R1, R2. La résistance R1 peut être nulle dans le cas d'une contre-réaction directe de la tension de sortie Vout sur l'entrée de l'amplificateur 22, la résistance R2 étant dans ce cas mathématiquement infinie. La tension de référence Vref appliquée sur l'entrée négative de l'amplificateur 2 est par exemple une tension dite de band-gap présentant une bonne stabilité en fonction de la température, générée au moyen de diodes à jonction PN et de miroirs de courant. La tension Vref est ainsi indépendante de la tension Vbat, à la condition d'être inférieure à la plus basse valeur de la tension Vbat.FIG. 4 represents a regulator 20 according to the invention, supplied here by a voltage Vbat supplied by a battery 21. The regulator 20 includes as that of FIG. 1 a differential amplifier 22 whose output controls the gate of a transistor PMOS type regulation 23. The drain D of transistor 23 is connected to the output of regulator 20 and is connected to a stabilization capacity Cst in parallel with a load Z, these various elements being arranged as described in the preamble. The output voltage Vout is brought back to the positive input of amplifier 2 by via a divider bridge comprising two resistors R1, R2. The resistance R1 can be zero in the case of a direct feedback of the voltage of output Vout on the input of amplifier 22, the resistance R2 in this case being mathematically infinite. The reference voltage Vref applied to the input negative of amplifier 2 is for example a voltage so-called band-gap with good stability in temperature function, generated by means of diodes PN junction and current mirrors. The voltage Vref is thus independent of the voltage Vbat, on the condition to be less than the lowest voltage value Vbat.

Le fonctionnement du régulateur 20 en régime stabilisé est en soi classique et ne sera pas à nouveau décrit. L'amplificateur 2 maintient la tension de contre-réaction Vfb égale à la tension de référence Vref et la tension de sortie nominale Voutnom est égale à [(R1+R2)Vref/R2].The operation of regulator 20 under operating conditions stabilized is inherently classic and will not be again described. Amplifier 2 maintains the feedback voltage Vfb equal to the reference voltage Vref and the nominal output voltage Voutnom is equal to [(R1 + R2) Vref / R2].

Selon l'invention, l'amplificateur 22 présente un mode de fonctionnement "normal" et un mode "veille" et bascule de l'un à l'autre selon la valeur d'un signal Vlc appliqué sur une entrée LCIN prévue à cet effet. La mise en veille de l'amplificateur 22 consiste, selon l'invention, dans le fait de placer l'amplificateur dans un état de faible consommation électrique tout en maintenant la tension de grille Vg à un potentiel assurant le maintient du transistor de régulation 23 dans l'état passant. Divers exemples de réalisation de l'amplificateur 22 seront décrits plus loin. On considèrera par convention, dans ce qui suit, que l'amplificateur bascule en mode veille lorsque le signal Vlc passe à 1.According to the invention, the amplifier 22 has a "normal" operating mode and a "standby" mode and switches from one to the other according to the value of a signal Vlc applied to an LCIN input provided for this purpose. Setting standby amplifier 22 consists, according to the invention, in placing the amplifier in a state of low power consumption while now the gate voltage Vg at a potential maintaining the regulation transistor 23 in the passing state. Various examples of realization of the amplifier 22 will be described later. We will consider by convention, in what follows, that the amplifier switches to standby mode when the signal Vlc goes to 1.

Le signal Vlc est délivré par un comparateur 24 recevant sur son entrée positive la tension de sortie Vout et sur son entrée négative la tension d'alimentation Vbat, le comparateur 24 étant alimenté par la tension Vbat. Le comparateur 24 est un comparateur à seuil Vd1 et met ici sa sortie à 1 (signal Vlc) lorsque la tension différentielle Vd vue sur ses entrées, égale à la différence entre la tension Vbat et la tension Vout, devient inférieure au seuil Vd1. Pour des raisons de stabilité de sa sortie, le comparateur 24 présente également, de préférence, une hystérésis de commutation et remet sa sortie à 0 lorsque la tension différentielle Vd remonte et devient supérieure à un seuil Vd2 supérieur à Vd1. Les seuils Vd1, Vd2 sont par exemple égaux à 100 mV et 120mV, respectivement.The signal Vlc is delivered by a comparator 24 receiving on its positive input the output voltage Vout and on its negative input the supply voltage Vbat, the comparator 24 being supplied by the voltage Vbat. Comparator 24 is a threshold comparator Vd1 and here sets its output to 1 (signal Vlc) when the voltage differential Vd seen on its inputs, equal to the difference between the voltage Vbat and the voltage Vout, becomes below the threshold Vd1. For reasons of stability of its output, comparator 24 has also, preferably, a switching hysteresis and resets its output to 0 when the differential voltage Vd goes up and becomes higher than a higher threshold Vd2 to Vd1. The thresholds Vd1, Vd2 are for example equal to 100 mV and 120mV, respectively.

Ainsi, comme on va le voir plus en détail dans ce qui suit, l'amplificateur 22 bascule dans le mode veille tout en maintenant le transistor de régulation 23 dans l'état passant, lorsque le régulateur 20 fonctionne en mode suiveur en raison d'une chute de la tension d'alimentation Vbat en dessous de la valeur nominale Voutnom de la tension de sortie.So, as we will see in more detail in this which follows, amplifier 22 switches to standby mode while holding the regulating transistor 23 in the on state, when the regulator 20 operates in follower mode due to voltage drop Vbat power supply below the nominal value Voutnom of the output voltage.

Les figures 5A, 5B, 5C illustrent le fonctionnement du régulateur 20 en mode suiveur et représentent respectivement les tensions Vbat et Vout, la tension différentielle Vd et le signal Vlc. Sur les figures 5A et 5B, on voit qu'une diminution de la tension Vbat à partir de sa valeur nominale Vbatnom n'a pas de conséquence sur la tension régulée Vout, qui demeure égale à Voutnom, tant que la tension Vbat reste supérieure à Voutnom. La tension différentielle Vd diminue proportionnellement à la tension Vbat jusqu'à un instant t2 où la tension Vbat devient sensiblement égale à Voutnom et entraíne la tension Vout dans sa chute, le régulateur étant alors déséquilibré et fonctionnant en mode suiveur. A cet instant t2, la tension différentielle Vd atteint une valeur minimale Vdmin qui correspond à la chute de tension aux bornes du transistor de régulation 23. Cette chute de tension Vdmin est en principe très faible, par exemple 50 mV, car le transistor de régulation d'un régulateur de type LDO présente généralement une résistance drain-source VdsON dans l'état passant très faible. A compter de l'instant t2, la tension Vout commence à diminuer et suit la tension Vbat, au décalage près de la tension Vdmin.Figures 5A, 5B, 5C illustrate the operation of regulator 20 in follower mode and represent the voltages Vbat and Vout respectively, the voltage differential Vd and the signal Vlc. In Figures 5A and 5B, it can be seen that a decrease in the voltage Vbat from of its nominal value Vbatnom has no consequence on the regulated voltage Vout, which remains equal to Voutnom, as long as the voltage Vbat remains greater than Voutnom. The differential voltage Vd decreases in proportion to the voltage Vbat until an instant t2 where the voltage Vbat becomes substantially equal to Voutnom and causes the voltage Vout in its fall, the regulator then being unbalanced and operating in follower mode. In this instant t2, the differential voltage Vd reaches a minimum value Vdmin which corresponds to the fall of voltage across the regulation transistor 23. This voltage drop Vdmin is in principle very small, by example 50 mV, because the regulating transistor of a LDO type regulator usually has a VdsON drain-source resistance in the very on state low. From time t2, the voltage Vout begins to decrease and follows the voltage Vbat, at the offset near the voltage Vdmin.

Selon l'invention, le passage en mode suiveur est détecté par le comparateur 24 à un instant t1 précédant t2 mais très proche de t2, lorsque la tension différentielle Vd atteint le seuil Vd1 mentionné plus haut, choisi très proche du minimum Vdmin. Ainsi, à l'instant t1, le signal Vlc passe à 1 (fig. 5C) et l'amplificateur 2 est mis en veille. Le "1" logique du signal Vlc est ici la tension Vbat, qui alimente le comparateur 24.According to the invention, the transition to follower mode is detected by comparator 24 at a time t1 preceding t2 but very close to t2, when the voltage differential Vd reaches the threshold Vd1 mentioned more high, chosen very close to the minimum Vdmin. So at at time t1, the signal Vlc goes to 1 (fig. 5C) and amplifier 2 is put on standby. The logical "1" of signal Vlc here is the voltage Vbat, which supplies the comparator 24.

Sur les figures 5A à 5C, ont voit que la tension Vbat remonte ensuite vers sa valeur nominale, par exemple après rechargement de la batterie 21 ou régénération naturelle de celle-ci lorsque le courant consommé diminue. A un instant t3, la tension Vbat dépasse la valeur Voutnom. A un instant t4, la tension différentielle Vd dépasse le seuil Vd2 et l'amplificateur 22 bascule dans son mode de fonctionnement normal, la tension Vout revenant à sa valeur nominale Voutnom.In FIGS. 5A to 5C, have seen that the voltage Vbat then goes back up to its nominal value, for example after recharging the battery 21 or regenerating natural of it when the current consumed decreases. At an instant t3, the voltage Vbat exceeds the Voutnom value. At an instant t4, the voltage differential Vd exceeds the threshold Vd2 and the amplifier 22 switches to its normal operating mode, the voltage Vout returning to its nominal value Voutnom.

On va maintenant décrire à titre non limitatif divers modes de réalisation de l'amplificateur 22, obtenus à partir de la structure de l'amplificateur 2 décrit au préambule en relation avec la figure 2.We will now describe, without limitation various embodiments of the amplifier 22, obtained from the structure of amplifier 2 described in the preamble in relation to Figure 2.

L'amplificateur 22a illustré en figure 6 est d'une structure semblable à celle de l'amplificateur 2. On y retrouve l'étage différentiel 5 polarisé par le générateur de courant 6, dont la sortie pilote le transistor NMOS 7 polarisé sur son drain par le générateur de courant 8, ainsi que la résistance Rg reliant le noeud de sortie de l'amplificateur 22a à la tension Vbat. Selon l'invention, un interrupteur 25, ici un transistor PMOS, est agencé en série avec la résistance Rg. Le transistor 25 reçoit sur sa grille le signal Vlc et est ainsi en permanence dans l'état passant lorsque le régulateur fonctionne en régime stabilisé, le signal Vlc étant à 0 comme indiqué plus haut. Lorsque le régulateur fonctionne en mode suiveur et que la tension Vg sur le noeud de sortie est tirée vers la masse par le transistor NMOS 7, le signal Vlc passe à 1, le transistor 25 se bloque et aucun courant ne passe dans la résistance Rg. En coupant ainsi le chemin reliant le noeud de sortie de l'amplificateur 22a à la tension Vbat, l'économie en consommation de courant peut être substantielle et de l'ordre de 80%.The amplifier 22a illustrated in FIG. 6 is of a structure similar to that of amplifier 2. There finds the differential stage 5 polarized by the current generator 6, the output of which controls the NMOS transistor 7 polarized on its drain by the current generator 8, as well as the resistance Rg connecting the output node of amplifier 22a to the Vbat voltage. According to the invention, a switch 25, here a PMOS transistor, is arranged in series with the resistance Rg. The transistor 25 receives on its gate the signal Vlc and is thus permanently in the on state when the regulator is operating in steady state, the signal Vlc being at 0 as indicated above. When the regulator operates in follower mode and that the voltage Vg on the output node is pulled to ground by the NMOS transistor 7, the Vlc signal goes to 1, the transistor 25 is blocked and no current flows through the resistor Rg. By thus cutting the path connecting the output node from amplifier 22a to voltage Vbat, the economy in current consumption can be substantial and around 80%.

L'amplificateur 22b représenté en figure 7 est quasiment identique à l'amplificateur 22a. Toutefois, les générateurs de courant 6, 8 ont été remplacés par des générateurs de courant 6', 8' qui sont commandés par le signal Vlc et qui délivrent des courants différents selon la valeur du signal Vlc. Les courants respectifs I1', I2' délivrés lorsque le signal Vlc est à 1 sont par exemple égaux à la moitié des courants I1, I2 délivrés lorsque le signal Vlc est à 0. Les courants I1', I2' sont par exemple de 10 microampères et les courants I1, I2 de 20 microampères. La réalisation de tels générateurs 6', 8' à deux courants de fonctionnement est en soi à la portée de l'homme de l'art, par exemple en agençant en parallèle, dans des miroirs de courants, des transistors de même structure, et en bloquant un transistor sur deux lorsque le signal Vlc est à 1. On économise ainsi, par cet arrangement, quelques dizaines de microampères supplémentaires.The amplifier 22b shown in FIG. 7 is almost identical to amplifier 22a. However, current generators 6, 8 have been replaced by current generators 6 ', 8' which are controlled by the signal Vlc and which deliver different currents according to the value of the signal Vlc. The respective currents I1 ', I2' delivered when the signal Vlc is at 1 are for example equal to half of the currents I1, I2 delivered when the signal Vlc is at 0. The currents I1 ', I2' are by example of 10 microamps and the currents I1, I2 of 20 microamps. The realization of such generators 6 ', 8' to two operating currents is in itself within the reach of those skilled in the art, for example by arranging in parallel, in current mirrors, transistors as well structure, and blocking every other transistor when the signal Vlc is at 1. One thus saves, by this arrangement, a few dozen microamps additional.

L'amplificateur 22c de la figure 8 est réalisé à partir de l'amplificateur 2 de la figure 2, que l'on n'a pas modifié dans sa structure interne. Toutefois, la tension Vbat est appliquée sur l'entrée d'alimentation de l'amplificateur 2 par l'intermédiaire d'un transistor PMOS 26 piloté par le signal Vlc. De plus, un transistor NMOS 27 piloté par le signal Vlc est ajouté entre la sortie de l'amplificateur 2 et la masse. Ainsi, lorsque le signal Vlc est à 0 (régulateur équilibré), le transistor 26 est passant et le transistor 27 est bloqué. L'amplificateur 2 fonctionne comme si ces deux éléments n'existaient pas. Lorsque le signal Vlc est à 1 (régulateur en mode suiveur), le transistor 26 est bloqué et le transistor 27 est passant. L'amplificateur 2 ne reçoit plus la tension d'alimentation Vbat et est complètement hors tension. Le transistor 27 tire la sortie de l'amplificateur à 0 (tension Vg) pour maintenir le transistor de régulation 23 dans l'état passant. Ce mode de réalisation 22c se distingue donc des précédents 22a, 22b par le fait qu'en mode veille la tension de grille Vg n'est pas tirée à la masse par le transistor NMOS 2 de l'étage de sortie de l'amplificateur 2, qui est hors service, mais par le transistor supplémentaire 27 prévu à cet effet. The amplifier 22c of FIG. 8 is produced at starting from the amplifier 2 of FIG. 2, which we have not changed in its internal structure. However, the Vbat voltage is applied to the power input of amplifier 2 via a transistor PMOS 26 controlled by the Vlc signal. In addition, a transistor NMOS 27 driven by the Vlc signal is added between the amplifier 2 output and ground. So when signal Vlc is at 0 (balanced regulator), the transistor 26 is on and transistor 27 is blocked. Amplifier 2 works as if these two elements did not exist. When the signal Vlc is at 1 (regulator in follower mode), transistor 26 is blocked and transistor 27 is on. Amplifier 2 does not no longer receives the supply voltage Vbat and is completely off. The transistor 27 draws the amplifier output at 0 (voltage Vg) to maintain the regulating transistor 23 in the on state. This embodiment 22c therefore differs from the preceding 22a, 22b by the fact that in standby mode the voltage of gate Vg is not grounded by the transistor NMOS 2 of the output stage of amplifier 2, which is out of service, but by the additional transistor 27 meant for that purpose.

L'amplificateur 22d représenté en figure 9 comprend également l'amplificateur 2 et le transistor 26 assurant la mise hors tension de l'amplificateur 2 lorsque le signal Vlc est à 1. Le transistor tire-bas 27 (pull down) à la sortie de l'amplificateur 22c est remplacé par un étage de polarisation 30 plus perfectionné qui maintient la sortie de l'amplificateur 2 à une tension Vg supérieure à la masse quand celui-ci est hors tension. Cette tension Vg est choisie de manière que la tension grille-source Vgs du transistor de régulation 23 soit maintenue au voisinage de la tension de seuil Vtp du transistor 23.The amplifier 22d represented in FIG. 9 comprises also amplifier 2 and transistor 26 ensuring switching off amplifier 2 when the signal Vlc is at 1. The pull-down transistor 27 (pull down) at the output of amplifier 22c is replaced by a 30 more advanced bias stage which maintains the output of amplifier 2 at a voltage Vg greater than ground when it is off. This voltage Vg is chosen so that the voltage source gate Vgs of the regulation transistor 23 or maintained in the vicinity of the threshold voltage Vtp of the transistor 23.

L'étape de polarisation 30 comprend par exemple un premier transistor PMOS 31 recevant la tension Vbat sur sa source, connecté par son drain à la source d'un deuxième transistor PMOS 32 dont le drain est connecté au noeud de sortie de l'amplificateur 22d. Les transistors 31, 32 sont agencés en diodes, chacun ayant sa grille connectée à son drain. Entre le noeud de sortie et la masse, l'étage de polarisation 30 comprend une résistance 33 de forte valeur en série avec un transistor NMOS 34 piloté par le signal Vlc. Lorsque le régulateur fonctionne en régime stabilisé, la tension Vg est maintenue autour de la valeur [Vbat - Vtp] par la sortie de l'amplificateur 2, Vtp étant la tension de seuil d'un transistor PMOS, de sorte que les deux transistors-diodes 31, 32 sont bloqués. De plus, le signal Vlc est à 0 et le transistor 34 est également bloqué. L'amplificateur 2 fonctionne comme si l'étage de polarisation 30 n'existait pas. Lorsque régulateur est déséquilibré, la tension Vg tend vers 0, le signal Vlc passe à 1 et l'amplificateur 2 est mis hors tension. Les deux transistors-diodes 31, 32 deviennent passants et imposent chacun une tension Vtp à leurs bornes, de sorte que la tension de grille Vg est dans ce cas égale à [Vbat - (2Vtp)]. La tension Vgs du transistor de régulation 23 est ainsi égale à 2Vtp en valeur absolue et est proche de Vtp (à la valeur Vtp près, de l'ordre de 0,7 V). D'autres méthodes sont bien entendu envisageables pour maintenir la tension Vg encore plus proche de la tension de seuil Vtp.The polarization step 30 comprises for example a first PMOS transistor 31 receiving the voltage Vbat on its source, connected by its drain to the source of a second PMOS transistor 32 whose drain is connected to the amplifier output node 22d. Transistors 31, 32 are arranged in diodes, each having its grid connected to its drain. Between the output node and the ground, the bias stage 30 includes a resistor 33 of high value in series with an NMOS transistor 34 driven by the Vlc signal. When the regulator operates in steady state, the voltage Vg is maintained around the value [Vbat - Vtp] by the output of amplifier 2, Vtp being the threshold voltage of a PMOS transistor, so the two diode transistors 31, 32 are blocked. In addition, the signal Vlc is at 0 and the transistor 34 is also blocked. Amplifier 2 operates as if bias stage 30 did not exist not. When the regulator is unbalanced, the voltage Vg tends to 0, signal Vlc goes to 1 and amplifier 2 is turned off. The two diode transistors 31, 32 become passers-by and each impose a voltage Vtp at their terminals, so the gate voltage Vg is in this case equal to [Vbat - (2Vtp)]. The voltage Vgs of regulation transistor 23 is thus equal to 2Vtp in absolute value and is close to Vtp (at the value Vtp close, of the order of 0.7 V). Other methods are good heard possible to maintain the voltage Vg still closer to the threshold voltage Vtp.

L'avantage de ce mode de réalisation est de ne pas décharger entièrement la capacité parasite de grille Cg du transistor de régulation 23, représentée en traits pointillés, qui est généralement de forte valeur (100-200 picofarads) avec un transistor de régulation à faible résistance série RdsON. En effet, lorsque la tension Vg est portée à la masse, la capacité Cg est entièrement déchargée pendant le mode veille. Si la tension Vbat remonte brutalement, un retard à la fermeture du transistor 23 (blocage du transistor) se produit lors du retour au mode régulé en raison du temps de charge de la capacité Cg. Un tel retard à la fermeture fait apparaítre une surtension à la sortie du régulateur, car la tension Vout continue de suivre la tension Vbat au-delà de sa valeur nominale Voutnom. En maintenant la tension Vg non nulle pendant le mode veille, la capacité de grille Cg ne se décharge pas entièrement et le basculement du mode veille au mode régulé se fait rapidement, avec une nette atténuation du phénomène de surtension.The advantage of this embodiment is that it does not fully discharge the stray capacitance of grid Cg of the regulation transistor 23, shown in lines dotted, which is usually of high value (100-200 picofarads) with a low regulation transistor resistance RdsON series. Indeed, when the voltage Vg is brought to ground, the Cg capacity is fully discharged during standby mode. If the voltage Vbat goes up suddenly, a delay in closing the transistor 23 (transistor blocking) occurs during return to regulated mode due to the charging time of the capacity Cg. Such a delay in closing reveals an overvoltage at the regulator output, because the voltage Vout continues to follow Vbat voltage beyond its nominal value Voutnom. Maintaining the voltage Vg no zero during standby mode, the grid capacity Cg does not not fully discharging and switching the mode Standby in regulated mode is done quickly, with a clear attenuation of the overvoltage phenomenon.

Bien entendu, diverses combinaisons des caractéristiques de chacun des amplificateurs 22a à 22d peuvent être prévues, pour réaliser d'autres variantes de réalisation. Notamment, l'étage de polarisation 30 de l'amplificateur 22d peut être incorporé dans les amplificateurs 22a, 22b. Il est également à la portée de l'homme de l'art d'appliquer les principes et solutions exposés ci-dessus à des structures d'amplificateur connues autres que celle de l'amplificateur 2 choisi ici à titre d'exemple. Par ailleurs, bien que les exemples qui viennent d'être décrits se rapportent à un régulateur ayant un transistor de régulation de type PMOS, il entre dans le cadre de la présente demande et il est à la portée de l'homme de l'art de transposer l'enseignement de la présente invention aux régulateurs ayant un transistor de régulation de type NMOS.Of course, various combinations of characteristics of each of the amplifiers 22a to 22d can be provided, to make other variants of production. In particular, the bias stage 30 of the 22d amplifier can be incorporated in the amplifiers 22a, 22b. It is also within reach of those skilled in the art of applying the principles and solutions exposed above to amplifier structures known other than that of amplifier 2 chosen here for exemple. By the way, although the examples which have just been described relate to a regulator having a PMOS type regulation transistor, it enters as part of this application and it is at the scope of the skilled person to transpose the teaching of the present invention to regulators having a NMOS type regulation transistor.

Enfin, bien que le problème résolu par la présente invention ait été décrit en relation avec les téléphones portables, il va de soi qu'un régulateur selon l'invention est susceptible de diverses autres applications, notamment dans le cas où la tension d'alimentation est fournie par une batterie dont on veut préserver l'autonomie.Finally, although the problem solved by this invention has been described in connection with telephones portable, it goes without saying that a regulator the invention is susceptible to various other applications, especially in cases where the voltage power is supplied by a battery which we want preserve autonomy.

Claims (15)

Régulateur de tension (20) comprenant un transistor MOS de régulation (23) et un amplificateur (22, 22a-22d) dont la sortie pilote la grille du transistor de régulation en fonction de l'écart entre une tension de référence (Vref) et une tension de contre-réaction (Vfb), caractérisé en ce qu'il comprend des moyens (6', 7', 24, 25, 27, 27, 30) pour faire basculer l'amplificateur dans un mode de veille à faible consommation de courant lorsque l'écart (Vd) entre la tension d'alimentation (Vbat) et la tension de sortie (Vout) du régulateur est inférieur à un premier seuil (Vd1), tout en maintenant sur la grille du transistor de régulation (23) un potentiel électrique permettant de maintenir le transistor de régulation dans l'état passant.Voltage regulator (20) comprising a regulation MOS transistor (23) and an amplifier (22, 22a-22d), the output of which controls the gate of the regulation transistor as a function of the difference between a reference voltage (Vref) and a feedback voltage (Vfb), characterized in that it comprises means (6 ', 7', 24, 25, 27, 27, 30) for switching the amplifier into a standby mode with low consumption current when the difference (Vd) between the supply voltage (Vbat) and the output voltage (Vout) of the regulator is less than a first threshold (Vd1), while maintaining the gate of the regulation transistor (23 ) an electrical potential allowing the regulation transistor to be kept in the on state. Régulateur selon la revendication 1, comprenant un comparateur (24) agencé pour comparer la tension d'alimentation (Vbat) et la tension de sortie (Vout) du régulateur, et délivrer à l'amplificateur (22) un signal de mise en veille (Vlc=1) lorsque l'écart (Vd) entre la tension d'alimentation et la tension de sortie du régulateur est inférieur au premier seuil (Vd1).The regulator of claim 1, comprising a comparator (24) arranged to compare the voltage power supply (Vbat) and the output voltage (Vout) of the regulator, and outputting a signal to the amplifier (22) standby (Vlc = 1) when the difference (Vd) between the supply voltage and the output voltage of the regulator is lower than the first threshold (Vd1). Régulateur selon la revendication 2, caractérisé en ce que le comparateur (24) présente une hystérésis de commutation et annule le signal de mise en veille de l'amplificateur (Vlc=0) lorsque l'écart (Vd) entre la tension d'alimentation et la tension de sortie du régulateur est supérieur à un second seuil (Vd2) supérieur au premier seuil (Vd1).Regulator according to claim 2, characterized in that the comparator (24) has a switching hysteresis and cancels the signal for putting the amplifier on standby (Vlc = 0) when the difference (Vd) between the supply voltage and the regulator output voltage is greater than a second threshold (Vd2) greater than the first threshold (Vd1). Régulateur selon l'une des revendications 1 à 3, dans lequel l'amplificateur (22a, 22b) comprend une résistance (Rg) reliant la sortie de l'amplificateur à la tension d'alimentation (Vbat), caractérisé en ce qu'un interrupteur (25) est agencé en série avec la résistance (Rg) et en ce que ledit interrupteur agencé en série avec la résistance est ouvert lorsque l'amplificateur est mis en veille et fermé dans le cas contraire.Regulator according to one of Claims 1 to 3, in which the amplifier (22a, 22b) comprises a resistor (Rg) connecting the output of the amplifier to the supply voltage (Vbat), characterized in that a switch (25) is arranged in series with the resistor (Rg) and in that said switch arranged in series with the resistor is open when the amplifier is put on standby and closed otherwise. Régulateur selon l'une des revendications 1 à 4, dans lequel l'amplificateur (22b) comprend des sources de courant (6', 8') basculant en mode faible courant lorsque l'amplificateur est mis en veille.Regulator according to one of claims 1 to 4, wherein the amplifier (22b) includes sources of current (6 ', 8') switching to low current mode when the amplifier is put on standby. Régulateur selon l'une des revendications 1 à 5, dans lequel l'amplificateur comprend un interrupteur (27) piloté par un signal de mise en veille (Vlc) pour connecter la grille du transistor de régulation (23) à un potentiel électrique rendant le transistor passant lorsque l'amplificateur est mis en veille.Regulator according to one of claims 1 to 5, wherein the amplifier includes a switch (27) controlled by a standby signal (Vlc) to connect the gate of the regulation transistor (23) to a electrical potential making the transistor on when the amplifier is put on standby. Régulateur selon l'une des revendications 1 à 6, dans lequel l'amplificateur (22d) comprend un étage (30) de polarisation de la grille du transistor de régulation (23), agencé pour appliquer sur la grille du transistor de régulation, lorsque l'amplificateur est mis en veille, une tension (Vg) qui est déterminée de manière que la tension grille-source (Vgs) du transistor de régulation soit proche de la tension de seuil (Vtp) du transistor de régulation.Regulator according to one of claims 1 to 6, wherein the amplifier (22d) comprises a stage (30) of polarization of the gate of the regulation transistor (23), arranged to apply to the gate of the transistor regulation, when the amplifier is put on standby, a voltage (Vg) which is determined so that the gate-source voltage (Vgs) of the regulation transistor is close to the threshold voltage (Vtp) of the transistor regulation. Régulateur selon l'une des revendications 6 et 7, dans lequel l'alimentation électrique de l'amplificateur (22c, 22d) est supprimée en mode veille par un interrupteur (26).Regulator according to one of claims 6 and 7, in which the power supply of the amplifier (22c, 22d) is suppressed in standby mode by a switch (26). Téléphone mobile comprenant une batterie et des circuits radio alimentés par l'intermédiaire d'un régulateur (20) selon l'une des revendications 1 à 8.Mobile phone with battery and radio circuits powered by a regulator (20) according to one of claims 1 to 8. Procédé de gestion de l'énergie disponible dans une batterie (21) alimentant une charge (Z) par l'intermédiaire d'un régulateur de tension (20), le régulateur comprenant un transistor MOS de régulation (23) et un amplificateur (22) dont la sortie pilote la grille du transistor de régulation en fonction de l'écart entre une tension de référence (Vref) et une tension de contre-réaction (Vfb), procédé caractérisé en ce qu'il comprend une étape consistant à surveiller l'écart (Vd) entre la tension d'alimentation (Vbat) et la tension de sortie (Vout) du régulateur, et une étape consistant à faire basculer l'amplificateur (22) dans un mode veille à faible consommation de courant lorsque l'écart (Vd) entre la tension d'alimentation (Vbat) et la tension de sortie (Vout) du régulateur est inférieur à un premier seuil (Vd1), tout en maintenant la grille du transistor de régulation (23) à un potentiel permettant de maintenir le transistor de régulation dans l'état passant.Method for managing the energy available in a battery (21) supplying a load (Z) via a voltage regulator (20), the regulator comprising a regulating MOS transistor (23) and an amplifier (22 ) the output of which controls the gate of the regulation transistor as a function of the difference between a reference voltage (Vref) and a feedback voltage (Vfb), method characterized in that it comprises a step consisting in monitoring the deviation (Vd) between the supply voltage (Vbat) and the output voltage (Vout) of the regulator, and a step consisting in switching the amplifier (22) to a standby mode with low current consumption when the difference (Vd) between the supply voltage (Vbat) and the output voltage (Vout) of the regulator is less than a first threshold (Vd1), while maintaining the gate of the regulation transistor (23) at a potential allowing to keep the regulating transistor in the state passerby. Procédé selon la revendication 10, caractérisé en ce que l'on réactive l'amplificateur (20) lorsque l'écart (Vd) entre la tension d'alimentation et la tension de sortie du régulateur est supérieur à un second seuil (Vd2) supérieur au premier seuil (Vd1).Method according to claim 10, characterized in that the amplifier (20) is reactivated when the difference (Vd) between the supply voltage and the output voltage of the regulator is greater than a second upper threshold (Vd2) at the first threshold (Vd1). Procédé selon l'une des revendications 10 et 11, dans lequel on réduit la consommation de l'amplificateur (22, 22a, 22b) en mode veille en déconnectant (25, Vlc=1) le noeud de sortie de l'amplificateur de la tension d'alimentation (Vbat).Method according to one of claims 10 and 11, in which the consumption of the amplifier (22, 22a, 22b) in standby mode in disconnecting (25, Vlc = 1) the output node of the supply voltage amplifier (Vbat). Procédé selon l'une des revendications 10 à 12, dans lequel on réduit la consommation de l'amplificateur (22, 22b) en mode veille en diminuant le courant délivré par des sources de courant (6', 8') internes à l'amplificateur.Method according to one of claims 10 to 12, in which the consumption of the amplifier is reduced (22, 22b) in standby mode by reducing the current delivered by current sources (6 ', 8') internal to the amplifier. Procédé selon l'une des revendications 10 et 11, dans lequel on supprime l'application de la tension d'alimentation à l'amplificateur en mode veille. Method according to one of claims 10 and 11, in which the application of the voltage is suppressed power to amplifier in standby mode. Procédé selon l'une des revendications 10 à 14, dans lequel on applique sur la grille du transistor de régulation (23), lorsque l'amplificateur est mis en veille, une tension (Vg) qui est déterminée de manière que la tension grille-source (Vgs) du transistor de régulation soit proche de la tension de seuil (Vtp) du transistor de régulation.Method according to one of claims 10 to 14, in which we apply to the gate of the transistor regulation (23), when the amplifier is switched on standby, a voltage (Vg) which is determined so that the gate-source voltage (Vgs) of the transistor regulation is close to the threshold voltage (Vtp) of the regulating transistor.
EP01108243A 2000-04-12 2001-03-31 Voltage regulator with low power consumption Expired - Lifetime EP1148404B1 (en)

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EP1148404B1 (en) 2005-11-02

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