EP1380913B1 - Linear voltage regulator - Google Patents

Linear voltage regulator Download PDF

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Publication number
EP1380913B1
EP1380913B1 EP03300056.3A EP03300056A EP1380913B1 EP 1380913 B1 EP1380913 B1 EP 1380913B1 EP 03300056 A EP03300056 A EP 03300056A EP 1380913 B1 EP1380913 B1 EP 1380913B1
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EP
European Patent Office
Prior art keywords
output
input
voltage
transistor
circuit
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EP03300056.3A
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German (de)
French (fr)
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EP1380913A1 (en
Inventor
Alexandre Pons
Christophe Bernard
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STMicroelectronics SA
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STMicroelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present invention generally relates to the regulation of a voltage across a load. More particularly, the present invention relates to such regulation carried out linearly.
  • the document EP1061428 describes a linear regulator.
  • the figure 1 illustrates, schematically and partially, a conventional example of a linear regulator of a voltage Vout across a load (LD) 1.
  • the regulator comprises a P-channel MOS transistor 2 whose source is connected to a rail of high voltage supply Vdd and whose drain constitutes the output terminal OUT of the regulator.
  • the load 1 is connected between the OUT terminal and a low supply rail or a reference voltage or ground GND.
  • the transistor 2 operates in linear mode, that is to say that its transconductance is used to vary its output current as a function of the control voltage applied to its gate G.
  • the control voltage of the gate G is regulated according to the voltage Vout across the load 1.
  • the regulation is performed by a differential comparator 3 having an input / output stage 4 and an output stage 5.
  • the input / output stage 4 comprises two differential branches each comprising a P-channel MOS transistor 61, 62 connected in series with an N-channel MOS transistor 63, 64.
  • the sources of the transistors 61 and 62 are connected to an output terminal of a current source 60 having an input terminal connected to the high power supply Vdd.
  • the sources of transistors 63 and 64 are connected to the low GND supply.
  • the gates of transistors 63 and 64 are interconnected.
  • One branch 61-63 constitutes an input branch, while the other branch 62-64 constitutes an output branch.
  • the transistor 61 of the input branch receives a constant DC voltage setpoint Vreg supplied by a voltage generator 8 connected between the gate of the transistor 61 and the ground GND.
  • the gate of the transistor 63 is connected to its drain, that is to say also to the drain of the transistor 61.
  • the gate of the transistor 63 receives the voltage Vout across the load 1 by a connection to the output terminal OUT of regulator, possibly at an intermediate point of a resistance bridge.
  • the connection point 65 of the drains of the transistors 62 and 64 constitutes the output of the input / output stage 4 of the comparator 3.
  • the output stage 5 consists of the series connection, between the high Vdd and low GND supplies, of a generally resistive impedance (R) and of an N-channel MOS transistor 10.
  • the connection point of the impedance 9 and transistor 10 constitutes the output terminal of the differential comparator 3 connected to the gate G of the regulation transistor 2.
  • the gate of the transistor 10 is connected to the point 65 of the differential input / output branch 62-64.
  • the regulator further comprises an impedance (C) 11, generally capacitive, for stabilizing the output voltage Vout.
  • C impedance
  • the Figures 2A-2C illustrate, by timing diagrams, an example of variation as a function of the time t of the voltage setpoint Vreg at the terminals of the source 8, the output voltage Vout across the load 1, and the voltage Vds between the terminals of drain and source of the transistor 2.
  • the constant constant voltage generator 8 is enabled so that it delivers a stable non-zero nominal regulation setpoint Vref up to a time t1 circuit extinction.
  • the differential comparator 3 then forces, as illustrated by Figure 2B , the output voltage Vout to follow the regulation voltage Vreg and to align with the reference level Vref.
  • the voltage Vout is then stably regulated at the Vref level by the gate control until the instant t1 of switching off or putting the circuit on standby.
  • This regulation is performed by a linear control of transistor 2 which is used as a variable transconductance whose output current depends on the control voltage on gate G.
  • the load 1 is to be supplied at a voltage level of the order of 3.3 to 5.5 volts are more particularly considered in the present description. Such a value is relatively high compared to the maximum voltage of the order of 2.4 to 2.8 volts that can hold the components (in particular the MOS transistor 2) used in standard integration technology channels. However, during the periods of extinction of the load 1, the MOS transistor 2 must hold the voltage Vdd at its terminals.
  • the standard 2.5-volt manufacturing die has been modified to insert MOS transistors capable of holding a maximum voltage greater than 5 volts between their drain and their source.
  • MOS transistors capable of holding a maximum voltage greater than 5 volts between their drain and their source.
  • the definition masks of the regulation transistor 2 with respect to to neighboring transistors so as to substantially increase the thickness of a portion of a gate insulator near one of the drain / source regions and to increase the area of the same drain / source region.
  • the parasitic gate capacitance of transistor 2 is increased, and its transconductance is reduced.
  • it is necessary that the transconductance is relatively high. To increase it, it is then necessary to further increase the integration surface of the transistor 2.
  • bipolar type regulating transistor which has the advantage of requiring a smaller integration area relative to the specific MOS, in particular because it can more easily be integrated in a vertical in a silicon substrate.
  • the use of a bipolar transistor poses many problems.
  • CMOS sector which is more complex than the MOS sector. It is also necessary to provide a specific circuit for setting the operating point of the bipolar transistor, and in particular to provide a limitation of the base current.
  • a bipolar control transistor leads to higher waste voltages than a MOS transistor with a smaller linearity range. This is particularly disadvantageous in the case of portable type devices for which it is desirable to minimize the waste voltage, i.e. to make it, preferably, less than 200 mV.
  • the present invention aims to provide a linear regulator that overcomes the disadvantages of known circuits.
  • the present invention aims in particular to provide a linear regulator which has a reduced waste voltage.
  • the present invention aims to provide such a regulator that can be manufactured using a standard MOS die.
  • the present invention provides a linear regulator having an output stage comprising first and second P-channel MOS transistors connected in series between a first DC power terminal and an output terminal providing an output terminal. regulated output voltage, and a control circuit of the first and second transistors capable of providing first and second control signals as a function of the output voltage and the voltage at the midpoint of the series connection.
  • the control circuit comprises an input / output circuit and a reference circuit, the input / output circuit having a first input, receiving a first voltage setpoint provided by said reference circuit; a second input, connected to said output terminal; a third input receiving a second voltage setpoint supplied by said reference circuit; a fourth input connected to said midpoint; a first output connected to the gate of the first transistor; and a second output connected to the gate of the second transistor.
  • the input / output circuit is a dual differential comparator with four inputs and two outputs.
  • the input / output circuit comprises first and second differential comparators with two inputs and two outputs, the input terminals of the first differential comparator being the first and second input terminals of the input comparator. an input / output circuit and its output being the second output of said input / output circuit; and the input terminals of the second differential comparator being the third and fourth input terminals of said input / output circuit and its output being the first output.
  • the first differential comparator comprises an input / output stage and an output stage, said input / output stage comprising two differential branches, each of which comprises a P-channel MOS transistor connected in parallel. series with a first N-channel MOS transistor, the sources of the P-channel transistors being interconnected to an output terminal of a current source whose input terminal is connected to said DC power terminal, the sources of the first N-channel transistors being interconnected to a ground terminal, the gates of said first N-channel MOS transistors being interconnected, the gates of the P-channel transistors constituting the first and second input terminals of the input / output circuit, the gate of the first N-channel MOS transistor of the branch having the first input being connected to its drain, the intermediate connection point of the drains of the complementary transistors of the other branch being connected to the gate of a second N-channel MOS transistor connected in said output stage, in series between the power supply terminals, with a first impedance, the midpoint of the series connection of said first impedance and the second
  • the second differential comparator comprises two symmetrical differential branches each consisting of the series connection of a second impedance, and a third N-channel MOS transistor, respectively, the sources of the third transistors.
  • N-channel transistor being interconnected to the drain of a fourth N-channel MOS transistor having its source connected to ground, the gate of the fourth N-channel transistor being connected to the gate of the second N-channel MOS transistor of the N-channel stage; output of the first differential comparator.
  • the figure 3 represents, in the form of a block diagram, a linear regulator 30 according to an embodiment of the present invention.
  • the regulator 30 comprises an output stage 31 consisting of the series connection, between a high power supply rail Vdd and an output terminal OUT, of two P-channel MOS transistors 32 and 33.
  • the output terminal OUT is intended for to be connected to a first power supply terminal of a load (LD) 1, a second power supply terminal of which is connected to a low supply rail or ground GND.
  • the linear regulator 30 also preferably includes a stabilization impedance 11, for example a capacitor C.
  • the regulation of the voltage Vout across the terminals of the load 1, that is to say on the output terminal OUT, is effected by modulating control signals of the gates G1 and G2 of the transistors 32 and 33, respectively, so as to modify their transconductance.
  • the control signals of the output stage 31 are produced by a control circuit 35.
  • the circuit 35 modulates the control signal of the gate G1 of the transistor 32 so as to regulate the voltage at the midpoint MID of the series connection. transistors 32 and 33 of the output stage 31. It also modulates the control signal of the gate G2 of the transistor 32 so as to regulate the output voltage Vout.
  • the circuit 35 includes an input / output stage (IN / OUT) 36 for generating the control signals and a reference stage (REF) 37.
  • the input / output stage 36 comprises four input terminals I1 , I2, I3 and I4 and two output terminals O1 and O2.
  • the terminal I1 receives a regulation voltage setpoint V1 of the output voltage Vout.
  • the terminal I2 receives the output voltage Vout.
  • the terminal I3 receives a regulation voltage setpoint V2 of the voltage at the MID midpoint.
  • the terminal I4 receives the voltage Vmid of the midpoint MID by a direct connection at this point.
  • the output terminals O1 and O2 are respectively connected to the gates G1, G2.
  • FIGS. 4A, 4B, 4C and 4D respectively illustrate, by timing diagrams, the variation as a function of time t of the regulation setpoint V1 of the output voltage Vout of regulator 30 of the figure 3 , the output voltage Vout, the regulation setpoint V2 of the mid-point voltage MID and the current voltage Vmid at the midpoint MID, that is to say the drain voltage of the transistor 32.
  • the output voltage Vout follows, from time t10, the first setpoint V1 until it stabilizes at time t11 at the nominal value Vref.
  • the voltage Vmid at the midpoint MID decreases in a controlled way from half of the high power supply (Vdd / 2) to the stable value (Vdd-Vref) / 2.
  • Vdd / 2 half of the high power supply
  • Vdd-Vref stable value
  • the first setpoint V1 is progressively reduced to zero along a ramp until a time t13.
  • the supply Vdd is then distributed symmetrically on the transistors 32 and 33.
  • the control circuit 35 ensures that any fluctuation of the power at the level of the load 1 results in a variation of the setpoints V1 and V2 so as to restore the rated speed and to distribute the power variation symmetrically on the two power transistors 32 and 33.
  • the control circuit 35 ensures that neither of the two transistors 32 and / or 33 is confronted with an excessive drain / source voltage.
  • ramps of initiation and extinction of respective slope different. More particularly, there is shown a faster extinction (t12-t13) than the boot (t10-t11).
  • the slope of the ramps depends on the technical performance of the circuits and in particular the capacity of the control circuit 35 to follow, transform and transmit, the variation of the first setpoint V1. Slopes may be faster or slower than represented. In addition, they may be symmetrical or have an asymmetry inverse to that shown, that is to say that the boot can be faster than extinction.
  • the figure 5 illustrates, schematically and partially, the structure of an embodiment of the input / output stage 36 of a control circuit 35 of an output stage 31 of a regulator 30 according to the present invention.
  • the input / output circuit 36 with four inputs and two outputs is a differential comparator. More particularly, the circuit 36 consists of the combination of a first differential comparator 50 and a second differential comparator 51 interlaced in the following manner.
  • the first comparator 50 delimited by a dotted frame in figure 5 , is intended to regulate the output voltage Vout from the first setpoint V1.
  • the comparator 50 therefore has a structure similar to that of a comparator known differential such as comparator 3 described in connection with the figure 1 .
  • the structure of the comparator 50 is described below using the same references as in figure 1 .
  • the comparator 50 comprises an input / output stage 4 and an output stage 5.
  • the stage 4 comprises two differential branches each comprising a P-channel MOS transistor 61, 62 connected in series with an N-channel MOS transistor 63,
  • the sources of transistors 61 and 62 are connected to an output terminal of a current source 60 having an input terminal connected to the high power supply Vdd.
  • the sources of transistors 63 and 64 are connected to the low GND supply.
  • the gates of transistors 63 and 64 are interconnected.
  • the gate of transistor 61 constitutes terminal I1 and receives setpoint V1.
  • the gate of the transistor 63 is connected to its drain, that is to say also to the drain of the transistor 61.
  • the gate of the transistor 62 constitutes the terminal I2 and receives the current voltage Vout across the load 1 by a connection to the output terminal OUT of the controller.
  • the connection point 65 of the drains of the transistors 62 and 64 constitutes the output of the input / output stage 4 of the comparator 50.
  • the output stage 5 consists of the series connection, between the high power supply Vdd and the ground GND, of an impedance 9, preferably resistive (R), and an N-channel MOS transistor 10.
  • the point of connection of the impedance 9 and the transistor 10 constitutes the output terminal 02 providing the control signal of the gate G2 of the transistor 33.
  • the gate of the transistor 10 is connected to the midpoint 65 of the differential branch 62-64 of the entrance floor 4.
  • the second differential comparator 51 is intended to control the regulation of the voltage at the MID point. It supplies on the output terminal 01 the control signal of the gate G1.
  • the second comparator 51 comprises two symmetrical differential branches each consisting of the series connection of an impedance 52, 53, preferably resistive, and a N-channel MOS transistor 54, 55, respectively.
  • the sources of transistors 54 and 55 are connected to the drain of an N-channel MOS transistor 56 whose source is connected to ground GND.
  • the gate of the transistor 56 is connected to the output 65 of the input / output stage 4 and to the gate of the transistor 10 of the output stage 5 of the first differential comparator 50. Therefore, the operating point of the second The differential comparator 51 depends on that of the output stage 5 of the first differential comparator 50.
  • the gate G2 of the transistor 33 supplied by the first comparator 50.
  • the transistor 56 will be completely on and allow a control of the gate G1 own to limit the voltage Vmid at half (Vdd / 2) of the high feed, as has been described previously in relation to the figure 4 .
  • the gates of the transistors 54 and 55 constitute, respectively, the terminals I3 and I4 for applying the voltages V2 and Vmid.
  • the figure 6 represents, schematically and partially, an embodiment of a generator 37 of the instructions V1 and V2.
  • the reference circuit 37 is, according to an embodiment of the present invention, a resistive voltage divider.
  • the resistive divider comprises the series connection between the high supply rails Vdd and low GND of three successive resistors 71, 72 and 73.
  • the connection point 74 of the resistors 72 and 73 is the output terminal of a differential comparator 75 two inputs and one output, for example similar to the comparator 3 of the figure 1 .
  • the non-inverting input terminal of the comparator 75 receives the regulation setpoint Vreg of the output voltage Vout of the regulator 30, for example, by a connection to the source 38.
  • the inverting input terminal of the comparator 75 is connected to the output terminal 74. Thus, it copies to the terminals of the resistor 73 the first set point V1.
  • resistors 71 and 72 of the same values, the midpoint of these two resistors is controlled linearly by the comparator 75 to the desired value V2 of the half-sum of the supply voltage and the first setpoint V1.
  • the present invention advantageously provides a linear power regulator fully achievable by a low voltage standard MOS die and small dimensions. Indeed, the replacement of the high voltage MOS transistor known regulators by two low voltage transistors reduces the integration surface. In addition, the surface increase of the control portion relative to the control circuit of a known regulator is negligible compared to the surface gain associated with the change of power switch.
  • the linear regulator according to the present invention has a lower voltage drop than known regulators.
  • the high supply voltage Vdd is from 3.3 to 5.5 volts
  • each transistor 32 and 33 of the output stage 31 of the linear regulator 30 of the present invention is a transistor Standard MOS clean to hold a drain / source voltage of about 2.5 volts. The regulator's waste voltage is then reduced to values of the order of 200 mV.
  • the present invention is susceptible of various variations and modifications which will be apparent to those skilled in the art.
  • the capacitor C (impedance 11) for stabilizing the output voltage Vout has been described as being functionally part of the linear regulator 30.
  • the capacitance value of the capacitor C is relatively high and varies in depending on the application, that is to say the load 1.
  • the capacitor C is therefore preferably made outside an integrated circuit chip comprising the entire regulator 30, and is mounted directly in parallel on the load 1.
  • the skilled person will modify the characteristics of the various components to the die used.

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Description

La présente invention concerne de façon générale la régulation d'une tension aux bornes d'une charge. Plus particulièrement, la présente invention concerne une telle régulation effectuée de façon linéaire. Le document EP1061428 décrit un régulateur linéal. La figure 1 illustre, de façon schématique et partielle, un exemple classique de régulateur linéaire d'une tension Vout aux bornes d'une charge (LD) 1. Le régulateur comporte un transistor MOS à canal P 2 dont la source est connectée à un rail d'alimentation de tension haute Vdd et dont le drain constitue la borne de sortie OUT du régulateur. La charge 1 est connectée entre la borne OUT et un rail d'alimentation basse ou de tension de référence ou masse GND. Le transistor 2 fonctionne en régime linéaire, c'est-à-dire que l'on utilise sa transconductance pour faire varier son courant de sortie en fonction de la tension de commande appliquée sur sa grille G. La tension de commande de la grille G est régulée en fonction de la tension Vout aux bornes de la charge 1. La régulation est effectuée par un comparateur différentiel 3 comportant un étage d'entrée/sortie 4 et un étage de sortie 5. L'étage d'entrée/sortie 4 comprend deux branches différentielles comportant chacune un transistor MOS à canal P 61, 62 connecté en série avec un transistor MOS à canal N 63, 64. Les sources des transistors 61 et 62 sont connectées à une borne de sortie d'une source de courant 60 dont une borne d'entrée est reliée à l'alimentation haute Vdd. Les sources des transistors 63 et 64 sont connectées à l'alimentation basse GND. Les grilles des transistors 63 et 64 sont interconnectées. Une branche 61-63 constitue une branche d'entrée, alors que l'autre branche 62-64 constitue une branche de sortie. Le transistor 61 de la branche d'entrée reçoit une consigne de tension continue constante Vreg fournie par un générateur de tension 8, connecté entre la grille du transistor 61 et la masse GND. La grille du transistor 63 est connectée à son drain, c'est-à-dire également au drain du transistor 61. La grille du transistor 63 reçoit la tension Vout aux bornes de la charge 1 par une connexion à la borne de sortie OUT du régulateur, éventuellement à une prise intermédiaire d'un pont de résistances. Le point de connexion 65 des drains des transistors 62 et 64 constitue la sortie de l'étage d'entrée/sortie 4 du comparateur 3.The present invention generally relates to the regulation of a voltage across a load. More particularly, the present invention relates to such regulation carried out linearly. The document EP1061428 describes a linear regulator. The figure 1 illustrates, schematically and partially, a conventional example of a linear regulator of a voltage Vout across a load (LD) 1. The regulator comprises a P-channel MOS transistor 2 whose source is connected to a rail of high voltage supply Vdd and whose drain constitutes the output terminal OUT of the regulator. The load 1 is connected between the OUT terminal and a low supply rail or a reference voltage or ground GND. The transistor 2 operates in linear mode, that is to say that its transconductance is used to vary its output current as a function of the control voltage applied to its gate G. The control voltage of the gate G is regulated according to the voltage Vout across the load 1. The regulation is performed by a differential comparator 3 having an input / output stage 4 and an output stage 5. The input / output stage 4 comprises two differential branches each comprising a P-channel MOS transistor 61, 62 connected in series with an N-channel MOS transistor 63, 64. The sources of the transistors 61 and 62 are connected to an output terminal of a current source 60 having an input terminal connected to the high power supply Vdd. The sources of transistors 63 and 64 are connected to the low GND supply. The gates of transistors 63 and 64 are interconnected. One branch 61-63 constitutes an input branch, while the other branch 62-64 constitutes an output branch. The transistor 61 of the input branch receives a constant DC voltage setpoint Vreg supplied by a voltage generator 8 connected between the gate of the transistor 61 and the ground GND. The gate of the transistor 63 is connected to its drain, that is to say also to the drain of the transistor 61. The gate of the transistor 63 receives the voltage Vout across the load 1 by a connection to the output terminal OUT of regulator, possibly at an intermediate point of a resistance bridge. The connection point 65 of the drains of the transistors 62 and 64 constitutes the output of the input / output stage 4 of the comparator 3.

L'étage de sortie 5 est constitué de la connexion en série, entre les alimentations haute Vdd et basse GND, d'une impédance 9 généralement résistive (R) et d'un transistor MOS à canal N 10. Le point de connexion de l'impédance 9 et du transistor 10 constitue la borne de sortie du comparateur différentiel 3 reliée à la grille G du transistor de régulation 2. La grille du transistor 10 est connectée au point 65 de la branche différentielle d'entrée/sortie 62-64.The output stage 5 consists of the series connection, between the high Vdd and low GND supplies, of a generally resistive impedance (R) and of an N-channel MOS transistor 10. The connection point of the impedance 9 and transistor 10 constitutes the output terminal of the differential comparator 3 connected to the gate G of the regulation transistor 2. The gate of the transistor 10 is connected to the point 65 of the differential input / output branch 62-64.

Le régulateur comporte en outre une impédance (C) 11, généralement capacitive, destinée à stabiliser la tension de sortie Vout.The regulator further comprises an impedance (C) 11, generally capacitive, for stabilizing the output voltage Vout.

Les figures 2A-2C illustrent, par des chronogrammes, un exemple de variation en fonction du temps t de la consigne de tension Vreg aux bornes de la source 8, de la tension de sortie Vout aux bornes de la charge 1, et de la tension Vds entre les bornes de drain et de source du transistor 2. Lors du démarrage du circuit, à un instant t0, on valide le générateur de tension constante continue 8 de façon qu'il délivre une consigne de régulation nominale non nulle stable Vref jusqu'à un instant t1 d'extinction du circuit. Le comparateur différentiel 3 force alors, comme l'illustre la figure 2B, la tension de sortie Vout à suivre la tension de régulation Vreg et à s'aligner sur le niveau de référence Vref. La tension Vout est ensuite régulée de façon stable au niveau Vref par la commande de grille jusqu'à l'instant t1 d'extinction ou de mise en veille du circuit. Cette régulation est effectuée par une commande en mode linéaire du transistor 2 qui est utilisé comme une transconductance variable dont le courant de sortie dépend de la tension de commande sur la grille G.The Figures 2A-2C illustrate, by timing diagrams, an example of variation as a function of the time t of the voltage setpoint Vreg at the terminals of the source 8, the output voltage Vout across the load 1, and the voltage Vds between the terminals of drain and source of the transistor 2. When starting the circuit, at a time t0, the constant constant voltage generator 8 is enabled so that it delivers a stable non-zero nominal regulation setpoint Vref up to a time t1 circuit extinction. The differential comparator 3 then forces, as illustrated by Figure 2B , the output voltage Vout to follow the regulation voltage Vreg and to align with the reference level Vref. The voltage Vout is then stably regulated at the Vref level by the gate control until the instant t1 of switching off or putting the circuit on standby. This regulation is performed by a linear control of transistor 2 which is used as a variable transconductance whose output current depends on the control voltage on gate G.

On considère plus particulièrement dans la présente description les applications dans lesquelles la charge 1 doit être alimentée à un niveau de tension de l'ordre de 3,3 à 5,5 volts. Une telle valeur est relativement élevée par rapport à la tension maximale de l'ordre de 2,4 à 2,8 volts que peuvent tenir les composants (en particulier le transistor MOS 2) utilisés dans des filières technologiques d'intégration standard. Toutefois, lors des périodes d'extinction de la charge 1, le transistor MOS 2 doit tenir la tension Vdd à ses bornes.Applications in which the load 1 is to be supplied at a voltage level of the order of 3.3 to 5.5 volts are more particularly considered in the present description. Such a value is relatively high compared to the maximum voltage of the order of 2.4 to 2.8 volts that can hold the components (in particular the MOS transistor 2) used in standard integration technology channels. However, during the periods of extinction of the load 1, the MOS transistor 2 must hold the voltage Vdd at its terminals.

En effet, comme l'illustre la figure 2C, lors des phases d'extinction de la charge 1 (Vreg=0, figure 2A), c'est-à-dire avant l'instant de démarrage t0 et après l'instant d'extinction t1, le transistor 2 de commande de la charge 1 doit supporter, entre ses bornes de drain et de source, une différence de potentiels Vds égale à l'amplitude d'alimentation Vdd-GND. Par contre, pendant le fonctionnement de la charge 1 (Vreg=Vref), la tension Vds est réduite à la différence entre l'alimentation haute Vdd et la tension Vout aux bornes de la charge 1, c'est-à-dire la valeur de régulation nominale Vref.Indeed, as illustrated by Figure 2C during the phases of extinction of the charge 1 (Vreg = 0, Figure 2A ), that is to say before the start time t0 and after the extinction time t1, the load control transistor 2 must withstand, between its drain and source terminals, a difference of potential Vds equal to the supply amplitude Vdd-GND. On the other hand, during the operation of the load 1 (Vreg = Vref), the voltage Vds is reduced to the difference between the high power supply Vdd and the voltage Vout at the terminals of the load 1, that is to say the value nominal regulation Vref.

Pour permettre la tenue en tension du transistor 2 pendant les phases d'extinction, on a modifié la filière de fabrication standard 2,5 volts pour insérer des transistors MOS susceptibles de tenir une tension maximale supérieure à 5 volts entre leur drain et leur source. On a notamment modifié les masques de définition du transistor de régulation 2 par rapport aux transistors voisins, de façon à accroître considérablement l'épaisseur d'une partie d'un isolant de grille proche d'une des régions de drain/source et à augmenter la surface de cette même région de drain/source. Mais alors, la capacité parasite de grille du transistor 2 est accrue, et sa transconductance est réduite. Or, pour permettre une commande linéaire du transistor 2 telle que décrite précédemment avec des niveaux de commande suffisamment faibles, il faut que la transconductance soit relativement élevée. Pour l'augmenter, on doit alors accroître encore plus la surface d'intégration du transistor 2.To enable the voltage resistance of the transistor 2 during the extinction phases, the standard 2.5-volt manufacturing die has been modified to insert MOS transistors capable of holding a maximum voltage greater than 5 volts between their drain and their source. In particular, the definition masks of the regulation transistor 2 with respect to to neighboring transistors, so as to substantially increase the thickness of a portion of a gate insulator near one of the drain / source regions and to increase the area of the same drain / source region. But then, the parasitic gate capacitance of transistor 2 is increased, and its transconductance is reduced. However, to allow a linear control of the transistor 2 as described above with sufficiently low control levels, it is necessary that the transconductance is relatively high. To increase it, it is then necessary to further increase the integration surface of the transistor 2.

L'accroissement de surface entraîne qu'il faut parfois intégrer ces commutateurs de commande en dehors de la puce dans laquelle est réalisé le reste du circuit de puissance constituant le régulateur de tension. En outre, il faut alors tenir compte d'une capacité parasite relativement élevée par rapport aux capacités parasites des autres éléments du circuit. De plus, la tension de déchet, c'est-à-dire l'écart entre la consigne de régulation Vref et la tension de sortie Vout peut difficilement être réduite à moins de 500 mV. Ceci est particulièrement désavantageux dans des dispositifs portables tels que des agendas électroniques, des téléphones satellites, des ordinateurs portables ou des organiseurs de poche. En effet, obtenir le niveau de sortie nominal nécessaire au bon fonctionnement de la charge, impose le recours à une consigne d'un niveau plus élevé. Ceci accroît l'encombrement du circuit et/ou, plus généralement, provoque alors une décharge accélérée des batteries alimentant l'ensemble du circuit et permettant de fournir la consigne de référence Vref. Dans ce dernier cas, il faut effectuer de fréquentes recharges des batteries du dispositif, ce qui est en contradiction avec leur caractère portable.Surface increase means that these control switches must sometimes be integrated outside the chip in which the rest of the power circuit constituting the voltage regulator is made. In addition, it is then necessary to take into account a relatively high parasitic capacitance compared to the parasitic capacitances of the other elements of the circuit. In addition, the waste voltage, that is to say the difference between the regulation setpoint Vref and the output voltage Vout can hardly be reduced to less than 500 mV. This is particularly disadvantageous in portable devices such as electronic diaries, satellite phones, laptops or handheld organizers. Indeed, to obtain the nominal output level necessary for the proper operation of the load, requires the use of a set of higher level. This increases the size of the circuit and / or, more generally, then causes an accelerated discharge of the batteries supplying the entire circuit and to provide the reference setpoint Vref. In the latter case, it is necessary to frequently recharge the batteries of the device, which is in contradiction with their wearable nature.

Par ailleurs, les modifications de la filière de fabrication nécessaires à la formation du transistor MOS de régulation sont particulièrement gênantes en termes de complication du procédé global et de coût.Moreover, the changes in the manufacturing process necessary for the formation of the regulating MOS transistor are particularly troublesome in terms of the complexity of the overall process and cost.

Pour pallier ces problèmes, on a proposé d'utiliser un transistor de régulation de type bipolaire haute tension, qui présente l'avantage de demander une moindre surface d'intégration par rapport au MOS spécifique, notamment car il peut plus facilement être intégré de façon verticale dans un substrat de silicium. Toutefois, le recours à un transistor bipolaire pose de nombreux problèmes.To overcome these problems, it has been proposed to use a high-voltage bipolar type regulating transistor, which has the advantage of requiring a smaller integration area relative to the specific MOS, in particular because it can more easily be integrated in a vertical in a silicon substrate. However, the use of a bipolar transistor poses many problems.

Notamment, il faut recourir à une filière BiCMOS qui est plus complexe que la filière MOS. Il faut également prévoir un circuit spécifique pour fixer le point de fonctionnement du transistor bipolaire, et notamment prévoir une limitation du courant de base. En outre, un transistor de régulation bipolaire conduit à des tensions de déchet plus élevées qu'un transistor MOS avec une plage de linéarité plus restreinte. Ceci est particulièrement désavantageux dans le cas de dispositifs de type portable pour lesquels il est souhaitable de réduire le plus possible la tension de déchet, c'est-à-dire de la rendre, de préférence, inférieure à 200 mV.In particular, it is necessary to resort to a BiCMOS sector which is more complex than the MOS sector. It is also necessary to provide a specific circuit for setting the operating point of the bipolar transistor, and in particular to provide a limitation of the base current. In addition, a bipolar control transistor leads to higher waste voltages than a MOS transistor with a smaller linearity range. This is particularly disadvantageous in the case of portable type devices for which it is desirable to minimize the waste voltage, i.e. to make it, preferably, less than 200 mV.

La présente invention vise à proposer un régulateur linéaire qui pallie les inconvénients des circuits connus.The present invention aims to provide a linear regulator that overcomes the disadvantages of known circuits.

La présente invention vise en particulier à proposer un régulateur linéaire qui présente une tension de déchet réduite.The present invention aims in particular to provide a linear regulator which has a reduced waste voltage.

La présente invention vise à proposer un tel régulateur qui peut être fabriqué à l'aide d'une filière MOS standard.The present invention aims to provide such a regulator that can be manufactured using a standard MOS die.

Pour atteindre ces objets et d'autres, la présente invention prévoit un régulateur linéaire comportant un étage de sortie comprenant des premier et second transistors MOS à canal P, connectés en série entre une première borne d'alimentation continue et une borne de sortie fournissant une tension de sortie régulée, et un circuit de commande des premier et second transistors propre à fournir des premier et second signaux de commande en fonction de la tension de sortie et de la tension au point milieu de la connexion en série.To achieve these and other objects, the present invention provides a linear regulator having an output stage comprising first and second P-channel MOS transistors connected in series between a first DC power terminal and an output terminal providing an output terminal. regulated output voltage, and a control circuit of the first and second transistors capable of providing first and second control signals as a function of the output voltage and the voltage at the midpoint of the series connection.

Selon un mode de réalisation de la présente invention, le circuit de commande comprend un circuit d'entrée/sortie et un circuit de référence, le circuit d'entrée/sortie comportant une première entrée, recevant une première consigne de tension fournie par ledit circuit de référence ; une deuxième entrée, connectée à ladite borne de sortie ; une troisième entrée recevant une seconde consigne de tension fournie par ledit circuit de référence ; une quatrième entrée connectée audit point milieu ; une première sortie connectée à la grille du premier transistor ; et une deuxième sortie connectée à la grille du deuxième transistor.According to an embodiment of the present invention, the control circuit comprises an input / output circuit and a reference circuit, the input / output circuit having a first input, receiving a first voltage setpoint provided by said reference circuit; a second input, connected to said output terminal; a third input receiving a second voltage setpoint supplied by said reference circuit; a fourth input connected to said midpoint; a first output connected to the gate of the first transistor; and a second output connected to the gate of the second transistor.

Selon un mode de réalisation de la présente invention, le circuit d'entrée/sortie est un double comparateur différentiel à quatre entrées et deux sorties.According to an embodiment of the present invention, the input / output circuit is a dual differential comparator with four inputs and two outputs.

Selon un mode de réalisation de la présente invention, le circuit d'entrée/sortie comporte des premier et second comparateurs différentiels à deux entrées et deux sorties, les bornes d'entrée du premier comparateur différentiel étant les première et deuxième bornes d'entrée du circuit d'entrée/sortie et sa sortie étant la deuxième sortie dudit circuit d'entrée/sortie ; et les bornes d'entrée du second comparateur différentiel étant les troisième et quatrième bornes d'entrée dudit circuit d'entrée/sortie et sa sortie en étant la première sortie.According to an embodiment of the present invention, the input / output circuit comprises first and second differential comparators with two inputs and two outputs, the input terminals of the first differential comparator being the first and second input terminals of the input comparator. an input / output circuit and its output being the second output of said input / output circuit; and the input terminals of the second differential comparator being the third and fourth input terminals of said input / output circuit and its output being the first output.

Selon un mode de réalisation de la présente invention, le premier comparateur différentiel comporte un étage d'entrée/sortie et un étage de sortie, ledit étage d'entrée/sortie comportant deux branches différentielles dont chacune comprend un transistor MOS à canal P connecté en série avec un premier transistor MOS à canal N, les sources des transistors à canal P étant interconnectées à une borne de sortie d'une source de courant dont une borne d'entrée est reliée à ladite borne d'alimentation continue, les sources des premiers transistors à canal N étant interconnectées à une borne de masse, les grilles desdits premiers transistors MOS à canal N étant interconnectées, les grilles des transistors à canal P constituant les première et deuxième bornes d'entrée du circuit d'entrée/sortie, la grille du premier transistor MOS à canal N de la branche comportant la première entrée étant connectée à son drain, le point milieu de connexion des drains des transistors complémentaires de l'autre branche étant relié à la grille d'un deuxième transistor MOS à canal N connecté, dans ledit étage de sortie, en série entre les bornes d'alimentation, avec une première impédance, le point milieu de la connexion en série de ladite première impédance et du deuxième transistor constituant la borne de sortie dudit premier comparateur différentiel.According to one embodiment of the present invention, the first differential comparator comprises an input / output stage and an output stage, said input / output stage comprising two differential branches, each of which comprises a P-channel MOS transistor connected in parallel. series with a first N-channel MOS transistor, the sources of the P-channel transistors being interconnected to an output terminal of a current source whose input terminal is connected to said DC power terminal, the sources of the first N-channel transistors being interconnected to a ground terminal, the gates of said first N-channel MOS transistors being interconnected, the gates of the P-channel transistors constituting the first and second input terminals of the input / output circuit, the gate of the first N-channel MOS transistor of the branch having the first input being connected to its drain, the intermediate connection point of the drains of the complementary transistors of the other branch being connected to the gate of a second N-channel MOS transistor connected in said output stage, in series between the power supply terminals, with a first impedance, the midpoint of the series connection of said first impedance and the second transistor constituting the output terminal of said first differential comparator.

Selon un mode de réalisation de la présente invention, le second comparateur différentiel comporte deux branches différentielles symétriques constituées chacune de la connexion en série d'une seconde impédance, et d'un troisième transistor MOS à canal N, respectivement, les sources des troisièmes transistors à canal N étant interconnectées au drain d'un quatrième transistor MOS à canal N dont la source est connectée à la masse, la grille du quatrième transistor à canal N étant connectée à la grille du deuxième transistor MOS à canal N de l'étage de sortie du premier comparateur différentiel.According to one embodiment of the present invention, the second differential comparator comprises two symmetrical differential branches each consisting of the series connection of a second impedance, and a third N-channel MOS transistor, respectively, the sources of the third transistors. N-channel transistor being interconnected to the drain of a fourth N-channel MOS transistor having its source connected to ground, the gate of the fourth N-channel transistor being connected to the gate of the second N-channel MOS transistor of the N-channel stage; output of the first differential comparator.

Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles :

  • la figure 1, qui a été décrite précédemment, représente de façon partielle et schématique la structure d'un régulateur linéaire connu associé à une charge ;
  • les figures 2A à 2C, qui ont été décrites précédemment, sont des chronogrammes illustrant le fonctionnement du régulateur de la figure 1 ;
  • la figure 3 représente, sous forme d'un schéma-blocs partiel et schématique, un régulateur linéaire selon un mode de réalisation de la présente invention associé à une charge ;
  • la figure 4A est un chronogramme illustrant une première consigne de tension du régulateur de la figure 3 ;
  • la figure 4B est un chronogramme illustrant la tension de sortie du régulateur de la figure 3 ;
  • la figure 4C est un chronogramme illustrant une deuxième consigne de tension du régulateur de la figure 3 ;
  • la figure 4D est un chronogramme illustrant une tension aux bornes d'un composant d'un étage de sortie du régulateur de la figure 3 ;
  • la figure 5 représente, partiellement et schématiquement, un mode de réalisation d'un étage d'entrée/sortie du régulateur de la figure 3 ; et
  • la figure 6 représente un mode de réalisation d'un générateur de première et deuxième consignes de tension utilisable dans le régulateur de la figure 3.
These and other objects, features, and advantages of the present invention will be set forth in detail in the following description of particular embodiments given as a non-limiting example in connection with the accompanying drawings in which:
  • the figure 1 , which has been previously described, partially and schematically represents the structure of a known linear regulator associated with a load;
  • the FIGS. 2A to 2C , which have been described previously, are timing diagrams illustrating the operation of the regulator of the figure 1 ;
  • the figure 3 represents, in the form of a partial and schematic block diagram, a linear regulator according to an embodiment of the present invention associated with a load;
  • the Figure 4A is a timing diagram illustrating a first voltage setpoint of the regulator of the figure 3 ;
  • the Figure 4B is a timing diagram illustrating the output voltage of the regulator of the figure 3 ;
  • the figure 4C is a timing diagram illustrating a second voltage setpoint of the regulator of the figure 3 ;
  • the figure 4D is a timing diagram illustrating a voltage across a component of an output stage of the regulator of the figure 3 ;
  • the figure 5 represents, partially and schematically, an embodiment of an input / output stage of the regulator of the figure 3 ; and
  • the figure 6 represents an embodiment of a generator of first and second voltage setpoints usable in the regulator of the figure 3 .

Par souci de clarté, de mêmes éléments ont été désignés aux différentes figures par de mêmes références. En outre, seuls les éléments qui sont nécessaires à la compréhension de la présente invention ont été représentés. Ainsi, d'éventuels circuits de validation des générateurs de tension de référence ne sont ni représentés, ni décrits.For the sake of clarity, the same elements have been designated in the various figures by the same references. In addition, only the elements that are necessary for the understanding of the present invention have been shown. Thus, any validation circuits of the reference voltage generators are neither represented nor described.

La figure 3 représente, sous forme d'un schéma-blocs, un régulateur linéaire 30 selon un mode de réalisation de la présente invention. Le régulateur 30 comporte un étage de sortie 31 constitué de la connexion en série, entre un rail d'alimentation haute Vdd et une borne de sortie OUT, de deux transistors MOS à canal P 32 et 33. La borne de sortie OUT est destinée à être connectée à une première borne d'alimentation d'une charge (LD) 1 dont une deuxième borne d'alimentation est reliée à un rail d'alimentation basse ou masse GND. Pour stabiliser rapidement la tension de sortie régulée, le régulateur linéaire 30 comprend également, de préférence, une impédance de stabilisation 11, par exemple un condensateur C.The figure 3 represents, in the form of a block diagram, a linear regulator 30 according to an embodiment of the present invention. The regulator 30 comprises an output stage 31 consisting of the series connection, between a high power supply rail Vdd and an output terminal OUT, of two P-channel MOS transistors 32 and 33. The output terminal OUT is intended for to be connected to a first power supply terminal of a load (LD) 1, a second power supply terminal of which is connected to a low supply rail or ground GND. To quickly stabilize the regulated output voltage, the linear regulator 30 also preferably includes a stabilization impedance 11, for example a capacitor C.

La régulation de la tension Vout aux bornes de la charge 1, c'est-à-dire sur la borne de sortie OUT, est effectuée en modulant des signaux de commande des grilles G1 et G2 des transistors 32 et 33, respectivement, de façon à modifier leur transconductance.The regulation of the voltage Vout across the terminals of the load 1, that is to say on the output terminal OUT, is effected by modulating control signals of the gates G1 and G2 of the transistors 32 and 33, respectively, so as to modify their transconductance.

Les signaux de commande de l'étage de sortie 31 sont produits par un circuit de commande 35. Le circuit 35 module le signal de commande de la grille G1 du transistor 32 de façon à réguler la tension au point milieu MID de la connexion en série des transistors 32 et 33 de l'étage de sortie 31. Il module également le signal de commande de la grille G2 du transistor 32 de façon à réguler la tension de sortie Vout. Le circuit 35 comporte un étage d'entrée/sortie (IN/OUT) 36 destiné à produire les signaux de commande et un étage de référence (REF) 37. L'étage d'entrée/sortie 36 comprend quatre bornes d'entrée I1, I2, I3 et I4 et deux bornes de sortie O1 et O2. La borne I1 reçoit une consigne de tension de régulation V1 de la tension de sortie Vout. La borne I2 reçoit la tension de sortie Vout. La borne I3 reçoit une consigne de tension de régulation V2 de la tension au point milieu MID. La borne I4 reçoit la tension Vmid du point milieu MID par une connexion directe à ce point. Les bornes de sortie O1 et O2 sont respectivement connectées aux grilles G1, G2.The control signals of the output stage 31 are produced by a control circuit 35. The circuit 35 modulates the control signal of the gate G1 of the transistor 32 so as to regulate the voltage at the midpoint MID of the series connection. transistors 32 and 33 of the output stage 31. It also modulates the control signal of the gate G2 of the transistor 32 so as to regulate the output voltage Vout. The circuit 35 includes an input / output stage (IN / OUT) 36 for generating the control signals and a reference stage (REF) 37. The input / output stage 36 comprises four input terminals I1 , I2, I3 and I4 and two output terminals O1 and O2. The terminal I1 receives a regulation voltage setpoint V1 of the output voltage Vout. The terminal I2 receives the output voltage Vout. The terminal I3 receives a regulation voltage setpoint V2 of the voltage at the MID midpoint. The terminal I4 receives the voltage Vmid of the midpoint MID by a direct connection at this point. The output terminals O1 and O2 are respectively connected to the gates G1, G2.

Les consignes de régulation V1 et V2 reçues sur les bornes I1 et I3 de l'étage 36, respectivement, sont fournies par le circuit de référence (REF) 37 à partir d'une source variable 38 de tension continue (Vreg). Plus particulièrement, pour réguler le point milieu MID de façon à garantir une équipartition des tensions aux bornes de chacun des deux transistors en série 32 et 33, la consigne de régulation V2 du point milieu MID est égale à la moitié de la somme de la tension d'alimentation haute Vdd et de la première consigne de régulation V1 (V2=(Vdd+V1)/2). La source 38 fournit donc, de préférence, directement la première consigne V1 (Vreg=V1) à partir de laquelle le circuit 37 fournit la seconde consigne V2 selon la relation précédente.The regulation setpoints V1 and V2 received on the terminals I1 and I3 of the stage 36, respectively, are provided by the reference circuit (REF) 37 from a variable voltage source 38 (Vreg). More particularly, in order to regulate the MID midpoint so as to guarantee an equipartition of the voltages across each of the two series transistors 32 and 33, the regulation setpoint V2 of the MID midpoint is equal to half the sum of the voltage. high power supply Vdd and the first regulation setpoint V1 (V2 = (Vdd + V1) / 2). The source 38 therefore preferably provides directly the first setpoint V1 (Vreg = V1) from which the circuit 37 supplies the second setpoint V2 according to the preceding relation.

Les figures 4A, 4B, 4C et 4D illustrent respectivement, par des chronogrammes, la variation en fonction du temps t de la consigne de régulation V1 de la tension de sortie Vout du régulateur 30 de la figure 3, de la tension de sortie Vout, de la consigne de régulation V2 de la tension du point milieu MID et de la tension courante Vmid au point milieu MID, c'est-à-dire la tension de drain du transistor 32.The FIGS. 4A, 4B, 4C and 4D respectively illustrate, by timing diagrams, the variation as a function of time t of the regulation setpoint V1 of the output voltage Vout of regulator 30 of the figure 3 , the output voltage Vout, the regulation setpoint V2 of the mid-point voltage MID and the current voltage Vmid at the midpoint MID, that is to say the drain voltage of the transistor 32.

Lors d'une mise en route du régulateur 30, à un instant t10, le circuit de référence 37 est validé par une mise en route de la source 38 et produit les consignes de régulation V1 et V2. Comme l'illustrent les figures 4A et 4C, les consignes de régulation V1 et V2 sont, pendant une phase d'amorçage (instants t10 à t11), des rampes parallèles. En effet, comme cela a été indiqué précédemment, pour assurer un équilibre de répartition des tensions aux bornes des transistors 32 et 33, il faut assurer qu'à tout instant le potentiel au point milieu MID est égal à la moitié de la différence entre la tension d'alimentation haute Vdd et la tension Vout aux bornes de la charge 1 (Vmid= (Vdd-Vout)/2). Pour ce faire, il faut appliquer une consigne égale à la demi-somme de la tension d'alimentation haute Vdd et de la première consigne V1. Lors de la variation de la consigne V1 d'une valeur nulle à une consigne nominale Vref, le circuit de commande 35 doit pouvoir assurer une telle condition. Pour permettre un suivi linéaire, il est alors préférable que la consigne V1 varie lentement plutôt que brutalement comme dans le cas d'une consigne standard (figure 2A).When starting the regulator 30, at a time t10, the reference circuit 37 is enabled by a start of the source 38 and produces the regulation setpoints V1 and V2. As illustrated by Figures 4A and 4C , the regulation setpoints V1 and V2 are, during a priming phase (times t10 to t11), parallel ramps. Indeed, as previously indicated, to ensure a balance of the distribution of the voltages across the transistors 32 and 33, it must be ensured that at all times the potential at the MID midpoint is equal to half the difference between the high supply voltage Vdd and the voltage Vout across the load 1 (Vmid = (Vdd-Vout) / 2). To do this, it is necessary to apply a setpoint equal to the half-sum of the high supply voltage Vdd and the first setpoint V1. When the setpoint V1 is changed from a zero value to a nominal setpoint Vref, the control circuit 35 must be able to provide such a condition. To allow a linear tracking, it is then preferable that the setpoint V1 varies slowly rather than abruptly as in the case of a standard setpoint ( Figure 2A ).

Comme l'illustre la figure 4B, pendant la phase d'amorçage, la tension de sortie Vout suit, à partir de l'instant t10, la première consigne V1 jusqu'à se stabiliser à l'instant t11 à la valeur nominale Vref. La tension Vmid au point milieu MID, illustrée en figure 4D, décroît par contre de façon contrôlée de la moitié de l'alimentation haute (Vdd/2) jusqu'à la valeur stable (Vdd-Vref)/2. En fonctionnement nominal, entre les instants t11 et t12, les tensions de sortie Vout et du point milieu Vmid sont maintenues stables par des consignes V1 et V2 stables. Lors d'une commande d'extinction de la charge 1 à un instant t12, pour permettre un suivi linéaire de la deuxième consigne V2, la première consigne V1 est progressivement ramenée à zéro selon une rampe jusqu'à un instant t13. L'alimentation Vdd se répartit alors symétriquement sur les transistors 32 et 33.As illustrated by Figure 4B during the priming phase, the output voltage Vout follows, from time t10, the first setpoint V1 until it stabilizes at time t11 at the nominal value Vref. The voltage Vmid at the midpoint MID, illustrated in figure 4D on the other hand, decreases in a controlled way from half of the high power supply (Vdd / 2) to the stable value (Vdd-Vref) / 2. In nominal operation, between instants t11 and t12, the output voltages Vout and the midpoint Vmid are kept stable by stable setpoints V1 and V2. During an extinguishing command of the load 1 at a time t12, to allow a linear follow-up of the second setpoint V2, the first setpoint V1 is progressively reduced to zero along a ramp until a time t13. The supply Vdd is then distributed symmetrically on the transistors 32 and 33.

En régime nominal (de t11 à t12), le circuit de commande 35 assure que toute fluctuation éventuelle de la puissance au niveau de la charge 1 se traduit par une variation des consignes V1 et V2 de façon à rétablir le régime nominal et à répartir la variation de puissance de façon symétrique sur les deux transistors de puissance 32 et 33. Ainsi, aucun des deux transistors 32 et/ou 33 ne se trouve confronté à une tension drain/source excessive.At nominal speed (from t11 to t12), the control circuit 35 ensures that any fluctuation of the power at the level of the load 1 results in a variation of the setpoints V1 and V2 so as to restore the rated speed and to distribute the power variation symmetrically on the two power transistors 32 and 33. Thus, neither of the two transistors 32 and / or 33 is confronted with an excessive drain / source voltage.

On a représenté en figure 4 des rampes d'amorçage et d'extinction de pente respective différente. Plus particulièrement, on a représenté une extinction plus rapide (t12-t13) que l'amorçage (t10-t11). En pratique, la pente des rampes dépend des performances techniques des circuits et notamment de la capacité du circuit de commande 35 à suivre, transformer et transmettre, la variation de la première consigne V1. Les pentes peuvent être plus rapides ou plus lentes que représentées. En outre, elles peuvent être symétriques ou présenter une asymétrie inverse de celle représentée, c'est-à-dire que l'amorçage peut être plus rapide que l'extinction.We have shown in figure 4 ramps of initiation and extinction of respective slope different. More particularly, there is shown a faster extinction (t12-t13) than the boot (t10-t11). In practice, the slope of the ramps depends on the technical performance of the circuits and in particular the capacity of the control circuit 35 to follow, transform and transmit, the variation of the first setpoint V1. Slopes may be faster or slower than represented. In addition, they may be symmetrical or have an asymmetry inverse to that shown, that is to say that the boot can be faster than extinction.

La figure 5 illustre, schématiquement et partiellement, la structure d'un mode de réalisation de l'étage d'entrée/sortie 36 d'un circuit de commande 35 d'un étage de sortie 31 d'un régulateur 30 selon la présente invention.The figure 5 illustrates, schematically and partially, the structure of an embodiment of the input / output stage 36 of a control circuit 35 of an output stage 31 of a regulator 30 according to the present invention.

Le circuit d'entrée/sortie 36 à quatre entrées et deux sorties est un comparateur différentiel. Plus particulièrement, le circuit 36 est constitué de l'association d'un premier comparateur différentiel 50 et d'un deuxième comparateur différentiel 51 entrelacés de la façon suivante.The input / output circuit 36 with four inputs and two outputs is a differential comparator. More particularly, the circuit 36 consists of the combination of a first differential comparator 50 and a second differential comparator 51 interlaced in the following manner.

Le premier comparateur 50, délimité par un cadre en pointillés en figure 5, est destiné à réguler la tension de sortie Vout à partir de la première consigne V1. Le comparateur 50 a donc une structure similaire à celle d'un comparateur différentiel connu tel que le comparateur 3 décrit en relation avec la figure 1. Par souci de clarté, la structure du comparateur 50 est décrite ci-après à l'aide des mêmes références qu'en figure 1.The first comparator 50, delimited by a dotted frame in figure 5 , is intended to regulate the output voltage Vout from the first setpoint V1. The comparator 50 therefore has a structure similar to that of a comparator known differential such as comparator 3 described in connection with the figure 1 . For the sake of clarity, the structure of the comparator 50 is described below using the same references as in figure 1 .

Le comparateur 50 comporte un étage d'entrée/sortie 4 et un étage de sortie 5. L'étage 4 comprend deux branches différentielles comportant chacune un transistor MOS à canal P 61, 62 connecté en série avec un transistor MOS à canal N 63, 64. Les sources des transistors 61 et 62 sont connectées à une borne de sortie d'une source de courant 60 dont une borne d'entrée est reliée à l'alimentation haute Vdd. Les sources des transistors 63 et 64 sont connectées à l'alimentation basse GND. Les grilles des transistors 63 et 64 sont interconnectées. La grille du transistor 61 constitue la borne I1 et reçoit la consigne V1. La grille du transistor 63 est connectée à son drain, c'est-à-dire également au drain du transistor 61. La grille du transistor 62 constitue la borne I2 et reçoit la tension courante Vout aux bornes de la charge 1 par une connexion à la borne de sortie OUT du régulateur. Le point de connexion 65 des drains des transistors 62 et 64 constitue la sortie de l'étage d'entrée/sortie 4 du comparateur 50.The comparator 50 comprises an input / output stage 4 and an output stage 5. The stage 4 comprises two differential branches each comprising a P-channel MOS transistor 61, 62 connected in series with an N-channel MOS transistor 63, The sources of transistors 61 and 62 are connected to an output terminal of a current source 60 having an input terminal connected to the high power supply Vdd. The sources of transistors 63 and 64 are connected to the low GND supply. The gates of transistors 63 and 64 are interconnected. The gate of transistor 61 constitutes terminal I1 and receives setpoint V1. The gate of the transistor 63 is connected to its drain, that is to say also to the drain of the transistor 61. The gate of the transistor 62 constitutes the terminal I2 and receives the current voltage Vout across the load 1 by a connection to the output terminal OUT of the controller. The connection point 65 of the drains of the transistors 62 and 64 constitutes the output of the input / output stage 4 of the comparator 50.

L'étage de sortie 5 est constitué de la connexion en série, entre l'alimentation haute Vdd et la masse GND, d'une impédance 9, de préférence résistive (R), et d'un transistor MOS à canal N 10. Le point de connexion de l'impédance 9 et du transistor 10 constitue la borne de sortie 02 fournissant le signal de commande de la grille G2 du transistor 33. La grille du transistor 10 est connectée au point milieu 65 de la branche différentielle 62-64 de l'étage d'entrée 4.The output stage 5 consists of the series connection, between the high power supply Vdd and the ground GND, of an impedance 9, preferably resistive (R), and an N-channel MOS transistor 10. The point of connection of the impedance 9 and the transistor 10 constitutes the output terminal 02 providing the control signal of the gate G2 of the transistor 33. The gate of the transistor 10 is connected to the midpoint 65 of the differential branch 62-64 of the entrance floor 4.

Le deuxième comparateur différentiel 51 est destiné à commander la régulation de la tension au point MID. Il fournit sur la borne de sortie 01 le signal de commande de la grille G1. Le deuxième comparateur 51 comporte deux branches différentielles symétriques constituées chacune de la connexion en série d'une impédance 52, 53, de préférence résistive, et d'un transistor MOS à canal N 54, 55, respectivement. Les sources des transistors 54 et 55 sont connectées au drain d'un transistor MOS à canal N 56 dont la source est connectée à la masse GND. La grille du transistor 56 est connectée à la sortie 65 de l'étage d'entrée/sortie 4 et à la grille du transistor 10 de l'étage de sortie 5 du premier comparateur différentiel 50. Par conséquent, le point de fonctionnement du deuxième comparateur différentiel 51 dépend de celui de l'étage de sortie 5 du premier comparateur différentiel 50. Ceci permet de stabiliser le signal de commande de la grille G1 du transistor 32 au plus à un niveau requis, qui dépend du niveau du signal de commande de la grille G2 du transistor 33 fourni par le premier comparateur 50. En particulier, lorsque la charge 1 est invalidée et que le transistor 33 est ouvert, le transistor 56 sera complètement passant et permettra une commande de la grille G1 propre à limiter la tension Vmid à la moitié (Vdd/2) de l'alimentation haute, comme cela a été décrit précédemment en relation avec la figure 4. Les grilles des transistors 54 et 55 constituent, respectivement, les bornes I3 et I4 d'application des tensions V2 et Vmid.The second differential comparator 51 is intended to control the regulation of the voltage at the MID point. It supplies on the output terminal 01 the control signal of the gate G1. The second comparator 51 comprises two symmetrical differential branches each consisting of the series connection of an impedance 52, 53, preferably resistive, and a N-channel MOS transistor 54, 55, respectively. The sources of transistors 54 and 55 are connected to the drain of an N-channel MOS transistor 56 whose source is connected to ground GND. The gate of the transistor 56 is connected to the output 65 of the input / output stage 4 and to the gate of the transistor 10 of the output stage 5 of the first differential comparator 50. Therefore, the operating point of the second The differential comparator 51 depends on that of the output stage 5 of the first differential comparator 50. This makes it possible to stabilize the control signal of the gate G1 of the transistor 32 by at most a required level, which depends on the level of the control signal. the gate G2 of the transistor 33 supplied by the first comparator 50. In particular, when the load 1 is disabled and the transistor 33 is open, the transistor 56 will be completely on and allow a control of the gate G1 own to limit the voltage Vmid at half (Vdd / 2) of the high feed, as has been described previously in relation to the figure 4 . The gates of the transistors 54 and 55 constitute, respectively, the terminals I3 and I4 for applying the voltages V2 and Vmid.

La figure 6 représente, schématiquement et partiellement, un mode de réalisation d'un générateur 37 des consignes V1 et V2. Le circuit de référence 37 est, selon un mode de réalisation de la présente invention, un diviseur de tension résistif. Le diviseur résistif comporte la connexion en série entre les rails d'alimentation haute Vdd et basse GND de trois résistances successives 71, 72 et 73. Le point de connexion 74 des résistances 72 et 73 est la borne de sortie d'un comparateur différentiel 75 à deux entrées et une sortie, par exemple similaire au comparateur 3 de la figure 1. La borne d'entrée non-inverseuse du comparateur 75 reçoit la consigne de régulation Vreg de la tension de sortie Vout du régulateur 30, par exemple, par une connexion à la source 38. La borne d'entrée inverseuse du comparateur 75 est reliée à la borne de sortie 74. Ainsi, on recopie aux bornes de la résistance 73 la première consigne nommée V1. En choisissant des résistances 71 et 72 de mêmes valeurs, le point milieu de ces deux résistances est contrôlé de façon linéaire par le comparateur 75 à la valeur voulue V2 de la demi-somme de la tension d'alimentation et de la première consigne V1.The figure 6 represents, schematically and partially, an embodiment of a generator 37 of the instructions V1 and V2. The reference circuit 37 is, according to an embodiment of the present invention, a resistive voltage divider. The resistive divider comprises the series connection between the high supply rails Vdd and low GND of three successive resistors 71, 72 and 73. The connection point 74 of the resistors 72 and 73 is the output terminal of a differential comparator 75 two inputs and one output, for example similar to the comparator 3 of the figure 1 . The non-inverting input terminal of the comparator 75 receives the regulation setpoint Vreg of the output voltage Vout of the regulator 30, for example, by a connection to the source 38. The inverting input terminal of the comparator 75 is connected to the output terminal 74. Thus, it copies to the terminals of the resistor 73 the first set point V1. By choosing resistors 71 and 72 of the same values, the midpoint of these two resistors is controlled linearly by the comparator 75 to the desired value V2 of the half-sum of the supply voltage and the first setpoint V1.

La présente invention fournit avantageusement un régulateur linéaire de puissance réalisable totalement par une filière MOS standard basse tension et de petites dimensions. En effet, le remplacement du transistor MOS haute tension des régulateurs connus par deux transistors basse tension permet de réduire la surface d'intégration. De plus, l'accroissement de surface de la partie commande 35 par rapport au circuit de commande d'un régulateur connu est négligeable par rapport au gain de surface lié au changement de commutateur de puissance.The present invention advantageously provides a linear power regulator fully achievable by a low voltage standard MOS die and small dimensions. Indeed, the replacement of the high voltage MOS transistor known regulators by two low voltage transistors reduces the integration surface. In addition, the surface increase of the control portion relative to the control circuit of a known regulator is negligible compared to the surface gain associated with the change of power switch.

En outre, le régulateur linéaire selon la présente invention présente une tension de déchet inférieure à celle des régulateurs connus. A titre d'exemple non limitatif, si la tension d'alimentation haute Vdd vaut de 3,3 à 5,5 volts, chaque transistor 32 et 33 de l'étage de sortie 31 du régulateur linéaire 30 de la présente invention est un transistor MOS standard propre à tenir une tension drain/source d'environ 2,5 volts. La tension de déchet du régulateur est alors réduite jusqu'à des valeurs de l'ordre de 200 mV.In addition, the linear regulator according to the present invention has a lower voltage drop than known regulators. By way of nonlimiting example, if the high supply voltage Vdd is from 3.3 to 5.5 volts, each transistor 32 and 33 of the output stage 31 of the linear regulator 30 of the present invention is a transistor Standard MOS clean to hold a drain / source voltage of about 2.5 volts. The regulator's waste voltage is then reduced to values of the order of 200 mV.

Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaîtront à l'homme de l'art. En particulier, on notera que le condensateur C (impédance 11) de stabilisation de la tension de sortie Vout a été décrit comme faisant fonctionnellement partie du régulateur linéaire 30. En pratique, la valeur de la capacité du condensateur C est relativement élevée et varie en fonction de l'application, c'est-à-dire de la charge 1. Le condensateur C est donc, de préférence, réalisé à l'extérieur d'une puce de circuit intégré comportant l'ensemble du régulateur 30, et est monté directement en parallèle sur la charge 1. Par ailleurs, l'homme du métier saura modifier les caractéristiques des divers composants à la filière utilisée.Of course, the present invention is susceptible of various variations and modifications which will be apparent to those skilled in the art. In particular, it will be noted that the capacitor C (impedance 11) for stabilizing the output voltage Vout has been described as being functionally part of the linear regulator 30. In practice, the capacitance value of the capacitor C is relatively high and varies in depending on the application, that is to say the load 1. The capacitor C is therefore preferably made outside an integrated circuit chip comprising the entire regulator 30, and is mounted directly in parallel on the load 1. Moreover, the skilled person will modify the characteristics of the various components to the die used.

Claims (6)

  1. A linear regulator having an output stage (31) comprising first and second P-channel MOS transistors (32, 33) serially connected between a first D.C. supply terminal (Vdd) and an output terminal (OUT) providing a regulated output voltage (Vout), and a control circuit (35) for controlling the first and second transistors, characterized in that the control circuit is capable of providing them with first and second control signals as a function of the output voltage and the voltage at the midpoint (MID) of the series connection, so that the voltage at the midpoint is maintained at half the difference between the D.C. supply and the regulated output voltage.
  2. The regulator according to claim 1, characterized in that the control circuit (35) comprises an input/output circuit (36) and a reference circuit (37), the input/output circuit comprising:
    a first input (I1), receiving a first voltage reference (V1) provided by said reference circuit;
    a second input (I2), connected to said output terminal (OUT);
    a third input (I3) receiving a second voltage reference (V2) provided by said reference circuit;
    a fourth input (14) connected to said midpoint (MID);
    a first output (O1) connected to the gate (G1) of the first transistor (32); and
    a second output (02) connected to the gate (G2) of the second transistor (33).
  3. The regulator according to claim 2, characterized in that the input/output circuit (36) is a double differential comparator with four inputs and two outputs.
  4. The regulator according to claim 2, characterized in that the input/output circuit (36) comprises first (50) and second (51) differential comparators with two inputs and two outputs, the input terminals of the first differential comparator being the first (I1) and second (I2) input terminals of the input/output circuit and its output being the second output (O2) of said input/output circuit; and the input terminals of the second differential comparator being the third (I3) and fourth (I4) input terminals of said input/output circuit and its output being the first output (O1) thereof.
  5. The regulator according to claim 4, characterized in that the first differential comparator (50) comprises an input/output stage (4) and an output stage (5), said input/output stage comprising two differential branches, each of which comprises a P-channel MOS transistor (61, 62) connected in series with a first N-channel MOS transistor (63, 64), the sources of the P-channel transistors being interconnected with an output terminal of a current source (60) having an input terminal connected to said D.C. supply terminal (Vdd), the sources of the first N-channel transistors being interconnected with a ground terminal (GND), the gates of the first N-channel MOS transistors being interconnected, the gates of the P-channel transistors forming the first (I1) and second (I2) input terminals of the input/output circuit (36), the gate of said first N-channel MOS transistor of the branch (61-63) comprising the first input being connected to its drain, the midpoint (65) of connection of the drains of the complementary transistors of the other branch (62-64) being connected to the gate of a second N-channel MOS transistor (10) connected, in said output stage (5), in series between the supply terminals, with a first impedance (9), the midpoint of the series connection of said first impedance and of the second transistor forming the output terminal (O2) of said first differential comparator.
  6. The regulator according to claim 5, characterized in that the second differential comparator (51) comprises two symmetrical differential branches, each formed of the series connection of a second impedance (52, 53) and of a third N-channel MOS transistor (54, 55), respectively, the sources of the third N-channel transistors being interconnected with the drain of a fourth N-channel MOS transistor (56) having its source connected to ground (GND), the gate of the fourth N-channel transistor being connected to the gate of the second N-channel MOS transistor (10) of the output stage (5) of the first differential comparator (50).
EP03300056.3A 2002-07-09 2003-07-09 Linear voltage regulator Expired - Lifetime EP1380913B1 (en)

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FR0208624A FR2842316A1 (en) 2002-07-09 2002-07-09 LINEAR VOLTAGE REGULATOR

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