EP1380913A1 - Linear voltage regulator - Google Patents

Abstract

The linear regulator (30) has a control unit (35) and output circuit (31) to supply a load (1) and smoothing capacitor (11). The output circuit consists of two MOS transistors (32,33) which supply an output terminal (OUT) and are controlled by connections to their grids (G1,G2) from the input/output stage (36) of the control unit. The input/output stage uses data from a reference unit (37) and the output circuit for regulation

Description

The present invention relates generally to the regulation of a voltage across a load. More specifically, the present invention relates to such regulation performed in a linear fashion.

FIG. 1 schematically and partially illustrates, a classic example of a linear regulator of a voltage Vout across a load (LD) 1. The regulator includes a transistor P 2 channel MOS whose source is connected to a rail high voltage supply Vdd and the drain of which constitutes the output terminal OUT of the regulator. Load 1 is connected between the OUT terminal and a low or voltage supply rail GND reference or mass. The transistor 2 works in regime linear, that is to say that we use its transconductance to vary its output current according to the voltage of control applied to its grid G. The control voltage of the grid G is regulated as a function of the voltage Vout at the terminals of load 1. Regulation is carried out by a comparator differential 3 comprising an input / output stage 4 and a stage 5. The input / output stage 4 comprises two branches differentials each with a P channel MOS transistor 61, 62 connected in series with an N-channel MOS transistor 63, 64. The sources of transistors 61 and 62 are connected to a output terminal of a current source 60 including one terminal input is connected to the high Vdd power supply. The sources of transistors 63 and 64 are connected to the GND low power supply. The gates of the transistors 63 and 64 are interconnected. A branch 61-63 constitutes an input branch, while the other branch 62-64 constitutes an output branch. The transistor 61 of the input branch receives a DC voltage setpoint constant Vreg supplied by a voltage generator 8, connected between the gate of transistor 61 and GND ground. The grid of transistor 63 is connected to its drain, i.e. also to the drain of transistor 61. The gate of transistor 63 receives the voltage Vout at the terminals of load 1 by a connection to the output terminal OUT of the regulator, possibly to a socket through a resistance bridge. Connection point 65 of the drains of the transistors 62 and 64 constitutes the output of the input / output stage 4 of the comparator 3.

The output stage 5 consists of the connection in series, between the high Vdd and low GND power supplies, of a generally resistive impedance 9 (R) and of a MOS transistor channel N 10. The connection point of impedance 9 and the transistor 10 constitutes the output terminal of the differential comparator 3 connected to the gate G of the regulation transistor 2. The gate of transistor 10 is connected to point 65 of the branch input / output differential 62-64.

The regulator also has an impedance (C) 11, generally capacitive, intended to stabilize the voltage of Vout exit.

FIGS. 2A-2C illustrate, by timing diagrams, an example of variation as a function of time t of the setpoint of Vreg voltage across source 8, output voltage Vout at the terminals of the load 1, and of the voltage Vds between the drain and source terminals of transistor 2. When starting of the circuit, at an instant t0, the voltage generator is validated constant constant 8 so that it delivers a setpoint of stable non-zero nominal regulation Vref up to an instant t1 circuit extinction. The 3 force differential comparator then, as illustrated in FIG. 2B, the output voltage Vout to follow the regulation voltage Vreg and align with the reference level Vref. The voltage Vout is then regulated by stably at level Vref by gate control up to the instant t1 of circuit extinction or standby. This regulation is carried out by a command in linear mode of the transistor 2 which is used as a variable transconductance whose output current depends on the control voltage on grid G.

We consider more particularly in the present description of the applications in which the load 1 must be supplied with a voltage level of around 3.3 to 5.5 volts. Such a value is relatively high compared to the 2.4 to 2.8 volts maximum voltage that can hold the components (in particular the MOS 2 transistor) used in standard integration technology streams. However, during periods of load 1 extinction, the MOS transistor 2 must hold the voltage Vdd across its terminals.

Indeed, as illustrated in Figure 2C, during the phases extinction of load 1 (Vreg = 0, FIG. 2A), that is to say before the start time t0 and after the shutdown time t1, the load control transistor 2 must support, between its drain and source terminals, a difference of potentials Vds equal to the amplitude of supply Vdd-GND. Through against, during the operation of load 1 (Vreg = Vref), the Vds voltage is reduced to the difference between the power supply high Vdd and the voltage Vout at the terminals of load 1, that is to say the nominal control value Vref.

To allow the voltage withstand of transistor 2 during the extinction phases, we changed the 2.5 volt standard manufacturing to insert MOS transistors likely to hold a maximum voltage greater than 5 volts between their drain and their source. In particular, the definition masks for regulating transistor 2 with respect to to neighboring transistors, so as to increase considerably the thickness of part of a gate insulator close to one of the drain / source regions and to increase the area of that same drain / source region. But then, the stray capacity of gate of transistor 2 is increased, and its transconductance is scaled down. However, to allow linear control of the transistor 2 as described above with control levels sufficiently weak, the transconductance must be relatively high. To increase it, we must then increase it further plus the integration surface of transistor 2.

The increase in surface area that sometimes takes integrate these command switches outside the chip in which is carried out the rest of the power circuit constituting the voltage regulator. In addition, it is necessary to hold account of a relatively high parasitic capacity compared to the parasitic capacities of the other elements of the circuit. Moreover, the waste voltage, i.e. the difference between the regulation Vref and the output voltage Vout can hardly be reduced to less than 500 mV. This is particularly disadvantageous in portable devices such as calendars electronics, satellite phones, laptops or pocket organizers. Indeed get the output level nominal necessary for the proper functioning of the load, imposes the use of a higher level deposit. This increases the congestion of the circuit and / or, more generally, causes then an accelerated discharge of the batteries supplying the assembly of the circuit and allowing to provide the reference setpoint Vref. In the latter case, frequent recharges the device’s batteries, which is contradiction with their portable nature.

In addition, changes in the manufacturing chain necessary for the formation of the regulating MOS transistor are particularly annoying in terms of complication of the overall process and cost.

To overcome these problems, it has been proposed to use a high voltage bipolar regulating transistor, which has the advantage of requiring less integration area compared to the specific MOS, in particular because it can more easily be vertically integrated into a substrate of silicon. However, the use of a bipolar transistor poses many problems.

In particular, it is necessary to use a BiCMOS sector which is more complex than the MOS sector. You also have to plan a specific circuit to fix the operating point of the bipolar transistor, and in particular provide for a limitation of the basic current. In addition, a bipolar regulating transistor leads to higher waste voltages than a transistor MOS with a narrower range of linearity. This is particularly disadvantageous in the case of devices of the type portable for which it is desirable to reduce the most possible waste voltage, that is to make it, to preferably less than 200 mV.

The present invention aims to propose a regulator linear which overcomes the drawbacks of known circuits.

The present invention aims in particular to propose a linear regulator which has a reduced waste voltage.

The present invention aims to propose such a regulator which can be manufactured using a standard MOS die.

To achieve these and other objects, this invention provides a linear regulator comprising a stage of output including first and second channel MOS transistors P, connected in series between a first supply terminal DC and an output terminal providing a voltage of regulated output, and a control circuit for the first and second transistors capable of providing first and second signals of control according to the output voltage and the voltage at midpoint of the serial connection.

According to an embodiment of the present invention, the control circuit includes an input / output circuit and a reference circuit, the input / output circuit comprising a first input, receiving a first voltage setpoint supplied by said reference circuit; a second input, connected at said output terminal; a third entry receiving a second voltage setpoint supplied by said circuit reference; a fourth input connected to said midpoint; a first output connected to the gate of the first transistor ; and a second output connected to the gate of the second transistor.

According to an embodiment of the present invention, the input / output circuit is a double differential comparator with four inputs and two outputs.

According to an embodiment of the present invention, the input / output circuit includes first and second comparators differential with two inputs and two outputs, the terminals input of the first differential comparator being the first and second input terminals of the input / output circuit and its output being the second output of said input / output circuit; and the input terminals of the second differential comparator being the third and fourth input terminals of said input / output circuit and its exit being the first exit.

According to an embodiment of the present invention, the first differential comparator has an input / output stage and an output stage, said input / output stage comprising two differential branches each of which includes a transistor P channel MOS connected in series with a first transistor N-channel MOS, sources of P-channel transistors being interconnected to an output terminal of a source of current of which one input terminal is connected to said terminal DC power sources, the sources of the first transistors N channel being interconnected to a ground terminal, the grids said first N-channel MOS transistors being interconnected, the gates of the P channel transistors constituting the first and second input terminals of the input / output circuit, the gate of the first N-channel MOS transistor of the branch comprising the first input being connected to its drain, the connection point of the transistors drains complementary to the other branch being connected to the grid of a second N-channel MOS transistor connected, in said stage of output, in series between the supply terminals, with a first impedance, the midpoint of the serial connection of said first impedance and the second transistor constituting the output terminal of said first differential comparator.

According to an embodiment of the present invention, the second differential comparator has two differential branches symmetrical each consisting of the connection in series of a second impedance, and of a third MOS transistor to N channel, respectively, the sources of the third transistors with N channel being interconnected to the drain of a fourth N-channel MOS transistor whose source is connected to the ground, the gate of the fourth N-channel transistor being connected to the gate of the second N-channel MOS transistor of the stage of output of the first differential comparator.

la figure 1, qui a été décrite précédemment, représente de façon partielle et schématique la structure d'un régulateur linéaire connu associé à une charge ;

les figures 2A à 2C, qui ont été décrites précédemment, sont des chronogrammes illustrant le fonctionnement du régulateur de la figure 1 ;

la figure 3 représente, sous forme d'un schéma-blocs partiel et schématique, un régulateur linéaire selon un mode de réalisation de la présente invention associé à une charge ;

la figure 4A est un chronogramme illustrant une première consigne de tension du régulateur de la figure 3 ;

la figure 4B est un chronogramme illustrant la tension de sortie du régulateur de la figure 3 ;

la figure 4C est un chronogramme illustrant une deuxième consigne de tension du régulateur de la figure 3 ;

la figure 4D est un chronogramme illustrant une tension aux bornes d'un composant d'un étage de sortie du régulateur de la figure 3 ;

la figure 5 représente, partiellement et schématiquement, un mode de réalisation d'un étage d'entrée/sortie du régulateur de la figure 3 ; et

la figure 6 représente un mode de réalisation d'un générateur de première et deuxième consignes de tension utilisable dans le régulateur de la figure 3.

These objects, characteristics and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which:

FIG. 1, which has been described previously, partially and schematically represents the structure of a known linear regulator associated with a load;

FIGS. 2A to 2C, which have been described previously, are timing diagrams illustrating the operation of the regulator of FIG. 1;

FIG. 3 represents, in the form of a partial and schematic block diagram, a linear regulator according to an embodiment of the present invention associated with a load;

FIG. 4A is a timing diagram illustrating a first voltage setpoint of the regulator of FIG. 3;

FIG. 4B is a timing diagram illustrating the output voltage of the regulator of FIG. 3;

FIG. 4C is a timing diagram illustrating a second voltage setpoint of the regulator of FIG. 3;

FIG. 4D is a timing diagram illustrating a voltage across a component of an output stage of the regulator of FIG. 3;

FIG. 5 represents, partially and schematically, an embodiment of an input / output stage of the regulator of FIG. 3; and

FIG. 6 represents an embodiment of a generator of first and second voltage set points usable in the regulator of FIG. 3.

For the sake of clarity, the same elements have been designated to the different figures by the same references. In addition, only the elements that are necessary for understanding the present invention have been shown. So, possible circuits validation of the reference voltage generators are neither shown or described.

FIG. 3 represents, in the form of a block diagram, a linear regulator 30 according to one embodiment of the present invention. The regulator 30 has an output stage 31 consisting of the series connection, between a power rail high Vdd and one output terminal OUT, of two transistors P channel MOS 32 and 33. The output terminal OUT is intended for be connected to a first load supply terminal (LD) 1, a second supply terminal of which is connected to a GND low or ground power rail. To stabilize quickly regulated output voltage, linear regulator 30 also preferably includes a stabilization impedance 11, for example a capacitor C.

The regulation of the voltage Vout at the terminals of the load 1, i.e. on the output terminal OUT, is carried out by modulating control signals of the grids G1 and G2 of the transistors 32 and 33, respectively, so as to modify their transconductance.

The control signals of the output stage 31 are produced by a control circuit 35. Circuit 35 modulates the control signal of the gate G1 of the transistor 32 so as to regulate the voltage at the midpoint MID of the series connection transistors 32 and 33 of the output stage 31. It modulates also the control signal of the gate G2 of the transistor 32 so as to regulate the output voltage Vout. Circuit 35 has an input / output stage (IN / OUT) 36 intended for producing the control signals and a reference stage (REF) 37. The input / output stage 36 includes four input terminals I1, 12, 13 and 14 and two output terminals 01 and 02. Terminal I1 receives a voltage regulation set point V1 of the Vout exit. Terminal I2 receives the output voltage Vout. The terminal I3 receives a regulation voltage setpoint V2 from the voltage at midpoint MID. Terminal I4 receives the voltage Vmid from the midpoint MID by a direct connection to this point. The output terminals O1 and 02 are respectively connected to the grids G1, G2.

The regulation instructions V1 and V2 received on the terminals I1 and I3 of stage 36, respectively, are supplied by the reference circuit (REF) 37 from a variable source 38 of direct voltage (Vreg). More specifically, to regulate the midpoint MID in order to guarantee an equipartition voltages across each of the two transistors in series 32 and 33, the midpoint V2 regulation setpoint is equal to half the sum of the high supply voltage Vdd and the first regulation setpoint V1 (V2 = (Vdd + V1) / 2). The source 38 therefore preferably provides directly the first setpoint V1 (Vreg = V1) from which circuit 37 provides the second setpoint V2 according to the previous relationship.

FIGS. 4A, 4B, 4C and 4D respectively illustrate, by chronograms, the variation as a function of time t of the regulation setpoint V1 of the output voltage Vout of regulator 30 of FIG. 3, of the output voltage Vout, of the V2 midpoint voltage regulation setpoint and of the current voltage Vmid at the midpoint MID, that is to say the drain voltage of transistor 32.

When the regulator 30 is started, at an instant t10, the reference circuit 37 is validated by a start-up from source 38 and produces the regulation setpoints V1 and V2. As illustrated in FIGS. 4A and 4C, the regulation instructions V1 and V2 are, during a priming phase (instants t10 at t11), parallel ramps. Indeed, as has been indicated previously, to ensure a balanced distribution of voltages at the terminals of transistors 32 and 33, it is necessary to ensure that at all times the potential at midpoint MID is equal to the half the difference between high supply voltage Vdd and the voltage Vout at the terminals of the load 1 (Vmid = (Vdd-Vout) / 2). To do this, you must apply a setpoint equal to the half sum of the high supply voltage Vdd and the first setpoint V1. When changing the setpoint V1 from a zero value to a nominal setpoint Vref, the command 35 must be able to ensure such a condition. To allow linear monitoring, then it is preferable that the setpoint V1 varies slowly rather than suddenly as in the case of a standard setpoint (Figure 2A).

As illustrated in Figure 4B, during the phase the output voltage Vout follows, from at time t10, the first setpoint V1 until it stabilizes at the instant t11 at the nominal value Vref. The voltage Vmid at midpoint MID, illustrated in FIG. 4D, decreases by controlled way of half the high feed (Vdd / 2) up to the stable value (Vdd-Vref) / 2. In nominal operation, between times t11 and t12, the output voltages Vout and from the midpoint Vmid are kept stable by stable V1 and V2 setpoints. When an extinction command load 1 at time t12, to allow linear monitoring of the second setpoint V2, the first setpoint V1 is gradually brought back to zero along a ramp up to an instant t13. The Vdd power supply is then distributed symmetrically over the transistors 32 and 33.

In nominal mode (from t11 to t12), the control circuit 35 ensures that any possible fluctuation in power at load level 1 results in a variation of the setpoints V1 and V2 so as to restore the nominal speed and distribute the power variation symmetrically on both power transistors 32 and 33. Thus, neither of the two transistors 32 and / or 33 does not face tension excessive drain / source.

FIG. 4 shows boot ramps and of different respective slope extinction. More specifically, we represented a faster extinction (t12-t13) than priming (t10-t11). In practice, the slope of the ramps depends technical performance of the circuits and in particular of the ability of the control circuit 35 to track, transform and transmit, the variation of the first setpoint V1. The hills may be faster or slower than shown. In in addition, they can be symmetrical or present an asymmetry opposite to that shown, that is to say that the priming can be faster than extinction.

FIG. 5 illustrates, schematically and partially, the structure of an embodiment of the input / output stage 36 a control circuit 35 of an output stage 31 of a regulator 30 according to the present invention.

Input / output circuit 36 with four inputs and two outputs is a differential comparator. More specifically, circuit 36 consists of the association of a first differential comparator 50 and a second differential comparator 51 intertwined as follows.

The first comparator 50, delimited by a frame in dotted in Figure 5, is intended to regulate the voltage of Vout output from the first setpoint V1. The comparator 50 therefore has a structure similar to that of a comparator known differential such as comparator 3 described in relation with Figure 1. For clarity, the structure of the comparator 50 is described below using the same references as in figure 1.

Comparator 50 has an input / output stage 4 and an output stage 5. Stage 4 comprises two differential branches each comprising a P-channel MOS transistor 61, 62 connected in series with an N-channel MOS transistor 63, 64. The sources of transistors 61 and 62 are connected to a terminal of output of a current source 60 of which an input terminal is connected to the high Vdd power supply. The sources of the transistors 63 and 64 are connected to the GND low power supply. Grates transistors 63 and 64 are interconnected. The grid of transistor 61 constitutes the terminal I1 and receives the setpoint V1. The gate of transistor 63 is connected to its drain, i.e. also to the drain of transistor 61. The gate of transistor 62 constitutes the terminal I2 and receives the current voltage Vout aux load 1 terminals by connection to the OUT output terminal of the regulator. The connection point 65 of the drains of the transistors 62 and 64 constitute the output of the input / output stage 4 of comparator 50.

The output stage 5 consists of the connection in series, between the high Vdd supply and GND ground, of a impedance 9, preferably resistive (R), and a MOS transistor N channel 10. The connection point of impedance 9 and transistor 10 constitutes the output terminal 02 providing the control signal of the gate G2 of the transistor 33. The gate of transistor 10 is connected to midpoint 65 of the branch differential 62-64 of the input stage 4.

The second differential comparator 51 is intended for control the voltage regulation at the MID point. He gives on the output terminal 01 the control signal from the gate G1. The second comparator 51 has two differential branches symmetrical, each consisting of the series connection an impedance 52, 53, preferably resistive, and a N-channel MOS transistor 54, 55, respectively. The sources of transistors 54 and 55 are connected to the drain of a transistor N-channel MOS 56 whose source is connected to GND ground. The gate of transistor 56 is connected to output 65 of the stage input / output 4 and to the gate of transistor 10 of the stage of output 5 of the first differential comparator 50. Consequently, the operating point of the second differential comparator 51 depends on that of the output stage 5 of the first comparator differential 50. This stabilizes the control signal of the gate G1 of the transistor 32 at most at a required level, which depends on the level of the gate G2 control signal of the transistor 33 provided by the first comparator 50. In particular, when load 1 is disabled and transistor 33 is open, transistor 56 will be completely on and allow a gate control G1 capable of limiting the voltage Vmid to half (Vdd / 2) of the high power supply, as has been described previously in relation to Figure 4. The grids transistors 54 and 55 constitute, respectively, the terminals I3 and I4 of application of the voltages V2 and Vmid.

FIG. 6 represents, schematically and partially, an embodiment of a generator 37 of the setpoints V1 and V2. The reference circuit 37 is, according to one embodiment of the present invention, a resistive voltage divider. The resistive divider has the series connection between the high Vdd and low GND power rails of three resistors 71, 72 and 73. The connection point 74 of the resistors 72 and 73 is the output terminal of a differential comparator 75 with two inputs and one output, for example similar to comparator 3 of figure 1. The non-inverting input terminal of comparator 75 receives the Vreg regulation setpoint from the output voltage Vout of regulator 30, for example, by a connection to the source 38. The inverting input terminal of the comparator 75 is connected to the output terminal 74. Thus, we copies the first setpoint across the terminals of resistor 73 named V1. By choosing resistors 71 and 72 of the same values, the midpoint of these two resistors is controlled by linearly through comparator 75 to the desired value V2 of the half sum of the supply voltage and the first setpoint V1.

The present invention advantageously provides a regulator linear power fully achievable by a die Low-voltage standard MOS with small dimensions. Indeed, replacement of the high-voltage regulator MOS transistor known by two low voltage transistors reduces the integration surface. In addition, the increased surface area of the control part 35 with respect to the control circuit of a known regulator is negligible compared to the surface gain related to the change of power switch.

In addition, the linear regulator according to this invention has a lower waste voltage than known regulators. By way of nonlimiting example, if the high supply voltage Vdd is 3.3 to 5.5 volts, each transistor 32 and 33 of the output stage 31 of the linear regulator 30 of the present invention is a standard MOS transistor suitable for holding a drain / source voltage of approximately 2.5 volts. The regulator waste voltage is then reduced to values of the order of 200 mV.

Of course, the present invention is capable of various variations and modifications that will appear to humans art. In particular, it will be noted that the capacitor C (impedance 11) stabilization of the output voltage Vout has been described as functionally part of the regulator linear 30. In practice, the value of the capacitance of the capacitor C is relatively high and varies depending on the application, that is to say of the charge 1. The capacitor C is therefore, preferably made outside a circuit chip integrated with the regulator assembly 30, and is mounted directly in parallel on the load 1. In addition, the man of the trade will be able to modify the characteristics of the various components to the sector used.

Claims (6)

Linear regulator with one output stage (31) comprising first and second P-channel MOS transistors (32, 33), connected in series between a first supply terminal continuous (Vdd) and an output terminal (OUT) providing a regulated output voltage (Vout), and a control circuit (35) first and second transistors capable of providing them with first and second control signals as a function of voltage output and voltage at the midpoint (MID) of the connection serial. Regulator according to claim 1, characterized in that the control circuit (35) comprises an input / output circuit (36) and a reference circuit (37), the input / output circuit comprising: a first input (I1), receiving a first voltage setpoint (V1) supplied by said reference circuit; a second input (I2), connected to said output terminal (OUT); a third input (I3) receiving a second voltage setpoint (V2) supplied by said reference circuit; a fourth input (I4) connected to said midpoint (MID); a first output (01) connected to the gate (G1) of the first transistor (32); and a second output (02) connected to the gate (G2) of the second transistor (33). Regulator according to claim 2, characterized in that the input / output circuit (36) is a double differential comparator with four inputs and two outputs. Regulator according to claim 2 or 3, characterized in that the input / output circuit (36) comprises first (50) and second (51) differential comparators with two inputs and two outputs, the input terminals of the first comparator differential being the first (I1) and second (I2) input terminals of the input / output circuit and its output being the second output (O2) of said input / output circuit; and the input terminals of the second differential comparator being the third (13) and fourth (14) input terminals of said input / output circuit and its output being the first output (01). Regulator according to claim 4, characterized in that the first differential comparator (50) comprises an input / output stage (4) and an output stage (5), said input / output stage comprising two differential branches each of which comprises a P-channel MOS transistor (61, 62) connected in series with a first N-channel MOS transistor (63, 64), the sources of the P-channel transistors being interconnected to an output terminal of a current source ( 60) an input terminal of which is connected to said continuous supply terminal (Vdd), the sources of the first N-channel transistors being interconnected to a ground terminal (GND), the gates of said first N-channel MOS transistors being interconnected, the gates of the P-channel transistors constituting the first (I1) and second (12) input terminals of the input / output circuit (36), the gate of the first N-channel MOS transistor of the branch (61- 63) with the first entry and ant connected to its drain, the midpoint (65) of connection of the drains of the complementary transistors of the other branch (62-64) being connected to the gate of a second N-channel MOS transistor (10) connected, in said output stage (5), in series between the supply terminals, with a first impedance (9), the midpoint of the series connection of said first impedance and of the second transistor constituting the output terminal (02) of said first differential comparator. Regulator according to claim 5, characterized in that the second differential comparator (51) comprises two symmetrical differential branches each consisting of the series connection of a second impedance (52, 53), and of a third N-channel MOS transistor (54, 55), respectively, the sources of the third N-channel transistors being connected to the drain of a fourth N-channel MOS transistor (56) whose source is connected to ground (GND), the gate of the fourth transistor to N channel being connected to the gate of the second N channel MOS transistor (10) of the output stage (5) of the first differential comparator (50).

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