EP2256578A1 - Low-dropout voltage regulator with low quiescent current - Google Patents
Low-dropout voltage regulator with low quiescent current Download PDFInfo
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- EP2256578A1 EP2256578A1 EP10004211A EP10004211A EP2256578A1 EP 2256578 A1 EP2256578 A1 EP 2256578A1 EP 10004211 A EP10004211 A EP 10004211A EP 10004211 A EP10004211 A EP 10004211A EP 2256578 A1 EP2256578 A1 EP 2256578A1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- the present invention relates to a low voltage drop voltage regulator circuit, or LDO. More particularly, the present invention relates to a circuit configuration for minimizing quiescent current in an LDO.
- LDOs are DC regulators that receive an input voltage from a voltage source, such as a battery, and provide a stable output voltage at an electrical load.
- the voltage source may vary or become depleted over time, but the load requires a constant supply voltage to operate.
- the minimum difference between the input and output voltages that still allows the low-voltage regulator to regulate the output voltage is known as the "drop out voltage".
- This waste voltage should be as low as possible to maximize efficiency while minimizing energy dissipation, and is thus between 1.0 and 1.5 V. For example, if the waste voltage is 0.7 V, the input voltage must be at least 4.0 V to provide an output voltage of 3.3 V.
- Low voltage drop regulators are particularly useful in battery-powered portable applications, such as mobile phones, digital music players, personal digital assistants, cameras, and so on.
- the LDO1 controller comprises an IN input node and an OUT output node.
- the input node receives a Vin input voltage provided by a PS power source, such as a battery.
- the output node OUT is connected to a load LD and provides a regulated output voltage Vreg and an output current Iout to the load LD.
- the regulator LDO1 comprises a regulation transistor TREG, a GCS gate control stage and an EAMP error amplifier.
- the regulation transistor TREG here a PMOS transistor, has its source S connected to the input node IN and its drain D connected to the output node OUT.
- the gate G of the transistor is driven by a gate voltage Vg supplied by the GCS gate control stage.
- the GCS gate control stage comprises a high-gate bias resistor RG1 ("pull-up gate resistor") and a control transistor TQ, here an NPN bipolar transistor.
- the resistor RG1 has a terminal connected to the input node IN and a terminal connected to the gate G of the transistor TREG.
- the transistor TQ has a collector C connected to the gate G of the transistor TREG and an emitter E connected to ground by a resistor RG2.
- the base B of the transistor TQ receives a control voltage Vc supplied by the error amplifier EAMP.
- the EAMP amplifier includes a negative input and a positive input.
- the negative input receives a stable voltage Vref provided by a stable voltage source BG, such as a bandgap voltage source.
- the positive input receives a feedback voltage Vf.
- the feedback voltage is a percentage of the output voltage Vreg, provided by a voltage divider comprising resistors R1, R2.
- the error amplifier compares the reference voltage Vref and the feedback voltage Vf, and supplies the control voltage Vc to the GCS gate control stage.
- the quiescent current Iq is defined as the current that is used to bias the GCS gate control stage, and is equal to a current Iin at the input node IN of the controller minus a current Iout supplied to the load LD and an Iamp current supplied to the EAMP error amplifier.
- the quiescent current is considered to consist essentially of the current flowing in the gate resistor RG1.
- the reference voltage Vref is assumed to be 1.8V and R2 is assumed to be 0.
- the horizontal axis represents time and it is assumed that the voltage Vin gradually decreases as the source of power is discharging.
- the quiescent current Iq is substantially constant in the region on the left side of the dashed line and begins to increase when the ohmic region is reached, particularly when the current consumption in the load is high. For both current consumption (50 nA and 50 mA), the quiescent current increases abruptly and reaches a maximum value when the output voltage Vreg is almost equal to the input voltage Vin (Vin-Vreg ⁇ 0, 2 V).
- the error amplifier EAMP tries to maintain the output voltage at its nominal value (Vref) and draws the gate voltage Vg downwards. Assuming that the voltage V CE flowing through the transistor TQ is very low, the maximum value of the quiescent current is approximately equal to Vin / (RG1 + RG2).
- Iamp current flowing through the error amplifier is in general constant and it will therefore be considered that nothing can be done to control its value.
- US Pat. No. 7,312,598 discloses a low waste voltage regulator having a quiescent current control circuit including a PMOS detecting transistor capable of detecting a low charge current, for example 0.5 mA.
- a voltage Vqc is set to a high value.
- the controller when it detects the low charge current state, generates a relatively low quiescent current by disabling some components, and so less power is consumed.
- the voltage Vqc is set to a low value so that all components disabled for the low charge state are quickly enabled for full operation.
- Embodiments of the invention provide a low voltage dropout voltage regulator comprising a regulating transistor for providing a regulated output voltage from an input voltage, a gate control stage including a gate circuit high-bias gate resistor and a control transistor, for supplying a gate voltage to the control transistor, an error amplifier for supplying a control voltage to a control transistor control terminal, and a quiescent current control circuit for limiting a quiescent current flowing through the gate control stage as the input voltage approaches the output voltage and inputs the control transistor into an ohmic conduction mode .
- the quiescent current control circuit includes a current source providing a current of reference and is configured to control the quiescent current by mirror effect based on the reference current.
- the current control circuit is also configured to simultaneously control the control voltage supplied by the error amplifier to the control terminal of the control transistor.
- the current control circuit comprises an output which is connected to the control terminal of the control transistor and is configured to change the control voltage supplied by the error amplifier to the control terminal.
- the quiescent current control circuit comprises a first transistor having a first conduction terminal connected to the current source, a second conduction terminal arranged to receive the output voltage and a terminal control circuit arranged to receive the gate voltage, and the gate resistance circuit comprises a transistor which is coupled in current mirror configuration with the first transistor of the idle current control circuit.
- the low-voltage voltage regulator comprises a Miller compensation branch connected between a conduction terminal of the control transistor and the first conduction terminal of the control transistor.
- the quiescent current control circuit comprises a second transistor having a control terminal connected to the first conduction terminal of the first transistor, a first conduction terminal connected to the ground, and a second conduction terminal connected to the control terminal of the control transistor.
- the gate resistance circuit comprises a gate transistor interacting with a transistor of the quiescent current control circuit to create a current mirror between the quiescent current control circuit and the grid control stage.
- the gate resistance circuit also comprises a first resistor in parallel with the gate transistor and a second resistor in series with the first resistor.
- the quiescent current control circuit is configured to be in a deactivated state in which it does not consume current when the control transistor has not entered ohmic conduction mode.
- the regulation transistor is in ohmic conduction mode when the voltage difference between the input voltage and the regulated output voltage is less than or equal to 2.0 V.
- Embodiments of the invention also relate to a portable device comprising a battery for providing an input voltage, a circuit powered by a regulated voltage, and a low voltage voltage regulator according to one of the embodiments. described above, to provide the regulated output voltage from the input voltage.
- the figure 3 illustrates a LDO2 low voltage regulator according to one embodiment of the invention.
- the LDO2 regulator comprises an input node IN and an output node OUT.
- the input node receives an input voltage Vin supplied by a PS power source, such as a battery.
- the output node OUT is connected to a load LD schematically represented by a resistor RL and a capacitor CL in parallel, and provides a regulated output voltage Vreg and an output current Iout to the load LD.
- the regulator LDO2 comprises a regulation transistor TREG, a gate control stage GCS, an amplifier amplifier EAMP (differential amplifier) and a current control circuit CCT.
- the regulation transistor TREG here a PMOS transistor, has its source S connected to the node IN and its drain D connected to the node OUT.
- the gate G of the transistor is driven by a gate voltage Vg supplied by the GCS gate control stage.
- the GCS gate control stage comprises a gate resistance circuit RG10 and a control transistor TQ, here an NPN bipolar transistor.
- the resistance circuit RG10 has a terminal connected to the input node IN and a terminal connected to the gate G of the transistor TREG.
- the transistor TQ has a collector C connected to the gate G of the transistor TREG and a transmitter E connected to ground (GND) by a resistor RG2.
- the base B of the transistor TQ receives a control voltage Vc supplied by the error amplifier EAMP.
- the EAMP amplifier includes a negative input and a positive input.
- the negative input receives a stable voltage Vref provided by a stable voltage source BG, such as a bandgap voltage source.
- the positive input receives a feedback voltage Vf.
- the feedback voltage is a percentage of the output voltage Vreg provided by a voltage divider comprising resistors R1, R2.
- the error amplifier compares the reference voltage Vref and the feedback voltage Vf, and supplies the control voltage Vc to the gate control stage GCS.
- the quiescent current control circuit CCT has two inputs respectively connected to the gate G of the transistor TREG and to the output node OUT of the regulator, and an output connected to the base B of the transistor TQ.
- the quiescent current control circuit CCT has an internal current source CS10, and is arranged to detect the gate voltage Vg applied by the gate control stage GCS to the transistor TREG. When the gate voltage Vg reaches a value which indicates that the transistor TREG has entered ohmic conduction mode, the quiescent current control circuit CCT activates and controls the quiescent current Iq passing through the gate control stage GCS so to prevent the quiescent current from reaching excessive values. Also, the quiescent current control circuit CCT "takes over" the error amplifier EAMP and takes control of the voltage Vc applied to the base B of the transistor TQ in order to control the gate voltage Vg of the transistor TREG regulation.
- the control of the quiescent current Iq by the control circuit CCT is carried out by means of a current mirror mechanism between the current source CS10 and the gate control stage GCS.
- a transistor may be added to the GCS gate control stage.
- a PMOS transistor TG is arranged in the gate resistance circuit RG10, i.e. in the pull-up section of the GCS gate control stage. which receives the input voltage Vin and supplies the gate voltage Vg.
- the gate resistance circuit RG10 comprises two resistors RG11, RG12 in series and a transistor TG is diode-connected in parallel with the resistor RG11, its drain D being connected to its gate G.
- the resistor RG11 has a high value, for example 1 M ⁇ , and is provided as a leakage resistor to ensure that the gate voltage Vg of the regulating transistor TREG receives the input voltage Vin in the absence of control by the error amplifier, for example when the circuit is switched on.
- the resistance RG12 has a low value, for example 10 K ⁇ .
- the figure 4 illustrates an example of implementation of the quiescent current control circuit CCT and an example of implementation of the error amplifier EAMP.
- the quiescent current control circuit CCT comprises a PMOS transistor T10, an NMOS transistor T11, and the current source CS10.
- a branch Miller compensation comprising, for example, a resistor R10 and a capacitor C10 may also be provided.
- the transistor T10 has its source S connected to the output node OUT of the regulator LDO2, its drain D connected to ground (GND) by the current source CS10, and its gate G connected to the gate G of the regulation transistor TREG in order to detect the gate voltage Vg.
- the transistor T11 has its gate connected to the drain D of the transistor T10, its drain D connected to the base B of the transistor TQ, and its source S connected to ground.
- the compensation branch Miller comprising the resistor R10 and the capacitor C10, is connected between the emitter E of the transistor TQ and the drain D of the transistor T10.
- the error amplifier EAMP conventionally comprises a current source CS1, PMOS transistors TE1, TE2, NPN bipolar transistors TE3, TE4 and resistors RE1, RE2.
- the current source CS1 has a first terminal connected to the input node IN of the regulator, and a second terminal connected to the sources S of the transistors TE1, TE2.
- the drains D of the transistors TE1, TE2 are respectively connected to the collectors C of the transistors TE3, TE4.
- Transmitters E of transistors TE3, TE4 are respectively connected to ground by resistors RE1, RE2.
- the collector C of the transistor TE4 is connected to the base B of the transistor TQ and supplies the control voltage Vc when the quiescent current control circuit CCT is in the non-conductive state.
- the bases B of the transistors TE3, TE4 are both connected to the collector C of the transistor TE3.
- the gate G of the transistor TE1 receives the reference voltage Vref and the gate G of the transistor TE2
- the quiescent current control circuit CCT is arranged to monitor the voltage difference between the gate voltage Vg and the output voltage Vreg.
- the transistor T10 of the current control circuit CCT is in the non-conducting state because the voltage difference Vgs between its gate G and its source S is positive and therefore higher than its negative threshold voltage (Vg> Vreg).
- Current source CS10 also prevents transistor T11 from driving. Therefore, the quiescent current control circuit CCT is in the off state and does not interfere with the normal operation of the EAMP error amplifier. In addition, it does not consume power.
- the LDO2 regulator functions as the conventional LDO1 regulator of the figure 1 .
- the error amplifier EAMP When the input voltage Vin decreases, for example as the power source PS discharges if it is a battery, the error amplifier EAMP tries to maintain the output voltage Vreg necessary, as explained above.
- the gate voltage Vg begins to decrease and the difference between the gate voltage and the source voltage of the transistor T10, which is equal to Vg-Vreg, becomes negative and lower than its negative threshold voltage (Vg ⁇ Vreg).
- the transistor TQ is highly conductive and the transistor T10 begins to become conductive.
- the current source CS10 imposes a current Iref by the transistor T10 and also limits the quiescent current by a current mirror effect.
- the ratio between the controlled quiescent current Iq and the current Iref is determined by the respective dimensions of the transistors T10 and TG, that is to say their respective W / L ratios (W being the width of the gate and L being the length of the gate of the transistors).
- W being the width of the gate
- L being the length of the gate of the transistors.
- the drain voltage of the transistor T10 causes the transistor T11 to begin to become conductive, and thus to control the base voltage Vb of the transistor TQ and to prevent the error amplifier EAMP from pulling the control voltage Vc upwards. .
- the base B of the transistor TQ is pulled to ground, and the transistor T11 regulates the conduction of the transistor TQ.
- the transistor T11 controls the base B of the transistor TQ to ensure that Iref is equal to the current flowing through the current source CS10, so that an additional control mechanism appears.
- Iref is equal to the through current CS10
- the current Iq is controlled and is equal to Iref or proportional to Iref as a function of the W / L ratios.
- the reference voltage Vref is assumed to be 1.8V, and R2 is assumed to be 0.
- the horizontal axis represents time and it is assumed that the voltage Vin gradually decreases.
- the quiescent current Iq is substantially constant in the region to the left of the dashed line.
- Vin approaches the nominal value the output voltage Vreg and Vin-Vreg becomes equal to 0.2 V.
- the quiescent current control circuit CCT prevents the gate control stage GCS from rapidly pulling the gate voltage Vg towards the gate. low while preventing the quiescent current Iq from decreasing abruptly.
- the quiescent current Iq is approximately maintained at the same value it had before reaching the ohmic conduction mode.
- the figure 6 illustrates schematically an example of application of a LDO2 low voltage regulator according to the invention.
- the low voltage LDO2 regulator is arranged in a portable HDV device having a BT battery forming its PS power source, and circuitry on MBD motherboard.
- the circuitry may include, for example, a BBP baseband processor configured to establish a telephone communication over a cellular network.
- the battery provides the Vin input voltage of the LDO2 regulator and the regulated voltage Vreg provided by the LDO2 regulator powers all or some of the components of the motherboard, in particular the BBP baseband processor.
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Abstract
Description
La présente invention concerne un circuit de régulateur de tension à faible tension de déchet, ou LDO. Plus particulièrement, la présente invention concerne une configuration de circuit permettant de minimiser le courant de repos dans un LDO.The present invention relates to a low voltage drop voltage regulator circuit, or LDO. More particularly, the present invention relates to a circuit configuration for minimizing quiescent current in an LDO.
Les LDO sont des régulateurs de courant continu qui reçoivent une tension d'entrée d'une source de tension, telle qu'une batterie, et fournissent une tension de sortie stable à une charge électrique. La source de tension peut varier ou s'épuiser avec le temps, mais la charge nécessite une tension d'alimentation constante pour fonctionner.LDOs are DC regulators that receive an input voltage from a voltage source, such as a battery, and provide a stable output voltage at an electrical load. The voltage source may vary or become depleted over time, but the load requires a constant supply voltage to operate.
La différence minimale entre les tensions d'entrée et de sortie qui permet encore au régulateur à faible tension de déchet de réguler la tension de sortie est connue sous le nom de "tension de déchet" ("drop out voltage"). Cette tension de déchet doit être la plus basse possible afin de maximiser l'efficacité tout en minimisant la dissipation d'énergie, et elle est ainsi comprise entre 1,0 et 1,5 V. Par exemple, si la tension de déchet est de 0,7 V, la tension d'entrée doit être d'au moins 4,0 V pour fournir une tension de sortie de 3,3 V.The minimum difference between the input and output voltages that still allows the low-voltage regulator to regulate the output voltage is known as the "drop out voltage". This waste voltage should be as low as possible to maximize efficiency while minimizing energy dissipation, and is thus between 1.0 and 1.5 V. For example, if the waste voltage is 0.7 V, the input voltage must be at least 4.0 V to provide an output voltage of 3.3 V.
Les régulateurs à faible tension de déchet sont particulièrement utiles dans les applications portables fonctionnant sur batterie, par exemple les téléphones portables, les baladeurs numériques, les assistants numériques personnels, les appareils photos, etc.Low voltage drop regulators are particularly useful in battery-powered portable applications, such as mobile phones, digital music players, personal digital assistants, cameras, and so on.
Une structure conventionnelle d'un régulateur à faible tension de déchet LDO1 est illustrée sur la
Le régulateur LDO1 comprend un transistor de régulation TREG, un étage de contrôle de grille GCS et un amplificateur d'erreur EAMP.The regulator LDO1 comprises a regulation transistor TREG, a GCS gate control stage and an EAMP error amplifier.
Le transistor de régulation TREG, ici un transistor PMOS, a sa source S connectée au noeud d'entrée IN et son drain D connecté au noeud de sortie OUT. La grille G du transistor est pilotée par une tension de grille Vg fournie par l'étage de contrôle de grille GCS.The regulation transistor TREG, here a PMOS transistor, has its source S connected to the input node IN and its drain D connected to the output node OUT. The gate G of the transistor is driven by a gate voltage Vg supplied by the GCS gate control stage.
L'étage de contrôle de grille GCS comprend une résistance de grille de polarisation à l'état haut RG1 ("pull-up gate resistor") et un transistor de contrôle TQ, ici un transistor bipolaire NPN. La résistance RG1 présente une borne connectée au noeud d'entrée IN et une borne connectée à la grille G du transistor TREG. Le transistor TQ présente un collecteur C connecté à la grille G du transistor TREG et un émetteur E relié à la masse par une résistance RG2.The GCS gate control stage comprises a high-gate bias resistor RG1 ("pull-up gate resistor") and a control transistor TQ, here an NPN bipolar transistor. The resistor RG1 has a terminal connected to the input node IN and a terminal connected to the gate G of the transistor TREG. The transistor TQ has a collector C connected to the gate G of the transistor TREG and an emitter E connected to ground by a resistor RG2.
La base B du transistor TQ reçoit une tension de contrôle Vc fournie par l'amplificateur d'erreur EAMP. L'amplificateur EAMP comprend une entrée négative et une entrée positive. L'entrée négative reçoit une tension stable Vref fournie par une source de tension stable BG, telle une source de tension à bande interdite ("bandgap"). L'entrée positive reçoit une tension de rétroaction Vf. La tension de rétroaction est un pourcentage de la tension de sortie Vreg, fournie par un diviseur de tension comprenant des résistances R1, R2.The base B of the transistor TQ receives a control voltage Vc supplied by the error amplifier EAMP. The EAMP amplifier includes a negative input and a positive input. The negative input receives a stable voltage Vref provided by a stable voltage source BG, such as a bandgap voltage source. The positive input receives a feedback voltage Vf. The feedback voltage is a percentage of the output voltage Vreg, provided by a voltage divider comprising resistors R1, R2.
L'amplificateur d'erreur compare la tension de référence Vref et la tension de rétroaction Vf, et fournit la tension de contrôle Vc à l'étage de contrôle de grille GCS.The error amplifier compares the reference voltage Vref and the feedback voltage Vf, and supplies the control voltage Vc to the GCS gate control stage.
Le courant de repos Iq est défini comme le courant qui est utilisé pour polariser l'étage de contrôle de grille GCS, et il est égal à un courant Iin au noeud d'entrée IN du régulateur moins un courant Iout fourni à la charge LD et un courant Iamp fourni à l'amplificateur d'erreur EAMP. Le courant de repos est considéré comme étant essentiellement constitué par le courant circulant dans la résistance de grille RG1.The quiescent current Iq is defined as the current that is used to bias the GCS gate control stage, and is equal to a current Iin at the input node IN of the controller minus a current Iout supplied to the load LD and an Iamp current supplied to the EAMP error amplifier. The quiescent current is considered to consist essentially of the current flowing in the gate resistor RG1.
L'efficacité en termes de puissance d'un régulateur à faible tension de déchet dépend ainsi de la valeur des courants Iq et Iamp et des tensions d'entrée et de sortie, comme l'illustre l'équation suivante :
En mode de fonctionnement normal, dans lequel la tension d'entrée Vin est supérieure à la tension de sortie Vreg, l'efficacité d'un LDO est en général satisfaisante. Cependant, le courant de repos Iq augmente de façon importante et l'efficacité diminue d'autant lorsque la tension d'entrée Vin s'approche de la tension de sortie Vreg. Cela provient du fait que le transistor de régulation TREG entre en mode de conduction ohmique et que la tension de grille Vg tend vers zéro, ce qui augmente de manière significative le courant de repos Iq. Cela pose un problème lorsque le régulateur de tension est alimenté par une batterie, puisque plus la batterie se décharge, plus le courant de repos Iq est élevé et décharge la batterie rapidement.In normal operating mode, in which the input voltage Vin is greater than the output voltage Vreg, the efficiency of an LDO is generally satisfactory. However, the quiescent current Iq increases significantly and the efficiency decreases as the input voltage Vin approaches the output voltage Vreg. This is because the control transistor TREG goes into ohmic conduction mode and the gate voltage Vg tends to zero, which significantly increases the quiescent current Iq. This is a problem when the voltage regulator is powered by a battery, since the more the battery discharges, the higher the quiescent current Iq is high and discharges the battery quickly.
A titre d'illustration, les
Une ligne verticale en pointillés indique la limite où Vin-Vreg = 0,2 V (0,2 V étant la tension de seuil du transistor de régulation TREG) et le côté à droite de la ligne en pointillés représente une région de fonctionnement du transistor de régulation où Vin-Vreg < 0,2 V, correspondant à un mode de conduction ohmique. On peut voir que le courant de repos Iq est sensiblement constant dans la région située sur le côté gauche de la ligne en pointillés et commence à augmenter lorsque la région ohmique est atteinte, en particulier lorsque la consommation de courant dans la charge est élevée. Pour les deux consommations de courant (50 nA et 50 mA), le courant de repos augmente de façon abrupte et atteint une valeur maximale lorsque la tension de sortie Vreg est presque égale à la tension d'entrée Vin (Vin-Vreg < 0,2 V). En effet, l'amplificateur d'erreur EAMP essaye de maintenir la tension de sortie à sa valeur nominale (Vref) et tire la tension de grille Vg vers le bas. En supposant que la tension VCE traversant le transistor TQ soit très basse, la valeur maximale du courant de repos est environ égale à Vin/(RG1+RG2).A dashed vertical line indicates the limit where Vin-Vreg = 0.2 V (0.2 V is the threshold voltage of the regulating transistor TREG) and the right side of the dotted line represents a region of operation of the transistor where Vin-Vreg <0.2 V, corresponding to an ohmic conduction mode. It can be seen that the quiescent current Iq is substantially constant in the region on the left side of the dashed line and begins to increase when the ohmic region is reached, particularly when the current consumption in the load is high. For both current consumption (50 nA and 50 mA), the quiescent current increases abruptly and reaches a maximum value when the output voltage Vreg is almost equal to the input voltage Vin (Vin-Vreg <0, 2 V). Indeed, the error amplifier EAMP tries to maintain the output voltage at its nominal value (Vref) and draws the gate voltage Vg downwards. Assuming that the voltage V CE flowing through the transistor TQ is very low, the maximum value of the quiescent current is approximately equal to Vin / (RG1 + RG2).
Il peut être noté que le courant Iamp traversant l'amplificateur d'erreur est en général constant et il sera donc considéré que rien ne peut être fait pour contrôler sa valeur.It can be noted that the Iamp current flowing through the error amplifier is in general constant and it will therefore be considered that nothing can be done to control its value.
Par conséquent, il peut être souhaité de prévoir un régulateur de tension à faible tension de déchet dans lequel le courant de repos Iq n'augmente pas de manière significative lorsque le transistor de régulation est en mode de conduction ohmique.Therefore, it may be desired to provide a low voltage voltage regulator of waste in which the quiescent current Iq does not increase significantly when the control transistor is in ohmic conduction mode.
Le brevet américain N° 7,312,598 décrit un régulateur à faible tension de déchet présentant un circuit de contrôle de courant de repos comprenant un transistor de détection PMOS pouvant détecter un faible courant de charge, par exemple de 0,5 mA. Dans un état de faible courant de charge, une tension Vqc est réglée à une valeur élevée. Le régulateur, lorsqu'il détecte l'état de faible courant de charge, génère un courant de repos relativement bas en désactivant certains composants, et ainsi moins de puissance est consommée. Lorsque qu'un état de courant de charge élevé est détecté, la tension Vqc est réglée à une valeur basse de telle sorte que tous les composants désactivés pour l'état de faible courant de charge sont rapidement activés pour un fonctionnement complet.US Pat. No. 7,312,598 discloses a low waste voltage regulator having a quiescent current control circuit including a PMOS detecting transistor capable of detecting a low charge current, for example 0.5 mA. In a low charge current state, a voltage Vqc is set to a high value. The controller, when it detects the low charge current state, generates a relatively low quiescent current by disabling some components, and so less power is consumed. When a high load current state is detected, the voltage Vqc is set to a low value so that all components disabled for the low charge state are quickly enabled for full operation.
Des modes de réalisation de l'invention prévoient un régulateur de tension à faible tension de déchet comprenant un transistor de régulation pour fournir une tension de sortie régulée à partir d'une tension d'entrée, un étage de contrôle de grille comprenant un circuit de résistance de grille de polarisation à l'état haut et un transistor de contrôle, pour fournir une tension de grille au transistor de régulation, un amplificateur d'erreur pour fournir une tension de contrôle à une borne de contrôle du transistor de contrôle, et un circuit de contrôle de courant de repos pour limiter un courant de repos circulant à travers l'étage de contrôle de grille lorsque la tension d'entrée s'approche de la tension de sortie et fait entrer le transistor de régulation dans un mode de conduction ohmique. Le circuit de contrôle de courant de repos comprend une source de courant fournissant un courant de référence et est configuré pour contrôler le courant de repos par effet miroir de courant basé sur le courant de référence.Embodiments of the invention provide a low voltage dropout voltage regulator comprising a regulating transistor for providing a regulated output voltage from an input voltage, a gate control stage including a gate circuit high-bias gate resistor and a control transistor, for supplying a gate voltage to the control transistor, an error amplifier for supplying a control voltage to a control transistor control terminal, and a quiescent current control circuit for limiting a quiescent current flowing through the gate control stage as the input voltage approaches the output voltage and inputs the control transistor into an ohmic conduction mode . The quiescent current control circuit includes a current source providing a current of reference and is configured to control the quiescent current by mirror effect based on the reference current.
Selon un mode de réalisation de l'invention, le circuit de contrôle de courant est également configuré pour contrôler simultanément la tension de contrôle fournie par l'amplificateur d'erreur à la borne de contrôle du transistor de contrôle.According to one embodiment of the invention, the current control circuit is also configured to simultaneously control the control voltage supplied by the error amplifier to the control terminal of the control transistor.
Selon un mode de réalisation de l'invention, le circuit de contrôle de courant comprend une sortie qui est reliée à la borne de contrôle du transistor de contrôle et est configuré pour modifier la tension de contrôle fournie par l'amplificateur d'erreur à la borne de contrôle.According to one embodiment of the invention, the current control circuit comprises an output which is connected to the control terminal of the control transistor and is configured to change the control voltage supplied by the error amplifier to the control terminal.
Selon un mode de réalisation de l'invention, le circuit de contrôle de courant de repos comprend un premier transistor présentant une première borne de conduction reliée à la source de courant, une seconde borne de conduction agencée pour recevoir la tension de sortie et une borne de contrôle agencée pour recevoir la tension de grille, et le circuit de résistance de grille comprend un transistor qui est couplé en configuration de miroir de courant avec le premier transistor du circuit de contrôle de courant de repos.According to one embodiment of the invention, the quiescent current control circuit comprises a first transistor having a first conduction terminal connected to the current source, a second conduction terminal arranged to receive the output voltage and a terminal control circuit arranged to receive the gate voltage, and the gate resistance circuit comprises a transistor which is coupled in current mirror configuration with the first transistor of the idle current control circuit.
Selon un mode de réalisation de l'invention, le régulateur de tension à faible tension de déchet comprend une branche de compensation Miller connectée entre une borne de conduction du transistor de contrôle et la première borne de conduction du transistor de contrôle.According to one embodiment of the invention, the low-voltage voltage regulator comprises a Miller compensation branch connected between a conduction terminal of the control transistor and the first conduction terminal of the control transistor.
Selon un mode de réalisation de l'invention, le circuit de contrôle de courant de repos comprend un second transistor présentant une borne de contrôle reliée à la première borne de conduction du premier transistor, une première borne de conduction reliée à la masse, et une seconde borne de conduction reliée à la borne de contrôle du transistor de contrôle.According to one embodiment of the invention, the quiescent current control circuit comprises a second transistor having a control terminal connected to the first conduction terminal of the first transistor, a first conduction terminal connected to the ground, and a second conduction terminal connected to the control terminal of the control transistor.
Selon un mode de réalisation de l'invention, le circuit de résistance de grille comprend un transistor de grille interagissant avec un transistor du circuit de contrôle de courant de repos afin de créer un miroir de courant entre le circuit de contrôle de courant de repos et l'étage de contrôle de grille.According to one embodiment of the invention, the gate resistance circuit comprises a gate transistor interacting with a transistor of the quiescent current control circuit to create a current mirror between the quiescent current control circuit and the grid control stage.
Selon un mode de réalisation de l'invention, le circuit de résistance de grille comprend également une première résistance en parallèle avec le transistor de grille et une seconde résistance en série avec la première résistance.According to one embodiment of the invention, the gate resistance circuit also comprises a first resistor in parallel with the gate transistor and a second resistor in series with the first resistor.
Selon un mode de réalisation de l'invention, le circuit de contrôle de courant de repos est configuré pour être dans un état désactivé dans lequel il ne consomme pas de courant lorsque le transistor de régulation n'est pas entré en mode de conduction ohmique.According to one embodiment of the invention, the quiescent current control circuit is configured to be in a deactivated state in which it does not consume current when the control transistor has not entered ohmic conduction mode.
Selon un mode de réalisation de l'invention, le transistor de régulation est en mode de conduction ohmique lorsque la différence de tension entre la tension d'entrée et la tension de sortie régulée est inférieure ou égale à 2,0 V.According to one embodiment of the invention, the regulation transistor is in ohmic conduction mode when the voltage difference between the input voltage and the regulated output voltage is less than or equal to 2.0 V.
Des modes de réalisation de l'invention concernent également un dispositif portable comprenant une batterie pour fournir une tension d'entrée, un circuit alimenté par une tension régulée, et un régulateur de tension à faible tension de déchet selon l'un des modes de réalisation décrits ci-dessus, pour fournir la tension de sortie régulée à partir de la tension d'entrée.Embodiments of the invention also relate to a portable device comprising a battery for providing an input voltage, a circuit powered by a regulated voltage, and a low voltage voltage regulator according to one of the embodiments. described above, to provide the regulated output voltage from the input voltage.
Un mode de réalisation d'un régulateur de tension à faible tension de déchet selon l'invention sera exposé dans la description suivante, faite à titre non limitatif en relation avec les figures jointes parmi lesquelles :
- la
figure 1 précédemment décrite illustre une structure conventionnelle d'un régulateur à faible tension de déchet ; - les
figures 2A et 2B précédemment décrites illustrent une tension et un courant caractéristiques du régulateur de lafigure 1 ; - la
figure 3 illustre un régulateur à faible tension de déchet selon un mode de réalisation de l'invention ; - la
figure 4 illustre un exemple de mise en oeuvre du régulateur de lafigure 3 ; - les
figures 5A et 5B illustrent des caractéristiques de tension et de courant du régulateur à faible tension de déchet selon un mode de réalisation de l'invention ; et - la
figure 6 illustre schématiquement un dispositif portable comprenant un régulateur à faible tension de déchet selon un mode de réalisation de l'invention.
- the
figure 1 previously described illustrates a conventional structure of a low voltage regulator of waste; - the
Figures 2A and 2B previously described illustrate a voltage and a current characteristic of the regulator of thefigure 1 ; - the
figure 3 illustrates a low voltage regulator of waste according to one embodiment of the invention; - the
figure 4 illustrates an example of implementation of the regulator of thefigure 3 ; - the
Figures 5A and 5B illustrate voltage and current characteristics of the low-loss regulator according to one embodiment of the invention; and - the
figure 6 schematically illustrates a portable device comprising a low voltage regulator waste according to one embodiment of the invention.
La
Le régulateur LDO2 comprend un transistor de régulation TREG, un étage de contrôle de grille GCS, un amplificateur d'erreur EAMP (amplificateur différentiel) et un circuit de contrôle de courant de repos CCT.The regulator LDO2 comprises a regulation transistor TREG, a gate control stage GCS, an amplifier amplifier EAMP (differential amplifier) and a current control circuit CCT.
Le transistor de régulation TREG, ici un transistor PMOS, a sa source S connectée au noeud IN et son drain D connecté au noeud OUT. La grille G du transistor est pilotée par une tension de grille Vg fournie par l'étage de contrôle de grille GCS.The regulation transistor TREG, here a PMOS transistor, has its source S connected to the node IN and its drain D connected to the node OUT. The gate G of the transistor is driven by a gate voltage Vg supplied by the GCS gate control stage.
L'étage de contrôle de grille GCS comprend un circuit de résistance de grille RG10 et un transistor de contrôle TQ, ici un transistor bipolaire NPN. Le circuit de résistance RG10 présente une borne connectée au noeud d'entrée IN et une borne connectée à la grille G du transistor TREG. Le transistor TQ présente un collecteur C connecté à la grille G du transistor TREG et un émetteur E relié à la masse (GND) par une résistance RG2.The GCS gate control stage comprises a gate resistance circuit RG10 and a control transistor TQ, here an NPN bipolar transistor. The resistance circuit RG10 has a terminal connected to the input node IN and a terminal connected to the gate G of the transistor TREG. The transistor TQ has a collector C connected to the gate G of the transistor TREG and a transmitter E connected to ground (GND) by a resistor RG2.
La base B du transistor TQ reçoit une tension de contrôle Vc fournie par l'amplificateur d'erreur EAMP. L'amplificateur EAMP comprend une entrée négative et une entrée positive. L'entrée négative reçoit une tension stable Vref fournie par une source de tension stable BG, telle qu'une source de tension à bande interdite. L'entrée positive reçoit une tension de rétroaction Vf. La tension de rétroaction est un pourcentage de la tension de sortie Vreg fournie par un diviseur de tension comprenant des résistances R1, R2.The base B of the transistor TQ receives a control voltage Vc supplied by the error amplifier EAMP. The EAMP amplifier includes a negative input and a positive input. The negative input receives a stable voltage Vref provided by a stable voltage source BG, such as a bandgap voltage source. The positive input receives a feedback voltage Vf. The feedback voltage is a percentage of the output voltage Vreg provided by a voltage divider comprising resistors R1, R2.
L'amplificateur d'erreur compare la tension de référence Vref et la tension de rétroaction Vf, et fournit la tension de contrôle Vc à l'étage de contrôle de grille GCS.The error amplifier compares the reference voltage Vref and the feedback voltage Vf, and supplies the control voltage Vc to the gate control stage GCS.
Le circuit de contrôle de courant de repos CCT présente deux entrées connectées respectivement à la grille G du transistor TREG et au noeud de sortie OUT du régulateur, et une sortie connectée à la base B du transistor TQ. Le circuit de contrôle de courant de repos CCT présente une source de courant interne CS10, et est agencé pour détecter la tension de grille Vg appliquée par l'étage de contrôle de grille GCS au transistor TREG. Lorsque la tension de grille Vg atteint une valeur qui indique que le transistor TREG est entré en mode de conduction ohmique, le circuit de contrôle de courant de repos CCT active et contrôle le courant de repos Iq traversant l'étage de contrôle de grille GCS afin d'empêcher le courant de repos d'atteindre des valeurs excessives. Egalement, le circuit de contrôle de courant de repos CCT "prend le dessus" sur l'amplificateur d'erreur EAMP et prend le contrôle de la tension Vc appliquée à la base B du transistor TQ afin de contrôler la tension de grille Vg du transistor de régulation TREG.The quiescent current control circuit CCT has two inputs respectively connected to the gate G of the transistor TREG and to the output node OUT of the regulator, and an output connected to the base B of the transistor TQ. The quiescent current control circuit CCT has an internal current source CS10, and is arranged to detect the gate voltage Vg applied by the gate control stage GCS to the transistor TREG. When the gate voltage Vg reaches a value which indicates that the transistor TREG has entered ohmic conduction mode, the quiescent current control circuit CCT activates and controls the quiescent current Iq passing through the gate control stage GCS so to prevent the quiescent current from reaching excessive values. Also, the quiescent current control circuit CCT "takes over" the error amplifier EAMP and takes control of the voltage Vc applied to the base B of the transistor TQ in order to control the gate voltage Vg of the transistor TREG regulation.
Le contrôle du courant de repos Iq par le circuit de contrôle CCT est effectué au moyen d'un mécanisme de miroir de courant entre la source de courant CS10 et l'étage de contrôle de grille GCS.The control of the quiescent current Iq by the control circuit CCT is carried out by means of a current mirror mechanism between the current source CS10 and the gate control stage GCS.
Afin de mettre en oeuvre un tel mécanisme de miroir de courant, un transistor peut être ajouté à l'étage de contrôle de grille GCS. Par exemple, un transistor PMOS TG est agencé dans le circuit de résistance de grille RG10, c'est-à-dire dans la section de tirage à l'état haut ("pull up") de l'étage de contrôle de grille GCS, qui reçoit la tension d'entrée Vin et fournit la tension de grille Vg. Dans un mode de réalisation le circuit de résistance de grille RG10 comprend deux résistances RG11, RG12 en série et un transistor TG est monté en diode en parallèle avec la résistance RG11, son drain D étant connecté à sa grille G. La résistance RG11 présente une valeur élevée, par exemple 1 MΩ, et est prévue comme une résistance de fuite pour garantir que la tension de grille Vg du transistor de régulation TREG reçoit la tension d'entrée Vin en l'absence de contrôle par l'amplificateur d'erreur, par exemple lorsque le circuit est mis sous tension. D'autre part, la résistance RG12 présente une valeur basse, par exemple 10 KΩ.In order to implement such a current mirror mechanism, a transistor may be added to the GCS gate control stage. For example, a PMOS transistor TG is arranged in the gate resistance circuit RG10, i.e. in the pull-up section of the GCS gate control stage. which receives the input voltage Vin and supplies the gate voltage Vg. In one embodiment the gate resistance circuit RG10 comprises two resistors RG11, RG12 in series and a transistor TG is diode-connected in parallel with the resistor RG11, its drain D being connected to its gate G. The resistor RG11 has a high value, for example 1 MΩ, and is provided as a leakage resistor to ensure that the gate voltage Vg of the regulating transistor TREG receives the input voltage Vin in the absence of control by the error amplifier, for example when the circuit is switched on. On the other hand, the resistance RG12 has a low value, for example 10 KΩ.
La
Le circuit de contrôle de courant de repos CCT comprend un transistor PMOS T10, un transistor NMOS T11, et la source de courant CS10. De préférence, une branche de compensation Miller comprenant par exemple une résistance R10 et un condensateur C10 peut également être prévue.The quiescent current control circuit CCT comprises a PMOS transistor T10, an NMOS transistor T11, and the current source CS10. Preferably, a branch Miller compensation comprising, for example, a resistor R10 and a capacitor C10 may also be provided.
Le transistor T10 a sa source S connectée au noeud de sortie OUT du régulateur LDO2, son drain D relié à la masse (GND) par la source de courant CS10, et sa grille G connectée à la grille G du transistor de régulation TREG afin de détecter la tension de grille Vg. Le transistor T11 a sa grille connectée au drain D du transistor T10, son drain D relié à la base B du transistor TQ, et sa source S reliée à la masse. La branche de compensation Miller, comprenant la résistance R10 et le condensateur C10, est connectée entre l'émetteur E du transistor TQ et le drain D du transistor T10.The transistor T10 has its source S connected to the output node OUT of the regulator LDO2, its drain D connected to ground (GND) by the current source CS10, and its gate G connected to the gate G of the regulation transistor TREG in order to detect the gate voltage Vg. The transistor T11 has its gate connected to the drain D of the transistor T10, its drain D connected to the base B of the transistor TQ, and its source S connected to ground. The compensation branch Miller, comprising the resistor R10 and the capacitor C10, is connected between the emitter E of the transistor TQ and the drain D of the transistor T10.
L'amplificateur d'erreur EAMP comprend de manière conventionnelle une source de courant CS1, des transistors PMOS TE1, TE2, des transistors bipolaires NPN TE3, TE4 et des résistances RE1, RE2. La source de courant CS1 présente une première borne connectée au noeud d'entrée IN du régulateur, et une seconde borne connectée aux sources S des transistors TE1, TE2. Les drains D des transistors TE1, TE2 sont respectivement connectés aux collecteurs C des transistors TE3, TE4. Les émetteurs E des transistors TE3, TE4 sont respectivement reliés à la masse par les résistances RE1, RE2. Le collecteur C du transistor TE4 est connecté à la base B du transistor TQ et fournit la tension de contrôle Vc lorsque le circuit de contrôle de courant de repos CCT est dans l'état non conducteur. Les bases B des transistors TE3, TE4 sont toutes deux connectées au collecteur C du transistor TE3. Enfin, la grille G du transistor TE1 reçoit la tension de référence Vref et la grille G du transistor TE2 reçoit la tension de rétroaction Vf.The error amplifier EAMP conventionally comprises a current source CS1, PMOS transistors TE1, TE2, NPN bipolar transistors TE3, TE4 and resistors RE1, RE2. The current source CS1 has a first terminal connected to the input node IN of the regulator, and a second terminal connected to the sources S of the transistors TE1, TE2. The drains D of the transistors TE1, TE2 are respectively connected to the collectors C of the transistors TE3, TE4. Transmitters E of transistors TE3, TE4 are respectively connected to ground by resistors RE1, RE2. The collector C of the transistor TE4 is connected to the base B of the transistor TQ and supplies the control voltage Vc when the quiescent current control circuit CCT is in the non-conductive state. The bases B of the transistors TE3, TE4 are both connected to the collector C of the transistor TE3. Finally, the gate G of the transistor TE1 receives the reference voltage Vref and the gate G of the transistor TE2 receives the feedback voltage Vf.
Le circuit de contrôle de courant de repos CCT est agencé pour surveiller la différence de tension entre la tension de grille Vg et la tension de sortie Vreg. Lorsque la différence entre la tension d'entrée Vin et la tension de sortie Vreg est importante, par exemple lorsque la source d'alimentation PS est une batterie complètement chargée, le transistor T10 du circuit de contrôle de courant de repos CCT est dans l'état non conducteur car la différence de tension Vgs entre sa grille G et sa source S est positive et par conséquent supérieure à sa tension de seuil négative (Vg>Vreg). La source de courant CS10 empêche également le transistor T11 de conduire. Par conséquent, le circuit de contrôle de courant de repos CCT est dans l'état désactivé et n'interfère pas avec le fonctionnement normal de l'amplificateur d'erreur EAMP. De plus, il ne consomme pas de courant. Le régulateur LDO2 fonctionne comme le régulateur conventionnel LDO1 de la
Lorsque la tension d'entrée Vin diminue, par exemple au fur et à mesure que la source d'alimentation PS se décharge s'il s'agit d'une batterie, l'amplificateur d'erreur EAMP essaye de maintenir la tension de sortie Vreg nécessaire, comme cela a été expliqué ci-dessus. La tension de grille Vg commence à diminuer et la différence entre la tension de grille et la tension de source du transistor T10, qui est égale à Vg-Vreg, devient négative et inférieure à sa tension de seuil négative (Vg<Vreg). Le transistor TQ est fortement conducteur et le transistor T10 commence à devenir conducteur. La source de courant CS10 impose un courant Iref par le transistor T10 et limite également le courant de repos par effet de miroir de courant.When the input voltage Vin decreases, for example as the power source PS discharges if it is a battery, the error amplifier EAMP tries to maintain the output voltage Vreg necessary, as explained above. The gate voltage Vg begins to decrease and the difference between the gate voltage and the source voltage of the transistor T10, which is equal to Vg-Vreg, becomes negative and lower than its negative threshold voltage (Vg <Vreg). The transistor TQ is highly conductive and the transistor T10 begins to become conductive. The current source CS10 imposes a current Iref by the transistor T10 and also limits the quiescent current by a current mirror effect.
Le rapport entre le courant de repos Iq contrôlé et le courant Iref est déterminé par les dimensions respectives des transistors T10 et TG, c'est-à-dire leurs rapports W/L respectifs (W étant la largeur de la grille et L étant la longueur de la grille des transistors). Par conséquent, le courant de repos ne peut dépasser une valeur fixée par le miroir de courant. La résistance R10 et le condensateur C10 aident à stabiliser le miroir de courant.The ratio between the controlled quiescent current Iq and the current Iref is determined by the respective dimensions of the transistors T10 and TG, that is to say their respective W / L ratios (W being the width of the gate and L being the length of the gate of the transistors). By therefore, the quiescent current can not exceed a value set by the current mirror. Resistor R10 and capacitor C10 help stabilize the current mirror.
Simultanément, la tension de drain du transistor T10 amène le transistor T11 à commencer à devenir conducteur, et ainsi à contrôler la tension de base Vb du transistor TQ et empêcher l'amplificateur d'erreur EAMP de tirer la tension de contrôle Vc vers le haut. La base B du transistor TQ est tirée vers la masse, et le transistor T11 régule la conduction du transistor TQ. Le transistor T11 contrôle la base B du transistor TQ afin de garantir que Iref est égal au courant traversant la source de courant CS10, de telle sorte qu'un mécanisme de régulation supplémentaire apparaît. Lorsque Iref est égal au courant traversant CS10, le courant Iq est contrôlé et est égal à Iref ou proportionnel à Iref en fonction des rapports W/L.Simultaneously, the drain voltage of the transistor T10 causes the transistor T11 to begin to become conductive, and thus to control the base voltage Vb of the transistor TQ and to prevent the error amplifier EAMP from pulling the control voltage Vc upwards. . The base B of the transistor TQ is pulled to ground, and the transistor T11 regulates the conduction of the transistor TQ. The transistor T11 controls the base B of the transistor TQ to ensure that Iref is equal to the current flowing through the current source CS10, so that an additional control mechanism appears. When Iref is equal to the through current CS10, the current Iq is controlled and is equal to Iref or proportional to Iref as a function of the W / L ratios.
A titre d'illustration, les
Une ligne verticale en pointillés indique la limite où Vin-Vreg = 0,2 V et la zone à droite de la ligne en pointillés représente une région de fonctionnement du transistor de régulation où Vin-Vreg < 0,2 V (mode de conduction ohmique). Comme dans le régulateur conventionnel LDO1, le courant de repos Iq est sensiblement constant dans la région située à gauche de la ligne en pointillés. Lorsque le mode de conduction ohmique est atteint, Vin s'approche de la valeur nominale de la tension de sortie Vreg et Vin-Vreg devient égal à 0,2 V. On peut voir que le circuit de contrôle de courant de repos CCT empêche l'étage de contrôle de grille GCS de tirer rapidement la tension de grille Vg vers le bas tout en empêchant le courant de repos Iq de diminuer de façon abrupte. Le courant de repos Iq est approximativement maintenu à la même valeur qu'il avait avant d'atteindre le mode de conduction ohmique.A dashed vertical line indicates the limit where Vin-Vreg = 0.2 V and the area to the right of the dotted line represents an operating region of the regulating transistor where Vin-Vreg <0.2 V (ohmic conduction mode ). As in the conventional regulator LDO1, the quiescent current Iq is substantially constant in the region to the left of the dashed line. When the ohmic conduction mode is reached, Vin approaches the nominal value the output voltage Vreg and Vin-Vreg becomes equal to 0.2 V. It can be seen that the quiescent current control circuit CCT prevents the gate control stage GCS from rapidly pulling the gate voltage Vg towards the gate. low while preventing the quiescent current Iq from decreasing abruptly. The quiescent current Iq is approximately maintained at the same value it had before reaching the ohmic conduction mode.
Compte tenu de ce qui précède, il sera noté que, bien que des modes de réalisation spécifiques de l'invention ont été décrits ici à des fins d'illustration, de nombreuses modifications peuvent être apportées sans pour autant s'écarter de l'esprit et de la portée de l'invention telle que définie dans les revendications jointes. En particulier, il est à la portée de l'homme de l'art d'ajouter des composants aux modes de réalisation décrits, de supprimer et de remplacer certains composants, d'utiliser un autre type de source de tension de référence plutôt qu'une référence à bande interdite, d'utiliser un type différent de transistor de régulation, de remplacer certains transistors bipolaires par des transistors MOS et vice-versa, de remplacer des transistors NPN par des transistors bipolaires PNP et vice-versa, de remplacer des transistors NMOS par des transistors PMOS et vice-versa, etc.In view of the foregoing, it will be appreciated that while specific embodiments of the invention have been described herein for purposes of illustration, many modifications may be made without departing from the spirit of the invention. and the scope of the invention as defined in the appended claims. In particular, it is within the abilities of those skilled in the art to add components to the described embodiments, to delete and replace certain components, to use another type of reference voltage source rather than to a forbidden band reference, to use a different type of regulation transistor, to replace certain bipolar transistors with MOS transistors and vice versa, to replace NPN transistors with PNP bipolar transistors and vice versa, to replace transistors NMOS by PMOS transistors and vice versa, etc.
La
Claims (11)
caractérisé en ce qu'il comprend un circuit de contrôle de courant de repos (CCT) pour limiter un courant de repos circulant dans l'étage de contrôle de grille (GCS) lorsque la tension d'entrée (Vin) s'approche de la tension de sortie (Vreg) et fait entrer le transistor de régulation (TREG) dans un mode de conduction ohmique, et en ce que le circuit de contrôle de courant de repos (CCT) comprend une source de courant (CS10) fournissant un courant de référence (Iref) et est configuré pour contrôler le courant de repos par effet miroir de courant basé sur le courant de référence (Iref).
characterized in that it comprises a quiescent current control circuit (CCT) for limiting a quiescent current flowing in the gate control stage (GCS) when the input voltage (Vin) approaches the output voltage (Vreg) and inputs the control transistor (TREG) into an ohmic conduction mode, and in that the quiescent current control circuit (CCT) comprises a current source (CS10) supplying a current of reference (Iref) and is configured to control the current mirror current based on the reference current (Iref).
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