CN114625206A

CN114625206A - Inrush current of at least one low dropout voltage regulator

Info

Publication number: CN114625206A
Application number: CN202111506242.4A
Authority: CN
Inventors: A·庞斯
Original assignee: STMicroelectronics Grenoble 2 SAS
Current assignee: STMicroelectronics Grenoble 2 SAS
Priority date: 2020-12-11
Filing date: 2021-12-10
Publication date: 2022-06-14
Anticipated expiration: 2041-12-10
Also published as: CN114625206B

Abstract

Embodiments of the present disclosure relate to an inrush current for at least one low dropout voltage regulator. The invention relates to a device comprising: n low dropout voltage regulators, N being an integer greater than or equal to 1; a first circuit configured to deliver N setpoint voltages to N regulators proportional to a same first current; and a second circuit configured to pass the first current, wherein the first current is proportional to a modulated reference current based on a sum of the inrush currents of the N regulators.

Description

Inrush current of at least one low dropout voltage regulator

Cross Reference to Related Applications

The present application claims priority from french application number FR 2023087 filed on 11/12/2020, which is incorporated herein by reference.

Technical Field

The present invention relates generally to electronic devices, and in particular embodiments, to managing inrush current of at least one low dropout voltage regulator provided in an electronic device.

Background

Electronic devices, in particular integrated electronic devices, having at least one low dropout voltage regulator (LDO) are known. When the regulator(s) are energized, each will generate an inrush current. Such inrush currents may cause problems if not controlled.

In particular, when the regulators are powered using the same supply voltage, e.g., provided by an AC/DC or DC/DC voltage converter, the inrush current drawn by the regulators may cause a change in the supply voltage, which may cause a failure, e.g., a failure of the converter that provides the supply voltage to the regulators.

It would be advantageous to overcome all or part of the disadvantages due to the inrush current of one or more low dropout voltage regulators.

Disclosure of Invention

One embodiment overcomes all or part of the disadvantages of known solutions for managing inrush current of one or more low dropout voltage regulators.

One embodiment provides an apparatus having: n low dropout voltage regulators, N being an integer greater than or equal to 1; a first circuit configured to deliver N setpoint voltages to N regulators proportional to a same first current; and a second circuit configured to pass a first current, wherein the first current is proportional to a modulated reference current based on a sum of inrush currents of the N regulators.

According to an embodiment, the second circuit is configured such that the absolute value of the first current increases when the sum decreases.

According to an embodiment, the second circuit is configured to receive a reference current and comprises a first node configured to receive a second current proportional to the reference current; and a third circuit configured to draw a third current from the first node, the third circuit configured such that the third current varies with the sum, the second circuit further configured to pass the first current, and such that the first current is proportional to a fourth current drawn from the first node.

According to an embodiment, the third circuit is configured such that the absolute value of the third current increases when the sum increases.

According to an embodiment, the second current and the third current are both positive or both negative.

According to an embodiment, the N regulators are configured to be powered with the same supply voltage.

According to an embodiment, the third circuit comprises: a second node configured to receive a supply voltage and a third node configured to receive a reference voltage; a first transistor having a drain and a gate connected together and coupled to a fourth node; a first switch coupling the fourth node to the second node; a second switch connected in series with the first transistor between the fourth node and the third node; circuitry configured to draw a current from the fourth node proportional to the reference current; for each of the N regulators, a capacitor coupling an output of the regulator to a fourth node; and a second transistor having a drain coupled to the first node, a gate connected to the fourth node, and a source coupled to the third node.

According to one embodiment, the apparatus includes a control circuit of the first switch and the second switch configured to turn off the first switch and turn on the second switch during the power-on of the N regulators.

According to one embodiment, the control circuit is further configured to turn on the first switch and turn off the second switch before energizing the N regulators.

According to one embodiment, for each regulator of the N regulators, the capacitor coupling the output of the regulator to the fourth node is at most one of 1000000, preferably one of 10000000, of equivalent capacitors of a load connected to the output of the regulator.

According to an embodiment, the size ratio of the second transistor is at least 30 times, preferably 50 times larger than the size ratio of the first transistor.

According to one embodiment, the apparatus includes a circuit configured to receive a reference current and pass a second current to a first node.

According to one embodiment, the apparatus includes a voltage converter configured to deliver a supply voltage.

According to one embodiment, the first circuit comprises a resistor for each of the N setpoint voltages, and the first circuit is configured to conduct a fifth current through the resistor proportional to the first current, the setpoint voltage being available between terminals of the resistor.

According to one embodiment, the first circuit includes a current mirror having an input branch configured to flow a current proportional to the first current through the input branch, and N output branches, each of the N output branches having one of N resistors, and each output branch configured to flow a fifth current through the resistor.

Drawings

Further advantages and features of the invention will become apparent upon review of the detailed description of embodiments and examples, which are not to be taken in any way limiting, wherein:

FIG. 1 is a schematic diagram of an embodiment apparatus having at least one low dropout voltage regulator;

FIG. 2 is a schematic circuit diagram of an embodiment of the apparatus of FIG. 1;

FIG. 3 is a schematic diagram of a portion of an embodiment of the circuit of FIG. 2; and is

Fig. 4 is a schematic diagram of another embodiment of the circuit of the device of fig. 1.

Detailed Description

Similar features have been designated by similar reference numerals in the various figures. In particular, structural and/or functional features common to various embodiments may have the same reference numbers, and may be configured with the same structural, dimensional, and material characteristics.

For clarity, only the steps and elements that are helpful in understanding the embodiments described herein have been illustrated and described in detail. In particular, various commonly used electronic circuits, in particular integrated circuits, providing at least one low dropout voltage regulator have not been detailed, the embodiments being compatible with such commonly used circuits.

Unless otherwise stated, when two elements are referred to as being connected together, this means a direct connection without any intervening elements other than a conductor, and when two elements are referred to as being coupled together, this means that the two elements can be connected or coupled through one or more other elements.

In the following disclosure, unless otherwise specified, when referring to absolute positional qualifiers, such as the terms "front", "back", "upper", "lower", "left", "right", etc., or relative positional qualifiers, such as the terms "upper", "lower", etc. Or orientation qualifiers, such as "horizontal", "vertical", etc., refer to the orientation shown in the figures.

Unless otherwise specified, "about", "approximately", "substantially" and "in" order "means within 10%, preferably within 5%.

In the following description, current is said to be drawn from a node when it flows from the node, and current is said to be supplied to the node when it flows to the node, regardless of whether the current is positive or negative.

In the following description, unless otherwise specified, when an indication signal (e.g., current or voltage) is proportional to another signal, this includes the case where the signals are equal (e.g., the same).

Fig. 1 very schematically shows, in the form of a block, an embodiment of an apparatus 1 having N low-dropout voltage regulators LDOi, i being an integer index in the range of 1 to N, N being an integer greater than or equal to 1.

In the example of fig. 1, the number N of regulators LDOi is greater than 1, for example at least equal to 3. In addition, to avoid overloading the drawing, only regulators LDO1, LDOi, and LDON are shown.

Each regulator LDOi is configured to receive a supply voltage Vdd, referred to as a reference voltage, in this example ground GND. For example, the voltage Vdd is positive.

Each regulator LDOi is configured to receive a respective set point voltage Vrefi. Each regulator LDOi is further configured to provide an output voltage Vi at a value determined by the voltage Vrefi. Voltages Vrefi and Vi are referenced to reference voltage GND, e.g., positive. For example, the voltages Vrefi are different from each other.

For example, each regulator LDOi supplies a respective load Loadi. Each load Loadi is connected to the output 100i of a respective regulator LDOi, where a voltage Vi is available. For example, each load Loadi comprises a capacitive component CLi between the node 101 at the reference voltage GND and the corresponding output 100i, or in other words each regulator LDOi sees on its output 100i the equivalent capacitance CLi of the load Loadi connected to this regulator.

Fig. 1 details an embodiment of the regulators LDO1 through LDON, only for the regulator LDON, to avoid overloading the drawing. For example, all regulators LDO1 to LDON are identical or similar, and the indices of the reference numerals used hereinafter in relation to the regulators LDON are adjusted according to the relevant regulators LDOi.

According to this exemplary embodiment, the regulator LDON comprises an error amplifier ErrAmp and a MOS (metal oxide semiconductor) transistor T controlled by the output signal of the amplifier ErrAmp. The error amplifier ErrAmp is configured such that its output signal varies with the voltage difference between the two inputs. Thus, its output signal represents such a voltage difference.

Transistor T has a conducting terminal coupled (e.g., connected) to node 102 at voltage Vdd, another conducting terminal coupled (e.g., connected) to output terminal 100N of regulator LDON, and a control terminal or gate of transistor T connected to the output of amplifier ErrAmp.

The error amplifier ErrAmp has an input configured to receive a voltage proportional to the voltage VN and another input configured to receive a voltage proportional to the voltage VrefN. The transistor T is then controlled such that the voltage difference across it can obtain the voltage VN of the desired value.

In the example of fig. 1, transistor T has N channels and has its source connected to node 102 and its drain connected to output terminal 100N. Furthermore, in the example of fig. 1, the voltage VrefN is received by the non-inverting input (+) of an amplifier ErrAmp of the regulator LDON, the inverting input (-) of which receives the voltage VN.

The device 1 further comprises a circuit 104, which circuit 104 is configured to transmit the voltages Vref1 to VrefN from the same current I1. More specifically, all voltages Vref1 through VrefN are proportional to current I1. For example, each voltage Vrefi corresponds to a voltage across a resistor that conducts a current proportional to current I1. For example, current I1 is positive.

In an embodiment, circuit 104 includes a current mirror (not shown in fig. 1) having an input branch and N output branches. Then, the input branches of the current mirror are configured such that a current proportional to the current I1 flows, and each of the N output branches comprises a resistor, and each branch is configured such that a current proportional to the current in the input branch, and thus proportional to the current I1, flows.

Current I1 is received by input terminal or node 106 of circuit 104. Each voltage Vrefi is available on a respective output terminal or node 108i of circuit 104. In other words, the circuit 104 includes N output nodes 1081, …, 108i, …, 108N that pass respective voltages Vref1, …, Vrefi, …, VrefN.

The device 1 comprises a circuit 110 configured to provide a current I1. More specifically, the circuit 110 is configured such that when the regulators LDO1 through LDON are powered on, the current I1 is proportional to the modulation reference current Iref based on the sum of the inrush currents of the N regulators LDO1 through LDON. In other words, the circuit 110 is configured to generate a current proportional to the reference current Iref and modulate or vary the generated current based on the sum of the inrush current of the regulator LDO1 to LDON. The current I1 is then proportional to the modulation current. For example, the current I1 may be obtained on the output terminal 112 of the circuit 110. Terminal 112 is preferably connected to input terminal 106 of circuit 104.

The current Iref is constant. For example, the current Iref is provided by a bandgap voltage source. The current Iref is received by input terminal 114 of circuit 110.

According to one embodiment, the circuit 110 is more specifically configured such that when the sum of the inrush currents of the regulators LDO1 to LDON is reduced when the regulators LDO1 to LDON are powered on, the current I1 is increased. Preferably, the circuit 110 is further configured such that the current I1 is zero at the very beginning of the power-on phase of the regulator LDO1 to LDON when the inrush current is maximum, the current I1 increases when the inrush current decreases, and the current I1 reaches the nominal value at the end of the power-on phase when the inrush current is zero.

Since the current I1 increases when the inrush current sum decreases, the current I1 increases more the faster the inrush current sum decreases, and thus the voltage Vref1 to VrefN increases faster. Conversely, the slower the sum of the inrush currents decreases, the slower the current I1, and the voltage Vref1 to VrefN increases. This allows the voltage Vref1 to VrefN to increase relatively slowly when the current sum is relatively high, and therefore does not further increase the inrush current. This results in a limitation of the maximum value that the sum of the inrush currents can reach.

This makes it possible, for example, to limit the maximum amplitude of the variation of the voltage Vdd caused by such inrush currents, thus avoiding malfunctioning of the electronic circuit with the device 1.

In steady state, the inrush current of the regulators LDO1 to LDON is zero, the setpoint voltages Vref1 to VrefN are determined only by the value of the current Iref, e.g., by the resistance value of the circuit 104, and the voltages Vref1 to VrefN are available on the circuit 104.

According to one embodiment, the circuit 110 is configured to generate a signal, preferably a current signal, whose value varies with the sum of the inrush current of the regulators LDO1 to LDON. For example, the circuit 110 is configured to generate the signal representing the sum of the inrush currents of the regulators LDO1 to LDON based on the output voltages V1 to VN of the regulators LDO1 to LDON. The circuit 110 then includes N terminals or input nodes 116i, each terminal or input node 116i receiving a respective voltage Vi.

According to one embodiment, the supply voltage Vdd is delivered by a voltage converter 118, for example of the AC/DC or DC/DC type, for example of the DC/DC type. The converter 118 receives a voltage Vsupply from the power supply and generates a voltage Vdd from the voltage Vsupply.

In the device 1, the voltage Vdd due to the inrush current of the regulator LDO1 to LDON has a limited amplitude, which makes it possible to avoid that the voltage Vdd reaches a low value, the converter 118 will enter a configuration mode, which causes the electronic system with the device 1 to malfunction. This also makes it possible to avoid the voltage Vdd reaching values lower than the low threshold of the converter 118, below which the converter 118 will stop passing the voltage Vdd.

To limit the inrush current of the regulators LDO1 to LDON, the circuit 100 may be throttled, making the current I1 constant and proportional to the current Iref, and providing a low pass RC filter between each terminal 108I of the circuit 104 and the respective regulator LDOi. During the power-on period of the regulator LDO1 to LDON, the voltage Vrefi will gradually increase.

However, the low-pass RC filter needs to have a relatively high time constant. This would require relatively high resistance and capacitance values, which would result in an unexpected increase in the surface area of the device 1.

Furthermore, providing a low-pass RC filter at the input of each regulator LDOi may cause instability and/or noise in the regulation of the voltage Vi by the regulator LDOi. Once steady state is established, it can be designed to short out the low pass RC filter. However, this leads to the provision of additional switches, which on the one hand lead to an unnecessary increase in the surface area of the device and on the other hand to unnecessary transients when the switch is switched on.

The above has described an embodiment where the current I1 is positive. Alternatively, current I1 may be negative, for example, by making each voltage Vrefi equal to the product of current I1 and a negative scale factor. In this case, when the sum of the inrush currents of the regulators LDO1 to LDON decreases, the absolute value of the current I1 increases. Thus, in this variant and as in the previously described embodiments, during the energization of the regulator LDO1 to LDON, the voltage Vrefi increases with a decrease in the sum of the inrush currents.

Fig. 2 shows very schematically, in block form, an embodiment of the circuit 110 of fig. 1.

The circuit 110 includes an internal node 200. Node 200 is configured to receive a current I2 proportional to the current Iref received on input terminal 114 of circuit 110. In other words, circuit 110 is configured to pass current I2 to node 200. As an example, the circuit 110 includes a current replica circuit 202 configured to generate a current I2 from the current Iref. The circuit 202 is implemented, for example, by one or more current mirrors (not shown).

The circuit 110 also includes a circuit 204. Circuit 204 is coupled (preferably connected) to node 200. Circuit 204 is configured to draw current I3 from node 200. According to one embodiment, the currents I3 and I2 are both positive, although both currents may be negative as a variant. The configuration of circuit 204 is such that the current I3 varies as a function of the sum of the inrush current of the regulator LDOi (fig. 1). Circuit 204 includes an output terminal or node 210 from which circuit 204 draws a current I3, output terminal 210 preferably being coupled to node 200.

The circuit 110 is further configured to draw a current I4 from the node 200 and to deliver a current I1 to an output terminal of the circuit 110. Specifically, the circuit 110 is configured such that the current I1 is proportional to the current I4 drawn from the node 200. For example, the circuit 110 includes a current replica circuit 206 configured to generate a current I1 from the current I4 it draws from the node 200. The circuit 206 is implemented, for example, by one or more current mirrors.

According to one embodiment, during energization of the regulator LDO1 to LDON, the circuit 204 is configured such that the absolute value of the current I3 decreases when the sum of the inrush currents decreases. Therefore, the absolute value of the current I4, which is equal to the constant current I2 minus the current I3, increases when the sum of the inrush currents decreases, whereby the absolute value of the current I1 increases when the sum of the inrush currents decreases.

For example, the circuit 204 is configured to provide a current I3 (fig. 1) from the output voltage Vi of the regulator LDOi. For example, the circuit 204 includes N inputs 2081, …, 208i, …, 208N configured to receive N respective voltages V1, …, Vi, …, VN. The inputs 208i are then coupled (e.g., connected) to respective inputs 108i of the circuit 110 (fig. 1) and thus to respective outputs 100i of the regulator LDOi.

According to one embodiment, during the energization of the regulator LDOi, the circuit 204 is configured to first draw a current I3 equal to the current I2, so that the current I1 is zero. Therefore, voltage Vrefi (fig. 1) and voltage Vi are zero. Then, when the sum of the inrush currents starts to decrease, the absolute value of the current I3 also starts to decrease, and thereby the absolute value of the current I4 starts to increase. Thus, current I1 begins to increase in absolute value, whereby voltage Vrefi begins to increase. At the end of the energization of the regulator LDOi, when steady state is reached and the inrush current is zero, the circuit 204 is configured to make the current I3 zero. The current I1 and the voltage Vrefi are then determined by the constant reference current Iref.

According to one embodiment, the circuit 204 is configured to receive a binary control signal ctrl that switches from a first binary state to a second binary state, indicating or corresponding to the energization of the regulator LDOi. The signal ctrl is provided, for example, by a control circuit (not shown) belonging to the apparatus 1 (fig. 1).

Fig. 3 schematically illustrates one embodiment of the circuit 204 of fig. 2. The circuit 204 includes, for example, a MOS transistor T1 having an N-channel with its gate and drain connected together and coupled (e.g., connected) to an internal node 300 of the circuit 204.

The circuit 204 also includes a switch SW1 coupling the node 300 to the node 102, and a switch SW2 in series with the transistor T1 between the node 300 and the node 101. In this example, switch SW2 is connected between the source of transistor T1 and node 101, and switch SW1 is connected between

nodes

102 and 300. Switches SW1 and SW2 are controlled by signal ctrl such that switches SW1 and SW2 are turned on and off, respectively, when regulator LDOi is powered down and are switched to the off and on states, respectively, when regulator LDOi is powered up, i.e., when signal ctrl switches from its first binary state to its second binary state. For example, switch SW1 is controlled by signal ctrl and switch SW2 is controlled by a binary complement of signal nctrl corresponding to signal ctrl.

The circuit 204 also includes a circuit 302 configured to draw a current Ios from the node 300. The configuration of the circuit 302 is such that the current Ios is proportional to the reference current Iref. For example, the current Ios is positive in polarity.

The circuit 204 includes a MOS transistor T2 having the same type of channel as the transistor T1. Transistor T2 has a gate connected to the gate of transistor T1 and a source connected to node 101 to which the source of transistor T1 is also coupled. Thus, transistors T1 and T2 are assembled as a current mirror. Further, the drain of the transistor T2 is coupled to the output terminal 210 of the circuit 204, for example, or in other words, the drain of the transistor T2 is coupled to the node 200 (fig. 2). Transistor T2 is configured such that a current I3 flows between its conducting terminals from node 210 to node 101.

For each regulator LDOi (fig. 1), the circuit 204 comprises a respective capacitor Ci, coupling a respective terminal 208i of the circuit 204 to the node 300, i.e. coupling the output 100i of the respective regulator LDOi to the node 300. Call Is the current provided to node 300 by the components of capacitor Ci, i.e., current Is equal to the sum of the currents in capacitors C1 through CN.

The operation of the device 1 is as follows, which is achieved by the

circuits

110 and 204 associated with fig. 2 and 3. To simplify the description of this operation, consider first the case where N is equal to 1, i.e. the case where the device 1 of fig. 1 only comprises the regulator LDO 1.

Initially, the regulator LDO1 is off, with its output voltage V1 being zero. In addition, switches SW1 and SW2 turn on and off, respectively, and the voltage at node 300 is equal to Vdd. As a result, the capacitor C1 is precharged to the voltage Vdd, the current I in the transistor T1 is zero, and the voltage Vref1 is zero.

When regulator LDO1 is powered on, signal ctrl is toggled, causing switch SW2 to be on and switch SW to be off.

In the first phase, the capacitor C1 discharges through the transistor T1 and the voltage Vdd at the node 300 gradually decreases. In this first phase, the current I in the transistor T, and thus the current I3, is relatively high, and the entire current I2 is drawn to the node 200 by the circuit 204. The current I1 is then zero, which results in a voltage Vref1 of zero.

In the second phase, which is started, for example, when the voltage of the node 300 reaches the turn-on threshold of the transistor T1, the current I starts to decrease, and the current I3 becomes smaller in absolute value than the current I2. The current I1 then begins to increase. Then, the voltage Vref1 begins to rise, the voltage V1 rises, and the regulator LDO1 draws an inrush current Irush1 from the node 102. The current Irush1 is equal to CL1 dV 1/dt. In practice, the gate-source voltage of transistor T1 varies slower than the voltage V1, and the current in capacitor C1 may be approximately C1/CL1 Irush 1. The current I Is equal to the current Is minus the current Ios, then the current I3 Is equal to n x (Is-Ios), n being the ratio of the size ratio of the transistor T2 to the size ratio of the transistor T1. In other words, the current I3 is equal to n (C1/CL1 Irush 1-Ios). Therefore, the current I3 effectively varies with the inrush current Irush1 of the regulator LDO1, and more specifically, the absolute value decreases as the inrush current Irush1 decreases.

Furthermore, in the second phase, the voltage V1 follows the voltage Vref1, which is proportional to the current I1 and therefore to I2-n (C1/CL1 Irush 1-Ios). Thus, voltage V1 is equal to K (I2-n (C1 (dV1/dt) -ions)), K being a scaling factor between voltage V1 and current I1. By solving the derivative power on V1By way of example, it is possible to obtain V1 equal to K (I2+ n Ios) (1-e)^-t/(n*K*C1)). It can be concluded that the current Irush1 is at most equal to (CL1/n C1) (I2+ n Ios).

For a given equivalent capacitance value CL1, the maximum value of the inrush current Irush1 is determined by the values of the ratio n, the capacitor C1, the current C2, and the ions.

Once steady state Is reached, i.e., voltage Vref1 reaches its nominal value, and voltage V1 equals the set point determined by the nominal value of Vref1, current Irush1 and current Is are zero. The current Ios then allows to keep the current I3 empty. Because current I3 is empty, current I1 is determined by current Iref.

An advantage of this embodiment of circuit 204 is that it is not necessary to detect the end of the energization of regulator LD1 to deactivate circuit 204, thereby forcing current I3 to a zero value.

According to one embodiment, the ratio n is chosen to be greater than or equal to 30, or even greater than or equal to 50. This achieves a relatively low maximum inrush current Irush1 by using a relatively low value of capacitor C1 (e.g., at least 10000 less than capacitor CL1, or at least 100000 less than capacitor CL 1).

In case N is greater than 1, the operation of the device 1 implemented using the

circuits

110 and 204 associated with the respective fig. 2 and 3 can be deduced from the described operation in case N is equal to 1. As previously mentioned, in case N is greater than 1, a maximum value can be selected for the sum of the inrush current of the regulator LDOi by setting the values of the ratio N, the capacitor Ci, the current I2 and the current Ios.

An embodiment in which current Is, current Ios, and current I3 are positive Is described above in connection with fig. 3. As a variant, the current Is positive, the Ios Is positive, and the current I3 Is negative. In this variant, the drain of the transistor T2 is coupled to the node 210, for example by at least one current mirror, so that the negative current I3 can be supplied from the current flowing through the transistor T2.

Fig. 4 schematically illustrates one embodiment of the circuit 104 of fig. 1. In this embodiment, the circuit 104 includes a current mirror 400 having an input branch 402 and N output branches 404 i.

The configuration of branch 402 causes a current I1' proportional to current I1 to flow through branch 402. For example, input branch 402 of current mirror 400 is also the output branch of current mirror 406, and current mirror 406 has input branch 408 coupled to input terminal 106 of circuit 104 such that current I1 flows through branch 402.

Each output branch 404I includes a respective resistor Ri, the value of which determines the respective value of voltage Vrefi by means of current I1.

More specifically, each branch 404I is configured such that current I5I flows therethrough in proportion to current I1' and thus in proportion to current I1. For example, in each branch 404I, a resistor Ri is connected between node 101 and the corresponding output of circuit 104, such that voltage Vrefi is equal to I5I × Ri.

For example, input branch 408 of current mirror 406 includes an N-channel MOS transistor T3 connected between input terminal 106 and node 101. In this example, branch 402, which is common to both current mirrors 404 and 406, includes transistor T4, which has the same type of channel as transistor T3. The transistor T4 is assembled as a mirror image of the transistor T3, i.e., here, the drain and gate of the transistor T3 are connected to each other, the source of the transistor T4 is connected to the node 101, and the gates of the transistors T3 and T4 are interconnected. Still in this example, branch 402 also includes a transistor T5, e.g., having a channel opposite the type of transistor T4, coupling transistor T4 to node 102. Each branch 404i then includes a corresponding transistor T6i coupled output 108i that branches to node 102. All transistors 1081, …, 108i, 108N are assembled as a mirror image of transistor T5, i.e., the drain and gate of transistor T5 are connected to each other, the source of transistor T5 is connected to node 102, and the gates of transistors T5 and T6i are interconnected.

Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these different embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, the skilled person will be able to modify the polarity (positive or negative) of said currents by means of various current mirrors, while maintaining the operation described for the device 1, i.e. the current I1 supplied to the circuit 104 is proportional to the current Iref modulated on the basis of the sum of the inrush currents of the regulators LDOi, so that the voltage Vrefi increases when the sum of the inrush currents decreases.

Finally, the actual implementation of the described embodiments and variants is within the abilities of a person skilled in the art based on the functional indications given above. In particular, implementation of

circuits

202, 206, and 302 is within the ability of those skilled in the art, for example, by implementing each of these circuits via one or more current mirrors.

Although the description has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims. In the various figures, like elements are designated with like reference numerals. Moreover, the scope of the present application is not intended to be limited to the particular embodiments shown herein, since those of ordinary skill in the art will readily appreciate that the processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Accordingly, the specification and figures are to be regarded only as illustrative of the invention as defined in the appended claims and are intended to cover any and all modifications, alterations, combinations, or equivalents within the scope of the invention.

Claims

1. An apparatus, comprising:

one or more low dropout voltage regulators;

a first circuit coupled to the one or more low dropout voltage regulators, the first circuit configured to deliver N setpoint voltages to the one or more low dropout voltage regulators, wherein N is a number of the one or more low dropout voltage regulators, and wherein each setpoint voltage of the N setpoint voltages is proportional to a first current; and

a second circuit coupled to the first circuit, the second circuit configured to generate the first current proportional to a reference current, the reference current modulated based on a sum of inrush current received from the one or more low dropout voltage regulators.

2. The apparatus of claim 1, wherein the second circuit is configured such that an absolute value of the first current increases in response to a decrease in a sum of the inrush currents received from the one or more low dropout voltage regulators.

3. The apparatus of claim 1, wherein the second circuit is configured to receive the reference current, the second circuit comprising:

a first terminal configured to receive a second current proportional to the reference current; and

a third circuit coupled to the first terminal, the third circuit configured to:

a third current is drawn from the first terminal, an

Varying the third current according to a sum of the inrush current received from the one or more low dropout voltage regulators,

wherein the second circuit is configured to pass the first current such that the first current is proportional to a fourth current drawn from the first terminal.

4. The apparatus of claim 3, wherein the third circuit is configured such that an absolute value of the third current increases in response to an increase in a sum of the inrush currents received from the one or more low dropout voltage regulators.

5. The apparatus of claim 3, wherein the second current and the third current are both positive or both negative.

6. The device of claim 1, wherein the one or more low dropout voltage regulators are configured to be powered using the same supply voltage.

7. The apparatus of claim 6, wherein the second circuit is configured to receive the reference current, the second circuit comprising:

a third circuit coupled to the first terminal, the third circuit configured to:

a third current is drawn from the first terminal, an

wherein the second circuit is configured to pass the first current such that the first current is proportional to a fourth current drawn from the first terminal, and

wherein the third circuit comprises:

a second terminal configured to receive the supply voltage,

a third terminal configured to receive a reference voltage,

a fourth terminal for the second terminal, and a fourth terminal,

a first transistor having a drain terminal and a gate terminal coupled to the fourth terminal,

a first switch configured to selectively couple the fourth terminal to the second terminal,

a second switch coupled in series with the first transistor and configured to selectively couple the fourth terminal with the third terminal,

a fourth circuit configured to draw a current from the fourth terminal proportional to the reference current,

a corresponding capacitor for each of the one or more low dropout voltage regulators, each corresponding capacitor coupling an output of the corresponding low dropout voltage regulator to the fourth terminal, an

A second transistor comprising:

a drain terminal coupled to the first terminal,

a gate terminal coupled to the fourth terminal, an

A source terminal coupled to the third terminal.

8. The apparatus of claim 7, further comprising a control circuit coupled to the first switch and the second switch, the control circuit configured to turn off the first switch and turn on the second switch during power-up of the one or more low dropout voltage regulators.

9. The apparatus of claim 8, wherein the control circuit is further configured to turn on the first switch and turn off the second switch before the one or more low dropout voltage regulators are powered on.

10. The apparatus of claim 7, wherein a value of each respective capacitor coupled to an output of a respective low dropout voltage regulator is one of at most 1000000 of a value of a capacitor of a load coupled to the output of the respective low dropout voltage regulator.

11. The apparatus of claim 7, wherein a value of a respective capacitor coupled to an output of a respective low dropout voltage regulator is one of at most 10000000 of a value of a capacitor of a load coupled to the output of the respective low dropout voltage regulator.

12. The apparatus of claim 7, wherein a size ratio of the second transistor is at least 30 times greater than a size ratio of the first transistor.

13. The apparatus of claim 7, wherein a size ratio of the second transistor is at least 50 times larger than a size ratio of the first transistor.

14. The apparatus of claim 6, further comprising a voltage converter configured to pass the supply voltage.

15. The apparatus of claim 1, wherein the first circuit comprises a corresponding resistor for each low-dropout regulator of the one or more low-dropout voltage regulators, wherein each respective resistor is configured to conduct a fifth current proportional to the first current, and wherein each setpoint voltage is available between terminals of each respective resistor.

16. The apparatus of claim 15, wherein the first circuit comprises a current mirror circuit comprising an input leg and N output legs, wherein the input leg is configured to flow a current proportional to the first current through the input leg, and wherein each output leg includes one of each respective resistor, and is configured to flow the fifth current through each respective resistor, and wherein N is equal to a number of one or more low-dropout voltage regulators.

17. An integrated circuit, comprising:

one or more low dropout voltage regulators;

a second circuit coupled to the first circuit, the second circuit configured to generate the first current proportional to a reference current, the reference current modulated based on a sum of inrush currents received from the one or more low dropout voltage regulators.

18. The integrated circuit of claim 17, wherein the one or more low-dropout voltage regulators are configured to power on using the same supply voltage, and wherein the second circuit is configured to receive the reference current, the second circuit comprising:

a third circuit coupled to the first terminal, the third circuit configured to:

a third current is drawn from the first terminal, an

wherein the third circuit comprises:

a second terminal configured to receive the supply voltage,

a third terminal configured to receive a reference voltage,

a fourth terminal for the second terminal, and a fourth terminal,

A second transistor comprising:

a drain terminal coupled to the first terminal,

a gate terminal coupled to the fourth terminal, an

A source terminal coupled to the third terminal.

19. A method, comprising:

passing, by a first circuit, N setpoint voltages to one or more low dropout voltage regulators, N being a number of the one or more low dropout voltage regulators, and each of the N setpoint voltages being proportional to a first current; and

generating, by a second circuit, the first current proportional to a reference current, the reference current modulated based on a sum of inrush currents received from the one or more low dropout voltage regulators.

20. The method of claim 19, further comprising:

receiving, by the second circuit, the reference current;

receiving, by a first terminal of the second circuit, a second current proportional to the reference current;

drawing a third current from the first terminal through a third circuit coupled to the first terminal; and

changing, by the third circuit, the third current according to a sum of the inrush current received from the one or more low dropout voltage regulators; and

passing the first current through the second circuit such that the first current is proportional to a fourth current drawn from the first terminal.