EP1348320A1 - Procede de fabrication de structures electroconductrices - Google Patents

Procede de fabrication de structures electroconductrices

Info

Publication number
EP1348320A1
EP1348320A1 EP02726979A EP02726979A EP1348320A1 EP 1348320 A1 EP1348320 A1 EP 1348320A1 EP 02726979 A EP02726979 A EP 02726979A EP 02726979 A EP02726979 A EP 02726979A EP 1348320 A1 EP1348320 A1 EP 1348320A1
Authority
EP
European Patent Office
Prior art keywords
depressions
substrate
structures
acid
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02726979A
Other languages
German (de)
English (en)
Inventor
Philippe Steiert
Silke Walz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elmicron AG
Original Assignee
Elmicron AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/CH2001/000004 external-priority patent/WO2001050825A1/fr
Application filed by Elmicron AG filed Critical Elmicron AG
Publication of EP1348320A1 publication Critical patent/EP1348320A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2072—Anchoring, i.e. one structure gripping into another
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0353—Making conductive layer thin, e.g. by etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating

Definitions

  • the invention is concerned with the filling of depressions in plastics with metal for technical purposes.
  • Processes for filling recesses in plastics have uses in the field of the production of electrical connecting elements, for example printed circuit boards, also flexible printed circuit boards, high-density interconnects, ball grid array (BGA) substrates, chip scale packages (CSP), Multi-chip module (MCM) substrates etc. They can also be used for semiconductor devices, other elements such as micro planar coils, micro relays etc.
  • the invention relates to a method according to the first claim.
  • the subject matter of this patent application also includes a connecting element and a semifinished product according to the further independent claims.
  • US Pat. No. 6,005,198 describes a process for producing printed circuit boards which, among other things, provides for the simultaneous pressing of U-shaped grooves and cup-shaped depressions into an insulating and preferably thermosetting substrate by means of an embossing tool.
  • material In order to form blind holes for the electrical connection of two conductor layers from the cup-shaped depressions, material then has to be removed chemically or mechanically. The channels and the depressions are then metallized. This is done, for example, by pressing a conductive paste into the recesses using a rubber roller.
  • the entire substrate can also be coated and then insulating material (etch resist) can be introduced into the depressions using a rubber roller.
  • the metal layer present in the depressions is protected on the basis of the etching resist.
  • This process saves some processing steps.
  • the process still requires several wet chemical processes. Due to the relatively wide U-shape required for the functionality of the method In addition, there are limits to miniaturization.
  • the conductor tracks either consist of relatively little conductive, hardenable paste ("conductive ink”) or they are comparatively thin. For this reason, the reliability that can be achieved and the power that can be transmitted by the conductor tracks are limited.
  • US Pat. No. 6,035,527 discloses a novel method for manufacturing printed circuit boards.
  • a first step depressions for conductor tracks are formed in a substrate.
  • a homogeneous deposition of conductive material for example by a chemical vapor deposition process.
  • conductor material is removed again, with some conductor material remaining in the depressions, which forms conductor tracks.
  • US Pat. No. 4,651,417 describes a printed circuit board production method in which recesses for the conductor tracks are mechanically introduced into a substrate. The substrate is then coated homogeneously with material, for which a vacuum deposition process, namely a "magnetically enhanced sputtering" process, is used. Finally, the conductor material is ground off again from the substrate surface, with conductor material remaining in the depressions and forming the conductor tracks achieved layer thicknesses are not sufficient, material can also be galvanically deposited.
  • US Pat. No. 4,912,844 describes a method for producing printed circuit boards according to which channels for printed conductors are pressed into a substrate and then filled up with solder.
  • British Laid-Open Specification 2 212 331 and Japanese Patent Application 11 146698 each show a process for producing printed circuit boards made of plastic, where a pattern of depressions is pressed into deformable plastic and a conductor paste is then pressed into the depressions.
  • the object of the invention is to provide a method for producing electrically conductive structures using depressions in a substrate.
  • the method should enable the structures such as conductor tracks and through holes to have the smallest possible lateral dimensions. Compared to the state of the art, however, the reliability and performance of the structures must not decrease. In the case of conductor tracks, there is therefore the requirement that, compared to existing systems, they have less flat cross-sectional portions in relation to the surface, i.e. should have a sufficient depth in the substrate.
  • the manufacturing process should be economical and feasible with equipment based on existing technology.
  • the process is essentially characterized in that recesses for conductor structures are made and galvanically filled.
  • conductor material may be removed from the locations between the conductor tracks.
  • Galvanic processes are quick and efficient.
  • the galvanically applied conductor structures can be made of copper, for example; the material of the structures obtained has a high specific conductivity. Nevertheless, the galvanic filling of conductor track structures has never been considered. An essential reason for this is shown in FIG. 1b. The figure shows the so-called "blow hole” formation.
  • the lines 41 "show the course of the surface with different amounts of applied material.
  • US Pat. No. 6,211,071 deals with the usual galvanic filling of structures with a characteristic size of 2 ⁇ m or less for the production of integrated circuits without specific information. No statements are made as to whether “pulse plating” or “reverse pulse plating” etc. is used. To prevent the formation of “voids”, it is proposed there that the edges of the depressions are chamfered, with which a larger aspect ratio can be achieved. However, one disadvantage is that the chamfers again require a large area (conductor width) The bevelling is not easy from a manufacturing point of view, and would be difficult to transfer to printed circuit boards. In addition, the dimensions are in the range of 0.1 ⁇ m.
  • the wafer must be planarized chemically and mechanically after filling.
  • the method according to the invention is based on the knowledge that it is possible to also form depressions with steep (“vertical” or essentially parallel) walls, with aspect ratios of 1: 5 to 5: 1 or more and with dimensions of less than approx.
  • the finding that the galvanic filling of essentially channel-shaped, ie elongated depressions with such aspect ratios is possible is surprising.
  • the relationship between structure depth and the total material deposited during electroplating can also be surprisingly favorable.
  • An important finding is the use of copper or other electrolytes, such as those used in decorative electroplating. It has surprisingly been found that such electrolytes are outstandingly suitable for filling void-free depressions to form conductor structures.
  • the method according to the invention is essentially characterized in that depressions in an electrically insulating substrate are completely galvanically filled or free of voids after being coated with a first conductive layer (“seed layer”.
  • the depressions have an aspect ratio of 1: 5 to 5 : 1, preferably between 2; 3 and 2.5: 1 a width of between 5 ⁇ m and several 100 ⁇ m, preferably between 10 ⁇ m and 500 ⁇ m and for example between 15 ⁇ m and 300 ⁇ m.
  • the first conductive layer is applied to the entire substrate surface to be provided with the conductor structure.
  • the filling is then carried out by electroplating the entire substrate with conductor material until the depressions are filled with conductor material. It also attaches to the between the conductor structures lying surfaces of conductor material. After filling, there is again a wet chemical removal of conductor material until these surfaces are again free of a conductor coating.
  • a substrate is used which has been cast or sprayed with the aid of a suitable mold in such a way that the depressions are formed when casting or spraying.
  • the substrate can also be designed as a thermoset and hardened on a mold which has elevations corresponding to the depressions.
  • the substrate has been produced from a preliminary product with a flat surface.
  • the recesses are made with laser ablation, by (mechanical) milling or drilling with a micro tool, by platical shaping ("embossing”) etc.
  • the respective deepening step may have been followed by a wet chemical post-cleaning step or by a plasma cleaning step.
  • the wells are made photochemically, conventionally or with a LIGA (X-ray lithography, electroplating and impression) process (above) etc.
  • the depressions can also have been created by means of plasma ablation, with the aid of a suitable mask or protective layer.
  • the conductor structures which have been produced by filling in depressions can fulfill various functions. They can serve as conventional conductor tracks or contacts between different conductor layers in electrical connection elements (printed circuit boards, HDIs etc.). They can also form contact areas, act as impedances or serve to generate certain electrical and / or magnetic fields, etc.
  • conductor material is removed again after the recesses have been filled. This is preferably done again wet-chemically in a manner known per se. It is an essential achievement of the invention that it is possible that the conductor material layers to be removed - in the context of this description the "residual layer thickness" is thin - compared to that Dimensions of the structures. This makes the galvanic filling and also the removal step inexpensive and more environmentally friendly in comparison to the prior art.
  • a residual layer thickness of between 2 and 30 ⁇ m or even between 2 and 10 ⁇ m can be achieved if the depth and width of the filled structures are in the range from 20 to 50 ⁇ m, according to Electroplating step the surface is essentially flat or even mirror-smooth - a very astonishing result.
  • the aspect ratio (the ratio of depth to width) is between 1: 5 and 5: 1, preferably between 1: 2 and 3: 1, particularly preferably between 2: 3 and 2.5: 1 for some applications at least 1 : 1 or at least 3: 2.
  • the method according to the invention is remarkably simple and very quick and therefore economical.
  • the fact that acidic copper electrolyte solutions for (decorative) galvanic applications are inexpensive and mass-marketable has a positive effect on the attractiveness of the process.
  • a copper electrolyte from decorative electroplating with corresponding additives is used for the galvanic filling of the depressions.
  • the method can also be used with other electrolytes from coating technology, which contain additives that have a smoothing or leveling effect.
  • the invention allows simple optimization of conductor cross sections in electrical connection elements.
  • the conductor tracks can, for example, have an essentially rectangular cross section, which, however, has an aspect ratio that is significantly more favorable than in the prior art.
  • the invention also makes it possible to easily produce conductor tracks of different thicknesses.
  • power conductor tracks and signal conductor tracks can be produced on the same printed circuit board and in one processing step.
  • the electrolyte is an aqueous solution and has at least three groups of components:
  • a transition metal or noble metal salt for example a copper sulfate, copper fluoroborate, copper acetate, copper nitrate, copper cyanide, etc.
  • B. acid for example. Sulfuric acid, a sulfonic acid, fluoroboric acid, sulfamic acid, hydrochloric acid etc.
  • Organic additives such as, for example, sulfur-containing aliphatic propanesulfonic acid derivatives, thiourea and derivatives, dithioalkyl acid derivatives, orthophosphoric acid, thiophosphoric acid esters, aromatic thio compounds, gelatin, molasses, phenazonium derivatives, polyalkylene glycol ether, formaldehyde, ditocarboxyl compounds, dithiocarbonyl compound, dithiocarbonyl compound, dithocarboxyl compounds, id compounds, succinic acid compounds, sulfosuccinic acid compounds.
  • the electrolyte can further comprise: buffering agent, an alkali or alkaline earth salt (for example NaCl), and / or other organic or inorganic additives.
  • buffering agent for example NaCl
  • alkali or alkaline earth salt for example NaCl
  • Figures 2a, 2b and 3 is a very schematic representation of the procedure according to the invention, using a cross section perpendicular to
  • FIG. 4 shows a schematic plan view of a container cut along a horizontal plane for carrying out the galvanic process step as a batch process
  • FIG. 4c shows a vertical section through the arrangement of FIG. 4,
  • FIG. 5 shows very schematically an example of an arrangement for performing the galvanic coating / filling as a continuous process
  • FIG. 6 shows a diagram for the electrolyte circuit according to a special variant
  • FIGS. 7 to 10 schematically show a selection of methods for making depressions in electrically insulating plates
  • FIGS. 12a, 12b and 12c sections through a region of an embodiment of the electrical connecting element according to the invention during various stages of manufacture
  • FIGS. 13a, 13b and 13c sections through a region of a further embodiment of the electrical connecting element according to the invention during various stages of manufacture.
  • FIGS. 2a and 2b show a substrate 101 with depressions which are filled in according to the exemplary embodiment of the invention.
  • a coating with a thin conductor layer is applied to the substrate 101.
  • “thin” means a small thickness in comparison with the characteristic dimensions of the depressions, for example approx. 50-500 nm, 100-300 nm, 150-250 nm etc., that is to say for example between one thousandth and a few hundredths
  • the width of a typical depression can be applied, for example, in a vacuum chamber by means of sputtering.
  • the coating material is preferred Copper is used, but other conductor materials such as silver, chromium, titanium, etc. are possible .. With certain polymer materials, copper can be applied directly without problems with the adhesive strength. In other cases, so-called adhesive layers made of chromium, titanium or tungsten must first be deposited In a second step, Ku horse upset. In such a case sets. the thin conductor layer is composed of two or possibly more metallic layers.
  • the wells are then filled galvanically.
  • the lines 41 represent the surface of the conductor layer 103 during various stages of the electroplating. As can be clearly seen from the figure, a flat surface is reached very quickly.
  • the dashed line in the figures represents the surface plane of the substrate.
  • the sizes b and t represent the width and depth of the depression, respectively.
  • any other cross sections for the depressions that can be provided with an embossing stamp are also conceivable.
  • the residual layer thickness r ie the thickness of the material applied at the points on the surface where the final or Intermediate product should be free of conductor material. It has been shown that depending on the electrolyte and the electroplating process, the remaining layer thickness, ideally between 10 ⁇ m and 30 microns, between 10 ⁇ m and 20 microns or even between 10 ⁇ m and 15 can be kept microns. This applies in a broad range of dimensions of the recesses of between 20 ⁇ m and 50 microns, practically independent of the size of the recesses.
  • the condition r ⁇ t usually also r ⁇ 2t, can often be met without any problems.
  • Electroplating process for example, no "reverse pulse plating" is used, ie the polarity is not reversed or, for example, reversed at most twice during the electroplating process.
  • the materials used are copper, but in principle also other conductor materials, for example silver.
  • the electroplating step is discussed in more detail below After the processing step, the substrate layer has a plating that fills the depressions and also covers the entire substrate.
  • the plating is removed until the conductor material 103 'is only present at the points at which it is provided, for example in depressions for conductor tracks, through holes and at contact points.
  • the removal can take place wet-chemically by etching. This can be done in a manner known per se, for example in a chemical bath or by spraying with an etching solution.
  • etching As an alternative to etching, however, other removal methods can also be used, for example mechanical removal methods such as fine grinding “flaps” or other chemical or physical removal methods.
  • FIG. 4 schematizes the top view of a device for electroplating in a vertical arrangement.
  • FIG. 4c shows a section along the line CC of FIG. 4.
  • the device has a container 51 in which two anode rods 53 are attached peripherally and a cathode rod 55 is attached centrally.
  • the cathode rod serves to hold and contact a steel plate 56 with an opening 56a shown in FIG. 4a in front view and on a reduced scale.
  • the opening 56a is provided with a clamping device 56b, which serves to hold the coated substrate.
  • a diaphragm 57 and an aperture 59 are also provided.
  • the diaphragm 57 serves to ensure that no anode sludge 60 gets into the electrolyte surrounding the cathode.
  • the diaphragm is used for laterally limited shielding of currents or electrical fields (see Figure 4b).
  • means 61 designed as perforated dielectric tubes are provided, through which the air injection necessary for each acidic copper electrolyte takes place.
  • pumping and filtering means are not yet shown, through which the electrolyte is removed, filtered and returned to the container.
  • the electrolyte circulation caused by these agents is, for example, 3 to 5 times the electrolyte volume per hour.
  • the electrolyte has the following components: sulfuric acid (H 2 SO 4 ): 10-200 g / L copper sulfate (CuSO 4 x 5 H 2 O): 50-500 g / L sodium chloride (NaCl): 10-250 mg / L, as well as the organic additives:
  • the same compositions are used for the inorganic components as for the first embodiment: sulfuric acid (H 2 SO 4 ): 10-200 g / L, preferably 45-70 g / L and, for example, 45-60 g / L copper sulfate (CuSO 4 x 5 H 2 O): 50-500 g / L, preferably 200-230 g / L and for example 210-230 g / L
  • the organic components are provided in the (conventionally decorative electroplating) HSO C-OF process from Schmidt in Solingen (DE).
  • Sulfuric acid H 2 SO 4 : 10-200 g / L, preferably 45-70 g / L and for example 50- 60 g / L
  • Organic components Novostar-ER from Enthone OMI in Germany - preparation solution 1-6 mL / L, preferably 1.5-5 mL / L and for example 2-4.5 mL / L; Level 0.05-1.0 mL / L preferably 0.1-0.7 mL / L and e.g. 0.2-0.5 mL / L, gloss support 0.05-1.0 mL / L preferably 0, 2-1.0 mL / L and e.g. 0.3-0.8 mL / L.
  • Copper sulfate 50-500 g / L, preferably 170-210 g / L, e.g. 190-205 g / L, Sulfur drinkers: 10-200 g / L, preferably 30-80 g / L, e.g. 30-50 g / L,
  • Chloride ions 50-150 mg / L, preferably 70-120 mg / L, e.g. 80-100 mg / L.
  • Carrier Copper Gleam BL 1-10 mL / L, preferably 2.5-5.0 mL / L, e.g. 2.8- 4.0 mL / L.
  • Leveler Copper Gleam BL 1-10 mL / L, preferably 1.5 mL / L, e.g. 1.5-3.0 mL / L.
  • a perfectly cleaned electrolyte tub is filled to up to 70% of the final volume with deionized water.
  • Inorganic salts such as copper sulfate are added and dissolved without residue. Alternatively, a highly concentrated solution of the salts can be used become. With copper sulfate, for example, a solution of 300 g / L copper sulfate can be used.
  • FIG. 5 also shows a device for carrying out the exemplary embodiment of the galvanic filling according to the invention as a continuous process.
  • a horizontal arrangement is shown very schematically. However, more complicated arrangements with deflection rollers etc. are also conceivable, especially in large systems.
  • the substrate 1 (with coating) functioning as cathode is, for example, designed as a bendable film as described above and is stretched by rolling. For example, it is moved throughout the process and drawn through the electrolyte container in a horizontal direction.
  • the anodes 53 ' are attached above and below or on both sides of the substrate.
  • the device has air inflow means and depending on that Diaphragms and panels, which will not be described again here.
  • nozzles (not shown) are provided for the constant generation of an electrolyte flow. This flow - symbolized by arrows in the figure - prevents the electrolyte from becoming locally poor near the cathode over time.
  • FIG. 6 A diagram of a variant for carrying out the method according to the invention is shown in FIG. 6.
  • the copper deposition process takes place on the coated substrate in an electrolysis cell 51 ", which is separated from a container 63" in which copper is brought into solution from the solid state in the electrolyte.
  • electrolysis cell 51 " which is separated from a container 63" in which copper is brought into solution from the solid state in the electrolyte.
  • electrolyte depleted electrolyte is transported from the electrolysis 'cell 51' into the container 63 "and with copper rich electrolyte from the reservoir to the electrolysis cell.
  • the substrate 1 of FIG. 7 is plastically deformed by an embossing step using an embossing tool 21, so that the depressions are formed.
  • thermoplastics and also thermosets exist, which are outstandingly suitable for embossing printed circuit board substrates.
  • suitable, piatically deformable materials are liquid crystal polymers (LCPs).
  • LCPs liquid crystal polymers
  • Other possibilities are polysulfones, epoxy resins that are deformable above the glass transition temperature, certain polyesters (PEEK), polycarbonates etc.
  • the embossing step can be carried out in a vacuum chamber or in an oxygen-containing atmosphere or, for example, under a protective gas.
  • the substrate can also be produced by injection molding in molds 23, 25 which have elevations.
  • an injection channel 27 is shown schematically; the air can escape through the parting plane 29.
  • FIG. 9 indicates that the depressions in substrate 1 can also be produced by laser ablation.
  • a laser light source 31 is indicated very schematically in the figure.
  • the substrate is covered with a structured resist layer 33 in a first step.
  • the structuring takes place, for example, in a conventional manner.
  • the depressions are then made wet-chemically or by etching.
  • the method according to the invention is particularly suitable for producing fine structures with high aspect ratios between 1: 5 and 3: 1 or> 2: 3, since the depth of the channels is also limited by the thickness of the dielectric used. Since the thickness is in the range of 10-200 micrometers, for example, the conductor channels usually have widths between 5 or 10 and a maximum of a few 100 micrometers. In printed circuit board applications, especially the finest conductor runs are very easy and economical to manufacture. In practically all applications, however, larger areas covered with metal are also necessary. For example, the connection areas for the components to be soldered to the circuit board are usually relatively large and the power supply conductors (Vcc and GND) often have to be flat.
  • Vcc and GND power supply conductors
  • FIG. 12a shows a substrate 201 after the embossing step. The same substrate is shown in FIG. 12b, it being provided with a copper layer 203 after the coating and the electroplating step is. After etching back, according to FIG. 12c, copper 203 'remains only in the vicinity of steps and in the depressions.
  • stamping step can also be accomplished by stamping via rotating rollers (“roller stamping”).
  • the post-cleaning or post-treatment step takes place, for example, with plasma etching. Alternatively, a wet chemical process would also be conceivable.
  • the area to be formed as a contact area is rastered into fine structures. This can be accomplished, for example, by fine channels running in parallel or intersecting with an aspect ratio that is optimal for the method according to the invention. In such a case, power supply levels or screen levels can be produced very well, since these are also used in conventional applications mostly rasterized. If, however, connection surfaces for soldering are to be produced, the rasterized surfaces would not allow good soldering quality and the method must be modified in such a way that closed soldering surfaces can be formed.
  • FIGS. 12a, 12b and 12c where, analogously to FIGS. 11a to 11c, an electrical connecting element is shown after the embossing step, after the electroplating step or after the etching back. It consists of rastering the flat areas with very fine structures 301a, which were added to the substrate 301 during the embossing step. These structures have depressions and elevations in between. The depth of these structures, i.e. the depressions are below T / 2, for example, if T represents the depth of the channel-shaped depressions for conductor tracks. This leads to an artificial thickening of the copper in these fine screen zones and after the copper has been thinned, a closed residual layer 303a 'remains.
  • the screening can be done in a variety of ways, e.g. parallel tracks, crossing tracks etc.
  • This effect can also be achieved by producing an embossing tool which, in addition to the fine structures with depressions and elevations in between, also contains larger, flat structures.
  • a corresponding electrical connecting element is shown in FIGS. 13a, 13b and 13c during various stages of manufacture.
  • the fine structures are quickly filled in and then the flat structures are electroplated. In total, this results in a slightly thicker copper layer in these flat areas, and after the copper has been thinned, a closed residual layer 403a 'remains, ie the elevations are also covered with copper after the etching back step. Scanning the flat areas for soldering areas also has the advantage that the copper layer is mechanically firmly anchored on the dielectric, as a result of which the adhesive strength of the soldering areas can be greatly increased.
  • the product of the method is a finished connecting element.
  • further processing steps can also be undertaken to complete an electrical connecting element.
  • the method is also suitable for the production of semi-finished products for further processing into a connecting element.
  • Such a semi-finished product can be processed, for example, with other components to form a multilayer electrical connecting element.
  • Electrical connecting elements which can be produced using the method according to the invention can have a large number of possible configurations and can generally be used in areas in which electrical connecting elements are used.
  • a connecting element according to the invention is of course outstandingly suitable for applications in which miniaturization is well advanced.
  • use in which the current carrying capacity of the conductor tracks is essential are favored by the fact that As described above, a connecting element according to the invention can have webs with a particularly favorable cross section.
  • An essential finding of the invention is the possibility of galvanically filling (“micro”) structures with widths in the range between approximately 10 ⁇ m and 100 ⁇ m, in some cases also of significantly wider structures.
  • the method according to the invention can also be supplemented with method steps which are based on methods of coating known per se.
  • the invention includes methods which include a method step or sub-step which a) is based on conventional circuit board electroplating b) on pulse-plating or reverse-pulse-plating, or c) on another conventional electroplating method.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

L'invention concerne un procédé de fabrication de structures électroconductrices, selon lequel on produit ou on prépare un substrat électro-isolant (101) de telle sorte qu'il présente une surface présentant des creux aux emplacements auxquels les structures électroconductrices doivent être formées. Au moins certains de ces creux présentent, perpendiculairement à une surface du substrat (101), une section dans laquelle le rapport profondeur (t)/largeur (b) des structures est compris entre 1:5 et 5:1, ce rapport pouvant être par exemple d'au moins 2:3. La surface du substrat est pourvue d'une couche électroconductrice qui est mince si on compare avec les dimensions caractéristiques des creux. Ensuite, la surface du substrat est soumise à une galvanoplastie jusqu'à ce que les creux soient remplis.
EP02726979A 2001-01-04 2002-01-03 Procede de fabrication de structures electroconductrices Withdrawn EP1348320A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
PCT/CH2001/000004 WO2001050825A1 (fr) 2000-01-04 2001-01-04 Procede, installation et dispositif permettant de produire un element de connexion electrique, element de connexion electrique et demi-produit
WOPCT/CH01/00004 2001-01-04
CH123201 2001-07-04
CH12322001 2001-07-04
PCT/CH2002/000001 WO2002054840A1 (fr) 2001-01-04 2002-01-03 Procede de fabrication de structures electroconductrices

Publications (1)

Publication Number Publication Date
EP1348320A1 true EP1348320A1 (fr) 2003-10-01

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Application Number Title Priority Date Filing Date
EP02726979A Withdrawn EP1348320A1 (fr) 2001-01-04 2002-01-03 Procede de fabrication de structures electroconductrices

Country Status (3)

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EP (1) EP1348320A1 (fr)
JP (1) JP2005501394A (fr)
WO (1) WO2002054840A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005191408A (ja) * 2003-12-26 2005-07-14 Matsushita Electric Ind Co Ltd コイル導電体とその製造方法およびこれを用いた電子部品
EP2320718A4 (fr) 2008-08-19 2017-08-02 Murata Manufacturing Co. Ltd. Module de circuit et son procédé de fabrication
CN103409052A (zh) * 2013-07-23 2013-11-27 吴江龙硕金属制品有限公司 用于汽车的金属面漆及其制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3434939A (en) * 1965-10-07 1969-03-25 Fabri Tek Inc Process for making printed circuits
US3438127A (en) * 1965-10-21 1969-04-15 Friden Inc Manufacture of circuit modules using etched molds
US4510347A (en) * 1982-12-06 1985-04-09 Fine Particles Technology Corporation Formation of narrow conductive paths on a substrate
DE3721985A1 (de) * 1987-06-30 1989-01-12 Schering Ag Waessriges saures bad zur galvanischen abscheidung glaenzender und eingeebneter kupferueberzuege
JP3361556B2 (ja) * 1992-09-25 2003-01-07 日本メクトロン株式会社 回路配線パタ−ンの形成法
US5764119A (en) * 1995-10-16 1998-06-09 Kabushiki Kaisha Toshiba Wiring board for high-frequency signals and semiconductor module for high-frequency signals using the wiring board
US6024857A (en) * 1997-10-08 2000-02-15 Novellus Systems, Inc. Electroplating additive for filling sub-micron features
US5968333A (en) * 1998-04-07 1999-10-19 Advanced Micro Devices, Inc. Method of electroplating a copper or copper alloy interconnect

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO02054840A1 *

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WO2002054840A1 (fr) 2002-07-11
JP2005501394A (ja) 2005-01-13

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