EP1334432A1 - Systeme de communication pour echanger des donnees au moyen d'un processeur supplementaire - Google Patents

Systeme de communication pour echanger des donnees au moyen d'un processeur supplementaire

Info

Publication number
EP1334432A1
EP1334432A1 EP01993881A EP01993881A EP1334432A1 EP 1334432 A1 EP1334432 A1 EP 1334432A1 EP 01993881 A EP01993881 A EP 01993881A EP 01993881 A EP01993881 A EP 01993881A EP 1334432 A1 EP1334432 A1 EP 1334432A1
Authority
EP
European Patent Office
Prior art keywords
data
cpu
communication system
processor
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP01993881A
Other languages
German (de)
English (en)
Inventor
Denis Archambaud
Peter Schneider
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1334432A1 publication Critical patent/EP1334432A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Definitions

  • the invention relates to a communication system for exchanging data according to the preamble of patent claim 1.
  • a software-controlled solution to tasks has the advantage that they can be easily and flexibly adapted to changing requirements.
  • the reasons for a necessary adjustment can be, for example, an additionally required property, an incorrect behavior of the remote site or an incorrect behavior of the own site.
  • a software-related solution generally also does not require any additional chip area, although at most an increased memory requirement is necessary, but this usually requires less additional area than a hardware-related solution.
  • the more that is done in software the lower the complexity of the hardware. Accordingly, the hardware becomes smaller and less prone to errors (errors in the hardware can often no longer be corrected).
  • the disadvantage of solving tasks in software is that the CPU that executes the software is burdened by this task and thus a smaller part of the CPU performance for other tasks are available. Especially when high data rates are transmitted via an interface and, of course, when several interfaces are to be operated, this can reduce the performance of the CPU to an intolerable extent, and even overwhelm the performance of the CPU.
  • the CPU In the first approach, the CPU is informed by an interrupt as soon as the desired number of bytes has been reached. The CPU must then fetch the data and process it further. Some hardware implementations make simple data processing (e.g. cutting off a start and stop bit, evaluating a parity bit) before the data is combined into bytes. The CPU is responsible for feeding the data to its destination, e.g. to make available another interface to which, for example, a display is connected.
  • a variant of this method is the use of a so-called “direct memory access” (DMA) block.
  • DMA direct memory access
  • a DMA independently transfers data (that is, without the involvement of the CPU) from the on-chip memory to the interface or from the interface to the on-chip This is triggered by the interrupt mentioned above
  • the purpose of this procedure is to reduce the number of interrupts to the CPU by first collecting a larger amount of data in the on-chip memory Add data to their destination.
  • the second approach is made possible by new on-chip systems that allow serial interfaces to work independently. Can carry out data transfers. This makes it possible to complete the processing of the data stream in hardware, ie not only serialization, but also recognition of the determination of the data and the corresponding execution of the data transfer. Disadvantages of this solution, as mentioned above, are the lack of flexibility, the difficult removal of errors and the additional space required.
  • Another disadvantage is that there is now direct access to memory and other on-chip peripherals that exist directly from the outside and are not directly perceived by the CPU.
  • EP 0 422 776 describes a communication system for serial data exchange, which consists of a microprocessor, a memory, a DMA unit and a serial interface (Serial Communication Control, SCC). These function blocks are connected to each other via a data bus. It describes how the data is received by the interface and then, under the control of the DMA unit, the address information and the message content of the data packets are written to a specified memory location in the memory via the data bus. In this phase, the interface does not supply any control signals to the microprocessor or the DMA unit.
  • the DMA unit controls the transmission of the data packets from. the interface into the memory, without checking the process and thus without the possibility of reacting to deviations from the normal process.
  • the DMA unit only delivers at the end of a data packet
  • DE 197 33 527 AI describes a communication system in which a DMA unit is in an inactive state, which characterizes an interrupt mode, for forwarding an interface control signal on the control line to the microprocessor and in a DMA -Mode characterizing, active state for forming at least one DMA control signal from the interface control signal and for supplying the DMA control signals formed on the control line to the microprocessor.
  • a serial interface for data exchange both in interrupt mode and in DMA mode
  • the control line through which the interface is connected to the controlling microprocessor is looped through the DMA unit.
  • the communication system recognizes this and can activate the DMA unit, for example software-controlled by the microprocessor. Then the DMA unit is switched into the control line and changes the interface control signals. The directly forwarded in interrupt mode control signals are interpreted and DMA control signals associated with 'which are then supplied instead to the microprocessor. With this solution, too, the microprocessor is overloaded with tasks, especially when transferring large amounts of data.
  • the communication system thus has a first processor and one or more serial interfaces for data exchange with external systems (for example external chips), the first processor and the serial interfaces being connected to a common bus line.
  • the organization and management of the data exchange is essentially carried out by a second processor, which is also connected to the common bus line and is arranged together with the first processor on one and the same chip.
  • a second processor is provided on one and the same chip, which essentially has the task of carrying out the data transfer from and to a serial interface, in particular the Management and processing of interrupt tasks.
  • Both processors can be constructed in the manner of a CPU (Central Processing Unit).
  • CPU Central Processing Unit
  • special emphasis can be placed on a quick context change and thus a shorter time to process the interrupt task than on a CPU that is not optimized for such a task.
  • Another advantage is that it is relatively easy to regulate between two intelligent on-chip CPUs which CPU is allowed to access which on-chip resources than, for example, between an internal and an external CPU. In the present invention, therefore, only a suitable regulation has to be found when the first CPU and when the second CPU are allowed to access the on-chip resources.
  • This second CPU should have full access to the on-chip system in order to relieve the first CPU independently.
  • the interrupt lines leading from the serial interfaces IF1, IF2 and IF3 to the second CPU 2 are omitted for simplification.
  • the second CPU is preferably connected to an external memory 2a arranged on the chip 10.
  • the first CPU 1 is connected to an external memory 1 a in a manner known per se.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)

Abstract

L'invention concerne un système de communication comportant, pour l'échange de données avec des systèmes externes, une ou plusieurs interfaces sérielles (IF1, IF2, IF3) reliées par une ligne de bus commune, ainsi qu'un premier processeur (1) relié à la ligne de bus commune. L'invention est caractérisée en ce que l'échange de données est essentiellement effectué par un second processeur (2), qui est relié à la ligne de bus commune et qui est disposé avec le premier processeur (1) sur une seule et même puce (10).
EP01993881A 2000-11-13 2001-10-25 Systeme de communication pour echanger des donnees au moyen d'un processeur supplementaire Ceased EP1334432A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10056198 2000-11-13
DE10056198A DE10056198A1 (de) 2000-11-13 2000-11-13 Kommunikationssystem zum Austausch von Daten unter Verwendung eines zusätzlichen Prozessors
PCT/DE2001/004081 WO2002039292A1 (fr) 2000-11-13 2001-10-25 Systeme de communication pour echanger des donnees au moyen d'un processeur supplementaire

Publications (1)

Publication Number Publication Date
EP1334432A1 true EP1334432A1 (fr) 2003-08-13

Family

ID=7663128

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01993881A Ceased EP1334432A1 (fr) 2000-11-13 2001-10-25 Systeme de communication pour echanger des donnees au moyen d'un processeur supplementaire

Country Status (6)

Country Link
US (1) US20030233506A1 (fr)
EP (1) EP1334432A1 (fr)
JP (1) JP2004513457A (fr)
CN (1) CN1474970A (fr)
DE (1) DE10056198A1 (fr)
WO (1) WO2002039292A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7206989B2 (en) 2002-11-20 2007-04-17 Intel Corporation Integrated circuit having multiple modes of operation
US7543085B2 (en) 2002-11-20 2009-06-02 Intel Corporation Integrated circuit having multiple modes of operation
US7093033B2 (en) 2003-05-20 2006-08-15 Intel Corporation Integrated circuit capable of communicating using different communication protocols
KR101033928B1 (ko) * 2008-07-01 2011-05-11 삼성전자주식회사 하이브리드 디엠에이를 이용한 고속의 데이터 처리 장치 및방법
DE102018124106A1 (de) * 2018-09-28 2020-04-02 Rockwell Collins Deutschland Gmbh Datenverarbeitungsvorrichtung mit mehreren Prozessoren und mehreren Schnittstellen

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US4603400A (en) * 1982-09-30 1986-07-29 Pitney Bowes Inc. Mailing system interface interprocessor communications channel
US4473133A (en) * 1982-12-06 1984-09-25 Westinghouse Electric Corp. Elevator system
US4713757A (en) * 1985-06-11 1987-12-15 Honeywell Inc. Data management equipment for automatic flight control systems having plural digital processors
JPS625408A (ja) * 1985-07-01 1987-01-12 Fanuc Ltd 関節形ロボツトの制御方式
JPS6434202A (en) * 1987-07-30 1989-02-03 Kubota Ltd Working wagon of automatic conduct type
US4992926A (en) * 1988-04-11 1991-02-12 Square D Company Peer-to-peer register exchange controller for industrial programmable controllers
KR0136594B1 (ko) * 1988-09-30 1998-10-01 미다 가쓰시게 단일칩 마이크로 컴퓨터
CA2022073A1 (fr) * 1989-10-11 1991-04-12 Arthur Jacob Heimsoth Appareil et methode de reception de donnees d'etat de communication serie au moyen d'un controleur a acces direct memoire
JP3415849B2 (ja) * 1995-06-07 2003-06-09 インターナショナル ビジネス マシーンズ， コーポレーション データ・バス制御装置およびプロセス
TW439380B (en) * 1995-10-09 2001-06-07 Hitachi Ltd Terminal apparatus
JP2970511B2 (ja) * 1995-12-28 1999-11-02 ヤマハ株式会社 電子楽器の制御回路
GB9622685D0 (en) * 1996-10-31 1997-01-08 Sgs Thomson Microelectronics An integrated circuit device and method of communication therewith
DE19733527A1 (de) * 1997-08-02 1999-02-04 Philips Patentverwaltung Kommunikationssystem mit einer DMA-Einheit
JPH1165989A (ja) * 1997-08-22 1999-03-09 Sony Computer Entertainment:Kk 情報処理装置
US6477177B1 (en) * 1997-11-14 2002-11-05 Agere Systems Guardian Corp. Multiple device access to serial data stream
SE520126C2 (sv) * 1997-12-11 2003-05-27 Axis Ab I/U-Processor och metod för styrning av periferienheter
US6704308B2 (en) * 1998-09-29 2004-03-09 Cisco Technology, Inc. Apparatus and method for processing signals in a plurality of digital signal processors
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Non-Patent Citations (1)

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Title
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Also Published As

Publication number Publication date
DE10056198A1 (de) 2002-02-14
US20030233506A1 (en) 2003-12-18
CN1474970A (zh) 2004-02-11
JP2004513457A (ja) 2004-04-30
WO2002039292A1 (fr) 2002-05-16

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