Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
  • C25D5/22—Electroplating combined with mechanical treatment during the deposition
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
  • C25D5/34—Pretreatment of metallic surfaces to be electroplated
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
  • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/7684—Smoothing; Planarisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
  • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Definitions

• the present invention relates generally to a semiconductor plating method and apparatus. More particularly, the present invention is directed to a method and apparatus that creates a differential between additive adsorbed on a top surface of a workpiece and additive adsorbed within a cavity portion of the workpiece using an external influence to enhance plating of a conductive material in the cavity portion of the workpiece.
• IC multi-level integrated circuits
• steps include depositing conductive and insulator materials on a semiconductor wafer or substrate followed by full or partly removal of these materials using photo-resist patterning, etching, and the like.
• the resulting surface is generally non- planar as it contains many cavities or features such as vias, lines, trenches, channels, bond-pads, and the like that come in a wide variety of dimensions and shapes.
• These features are typically filled with a highly conductive metal material before additional processing steps such as etching and/or chemical mechanical polishing (CMP) is/are performed. Accordingly, a low resistance interconnection structure is formed between the various levels/sections of the IC.
• CMP chemical mechanical polishing
• Copper (Cu) is quickly becoming the preferred material for interconnections in ICs because of its low electrical resistively and high resistance to electro-migration. Electrodeposition is one of the most popular methods for depositing Cu into the features on the substrate surface.
• U.S. Patent No. 5,516,412 issued on May 14, 1996, to Andricacos et al. discloses a vertical paddle plating cell that is designed to electrodeposit a film on a flat article.
• U.S. Patent No. 5,985,123 issued on Nov. 16, 1999, to Koon discloses yet another vertical electroplating apparatus, which purports to overcome the non-uniform deposition problems associated with varying substrate sizes.
• U.S Patent No. 5,853,559 issued on Dec. 29, 1998, to Tamaki et al. discloses an electroplating apparatus that minimizes waste of the plating electrolyte and accomplishes high recovery of the electrolyte.
• plating solutions or electrolyte are used. These solutions or electrolyte contain ionic species of Cu and additives to control the texture, morphology, and the plating behavior of the deposited material. Additives are needed to make the deposited layers smooth and somewhat shiny.
• Cu plating solution formulations There are many types of Cu plating solution formulations, some of which are commercially available.
• One such formulation includes Cu-sulfate (CuSO 4 ) as the copper source (see James Kelly et al., Journal of The Electrochemical Society, Vol. 146, pages 2540-2545, (1999)) and includes water, sulfuric acid (H 2 SO 4 ), and a small amount of chloride ions.
• CuSO 4 Cu-sulfate
• H 2 SO 4 sulfuric acid
• other chemicals can be added to the Cu plating solution to achieve desired properties of the deposited material.
• the additives in the Cu plating solution can be classified under several categories such as suppressors, levelers, brighteners, grain refiners, wetting agents, stress-reducing agents, accelerators, etc. In many instances, different classifications are often used to describe similar functions of these additives.
• solutions used in electronic applications, particularly in manufacturing ICs contain simpler additives consisting of two-component two-ingredient packages (e.g., see Robert Mikkola and Linlin Chen, "investigation of the Roles of the Additive Components for Second Generation Copper Electroplating Chemistries used for Advanced Interconnect Metallization", Proceedings of the International Interconnect Technology Conference, pages 117-119, June 5-7, 2000). These formulations are generically known as suppressors and accelerators.
• Suppressors are typically polymer formulated from polyethylene glycol-PEG or polypropylene glycol-PPG and is believed to attach themselves to the substrate surface at high current density regions, thereby forming a high resistance film and suppressing the material deposited thereon.
• Accelerators are typically organic disulfides that enhance Cu deposition on portions of the substrate surface where they are adsorbed. The interplay between these two additives and possibly the chloride ions determines the nature of the Cu deposit.
• Fig. 1 illustrates a perspective view ofa cross-section of a substrate 3 having an insulator 2 formed thereon.
• features such as a row of small vias 4a and a wide trench 4b are formed on the insulator 2 and the substrate 3.
• the vias 4a are narrow and deep; in other words, they have high aspect ratios (i.e., their depth to width ratio is large).
• the widths of the vias 4a are sub-micron.
• the trench 4b is typically wide and has a small aspect ratio. In other words, the width of the trench 4b may be five to fifty times or more greater than its depth.
• Figs. 2a -2c illustrate a conventional method for filling the features with Cu.
• Fig. 2a illustrates a cross sectional view of the substrate 3 in Fig. 1 having various layers disposed thereon.
• this figure illustrates the substrate 3 and the insulator 2 having deposited thereon a barrier/glue or adhesion layer 5 and a seed layer 6.
• the barrier layer 5 may be tantalum, nitrides of tantalum, titanium, tungsten, or TiW, etc., or combinations of any other materials that are commonly used in this field.
• the barrier layer 5 is generally deposited using any of the various sputtering methods, by chemical vapor deposition (CVD), or by electroless plating methods.
• the seed layer 6 is deposited over the barrier layer 5.
• the seed layer 6 material may be copper or copper substitutes and may be deposited on the barrier layer 5 using various sputtering methods, CVD, or electroless deposition or combinations thereof.
• a conductive material 7 (e.g., copper layer) is generally electrodeposited thereon from a suitable acidic or non-acidic plating bath or bath formulation.
• a cathodic (negative) voltage can be applied thereto with respect to an anode (not shown).
• the Cu material 7 is electrodeposited over the substrate surface using the specially formulated plating solutions, as discussed above.
• the Cu material 7 completely fills the via 4a and is generally uniform in the large trench 4b, but does not completely fill the trench 4b because the additives that are used are not operative in large features.
• the bottom up deposition into the via 4a occurs because the suppressor/inhibitor molecules attach themselves to the top of the via 4a to suppress the material growth thereabouts. These molecules can not effectively diffuse to the bottom surface of the via 4a through the narrow opening.
• Preferential adsorption of the accelerator on the bottom surface of the via 4a results in faster growth in that region, resulting in bottom-up growth and the Cu deposit profile as shown in Fig. 2b.
• Cu can grow on the vertical walls as well as the bottom surface of the via 4a at the same rate, thereby causing defects such as seams and/or voids.
• Adsorption characteristics of the suppressor and accelerator additives on the bottom surface of the large trench 4b is not expected to be any different than the adsorption characteristics on the top surface of the field regions 8 of the substrate. Therefore, the Cu thickness tl at the bottom surface of the trench 4b is about the same as the Cu thickness t2 over the field regions 8.
• Fig. 2c illustrates the resulting structure after additional Cu plating.
• the Cu thickness t3 over the field regions 8 is relatively large and there is a step si from the field regions 8 to the top of the Cu material 7 in the trench 4b.
• the Cu material 7 needs to be subjected to CMP or other material removal process so that the Cu material 7 as well as the barrier layer 5 in the field regions 8 are removed, thereby leaving the Cu material 7 only within the features.
• Fig. 4 shows a schematic depiction of an electrochemical mechanical deposition apparatus that can be used for planar or near-planar Cu deposition on a semiconductor wafer.
• a carrier head 10 holds a semiconductor wafer 16 and provides an electrical lead 17 connected to the conductive portion of the wafer 16.
• the head 10 can be rotated clockwise or counter-clockwise about a first axis 10b and can be moved in x, y, and z directions.
• a pad 18 is provided on top of an anode assembly 19, which pad 18 faces the wafer 16.
• An electrolyte 20 containing the plating material is applied to the wafer 16 surface using the anode assembly 19.
• the electrolyte 20 can be flowed through the holes/openings in the pad 18, which makes physical contact with the wafer 16 surface.
• the electrolyte 20 then flows in the narrow gap between the wafer 16 and the pad 18, eventually flowing over the edges of the pad 18 into a chamber 22 to be re-circulated (not shown) after cleaning/filtering/refurbishing.
• a second electrical lead 24 is connected to the anode assembly 19. Any other known method for providing the electric potentials to the anode assembly 19 and cathode wafer 16 can be used herein.
• the anode assembly 19 can also be rotated around a second axis 10c at controlled speeds in both the clockwise and counter-clockwise directions. It is also understood that axes 10b and 10c are substantially parallel to each other.
• the gap between the wafer 16 and the pad 18 is adjustable by moving the carrier head 10 in the z direction. When the wafer 16 surface and the pad 18 are in contact, the pressure that is exerted on the two surfaces can also be adjusted.
• a potential is applied between the electrical lead 17 to the wafer 16 and the electrical lead 24 to the anode assembly 19, making the wafer 16 surface more negative than the anode assembly 19.
• the electrolyte 20 can be introduced to the pad 18 from a reservoir (not shown) located in proximity to the anode assembly 19.
• the anode assembly 19 can have an in-channel and holes that are made therein, which together provide a path for the electrolyte 20 to be fed to the gap between the pad 18 and the wafer 16.
• the pad 18 is preferably nonconductive, hard, porous, or perforated type material so that an electric field can pass through it, while preventing shorting between the anode assembly 19 and the cathode wafer 16.
• the spacing or gap between the pad 18 and the cathode wafer 16 may range from less than 1 micron up to 2 millimeter.
• the diameter or cross sectional length of the pad 18 and the wafer 16 may range from about 5 millimeter to over 300 millimeter. The larger the wafer 16 diameter, the larger the pad 18 diameter.
• an electrolyte solution with at least one additive disposed therein is applied over the workpiece, such that the additive becomes adsorbed onto the top portion and the cavity portion of the workpiece.
• An external influence is applied so that the additive adsorbed onto the top surface is removed, and plating of the conductive material take place before the additive fully re-adsorbs onto the top portion, thereby causing greater plating of the cavity portion relative to the top portion.
• an electrolyte solution with at least one additive disposed therein is applied over the workpiece, such that the additive becomes adsorbed onto the top portion and the cavity portion of the workpiece.
• An external influence is applied so that a differential in the amount of additive that is adsorbed on the top portion relative to the cavity portion is achieved. Plating takes place while the differential still exists, thereby causing greater plating of the cavity portion relative to the top portion.
• a mask disposed between an anode and the workpiece and is movable with respect to the workpiece physically sweeps a top portion of the workpiece, thereby reducing additive adsorbed thereon, while additive adsorbed on a cavity portion remains.
• An anode that assists in creating an electric field between it and the workpiece is used to promote plating of the conductor within the electrolyte that is disposed over the workpiece.
• the mask contains an open area that is used to help define where the electric field will exist, thus allowing greater control over where plating will occur on the workpiece.
• an electrolyte solution with at least one additive disposed therein is applied over the workpiece, such that the additive becomes adsorbed onto the top portion and the cavity portion of the workpiece.
• An external influence is applied using a mask that is in spaced relation that is proximite to but does not contact the top surface of the workpiece while the workpiece and mask move relative to each other so that the additive adsorbed onto the top surface is removed or otherwise changed with respect to the additive on the cavity surface of the workpiece.
• Plating of the conductive material subsequently takes place before the additive fully re-adsorbs onto the top portion, thereby causing greater plating of the cavity portion relative to the top portion.
• Fig. 1 illustrates a perspective view of a cross section of a substrate having an insulator layer and various features formed thereon;
• Figs. 2a-2c illustrate cross sectional views of a conventional method for depositing a conductive material on the substrate of Fig. 1;
• Fig. 3 illustrates a cross sectional view ofa substrate having a conductive material deposited thereon in accordance with another conventional method;
• Fig. 4 illustrates an example of an electrochemical mechanical deposition apparatus
• Fig. 5 illustrates a conventional plating cell having an anode, cathode, and electrolyte disposed therein;
• Fig. 6 illustrates a partial view of an apparatus in accordance with the preferred embodiment of the present invention
• Figs. 7a-7d illustrate a mask pulsed plating method in accordance with the preferred embodiment of the present invention
• Fig. 7e illustrates a graph corresponding to Figs. 7a-7d in accordance with the preferred embodiment of the present invention
• Fig. 8 illustrates a perspective view of an apparatus in accordance with the first preferred embodiment of the present invention
• Fig. 9 illustrates a perspective view of an apparatus in accordance with the second preferred embodiment of the present invention.
• Fig. 10 illustrates a side view of an apparatus in accordance with the third preferred embodiment of the present invention.
• the present invention can be used with any substrate such as a semiconductor wafer, flat panel, magnetic film head, packaging substrate, and the like. Further, specific processing parameters such as time, pressure, mask designs, and the like are provided herein, which specific parameters are intended to be explanatory rather than limiting.
• the plating method described herein is called "mask-pulsed" plating.
• the present invention describes a method and apparatus for mask-pulse plating the conductive material onto the substrate by intermittently moving the mask to make contact with the substrate surface and applying power between an anode and the substrate, the mask being positioned in between the anode and the substrate. Furthermore, the present invention is directed to novel plating method and apparatus that provide enhanced electrodeposition of conductive materials into the various features on the substrate surface.
• Fig. 5 illustrates a plating cell 30 having therein an anode 31, a cathode 32, and an electrolyte 33.
• the electrolyte 33 is in contact with the top surface of the cathode 32.
• the cathode 32 in the examples provided herein is a wafer (substrate) having various features on its top surface.
• Fig. 6 illustrates a preferred embodiment of the present invention.
• a mask 40 is positioned in close proximity to the cathode wafer 32, where the mask 40 includes an opening 42 through which the electrolyte 33 makes physical contact with a section of the wafer 32.
• Fig. 6 does not illustrate the electrical connections, the anode, and the plating cell containing the electrolyte 33.
• the opening 42 allows the Cu from the electrolyte 33 to be plated onto the surface of the substrate 32 directly below the opening 42.
• the plating would largely be limited to the area of the substrate directly underneath the opening 42.
• the electrical current passing through a section on the wafer surface will vary. This is discussed in greater detail later herein.
• Figs. 7a-7d illustrate a mask pulsed plating method in accordance with the preferred embodiment of the present invention.
• the mask 40 is moved to the left with respect to the cathode wafer 32 (or alternatively, the wafer 32 may be moved to the right, or both the mask 40 and the wafer 32 may be moved relative to each other).
• Fig. 7e illustrates a graph depicting the deposition/plating current in relation to time at the section 45.
• the time interval ⁇ t (time between t 2 and t 3 ) is a function of the speed of the mask 40 as well as the size of the opening 42.
• ⁇ t will be a small value if the mask 40 is moved rapidly in relation to the wafer 32.
• the corresponding current vs. time plots would consist of multiple pulses.
• a DC power supply can be used for this plating technique.
• any section on the wafer surface can be suddenly and briefly exposed to the electrolyte and to the applied plating current.
• certain sections of the wafer surface are substantially free from the electrolyte. The electrolyte is applied to a section of the wafer only when that section is exposed to the electrolyte and a pulse of current is simultaneously applied.
• the current mask-pulsed plating method is used with simple metal deposition electrolytes with no additives (i.e., inhibitors and accelerators), it would not be expected to be much different than conventional plating. This is because the size of the openings 42 in the mask 40 is much larger than the feature size on the wafer 32 surface. Therefore, when a section is exposed through the opening 42 to the electrolyte, regular plating would commence. However, if additives are added that influence polarization, then the mask-pulsed plating method can offer advantages that is not existent in conventional pulsed plating techniques.
• the mask would clear away the additive A from the field regions since it makes physical contact with these regions. Both the small and large features, however, will still contain the adsorbed additive A since these features are not in direct physical contact with the mask.
• the bottom and side surfaces of the features with the previously adsorbed additive A would immediately start plating at a higher rate than the field regions. If the time period ⁇ t is less than the adsorption period required for the additive A to attach itself to the substrate surface, the applied plating current preferentially flows through the features to be filled, thereby yielding an enhanced deposition rate within the features in relation to the deposition rate on the field regions.
• the mask-pulsed plating method of the present invention utilizes the differences between response times of various additives to achieve enhanced plating into the various features of the substrate surface.
• the mechanism involves "sweeping" of the top surface of the substrate (field regions) by the mask, which does not make physical contact with the regions inside the features.
• the sweeping on the field regions establishes a differential between the concentration of the adsorbed species in those regions that are swept away and the regions that are within the features.
• the features with the adsorbed species attracts most of the plating current from the field regions. This present method works equally well using multiple additives.
• the plating solution contains an inhibitor B and an accelerator C with the adsorption kinetics of the inhibitor being much faster than that of accelerator
• the following mechanism can be used by the mask-pulsed plating method.
• Both the inhibitor B and the accelerator C would be partially or wholly swept off the field regions of the substrate by the mask. However, both species would still be present in the features.
• the inhibitor B When the substrate is exposed to the electrolyte and the electric field, the inhibitor B would readily adsorb onto the field regions introducing a high resistance path for the plating current.
• the accelerator C which is already present within the features, compensates for the action of the inhibitor in those regions and the current can easily flow through these features. Therefore, until the accelerator C is properly adsorbed onto the field regions, the film growth rate within the features will be higher.
• the present invention utilizes differences between adsorption/de-sorption kinetic of various electrolyte additives.
• the present invention accomplishes this by applying a solution and power suddenly and simultaneously to a specific section of the substrate surface that has been previously cleared off, partially or wholly, of one or more of the additive species.
• the geometry of the plating system shown in Fig. 6 is quite simplistic. There are many possible designs that can be used to practice this invention.
• the mask needs to be flat when using a wafer that is also flat.
• the mask should be made of an insulating rigid material and the surface facing the wafer may be hard and even contain abrasives to help "sweep" away the additives more efficiently.
• the wafer, mask, or both may be moved in linear or orbital manner or combination thereof.
• the size of the opening(s) in the mask and the speed of the relative motion between the mask and the wafer should be such that any section on the wafer should be exposed to the electrolyte only briefly, typically for less than two seconds, preferably less than one second, e.g., 10-500 msec. This time interval should be adjusted with respect to the adsorption characteristics of the additives being used.
• Fig. 8 illustrates a perspective view of an apparatus in accordance with the first preferred embodiment of the present invention.
• a mask 80 and an electrolyte channel plate 300 are mounted on an anode assembly 90.
• the electrolyte 100 is supplied to the anode assembly 90 by a pumping conventional system (not shown).
• the electrolyte 100 is pumped through the holes 210 into the channels 310 in the channel plate 300.
• the substrate/cathode is positioned facing the top surface of the mask 80 and the substrate and/or the mask 80 is/are rotated.
• the substrate may be pushed against the mask 80 at a pressure in the range of 0.01 psi and 0.5 psi. Higher pressures may be used, but may not be necessary.
• the entire anode assembly 90 may likewise be rotated.
• a cathodic voltage is applied to the substrate (not shown) with respect to an anode (not shown) placed within the anode assembly 90.
• the electrolyte 100 flowing through the channels 310 make physical contact with the wafer surface through the openings 250 in the mask 80.
• the electrolyte 100 is continuously discharged from the small bleeding holes 320 to be filtered and re-circulated. Very little, if any electrolyte actually get into the interface between the mask 80 and the wafer surface, which are in intimate contact during operation.
• Fig. 9 illustrates a perspective view of an apparatus in accordance with the second preferred embodiment of the present invention.
• the apparatus in Fig. 9 is similar to that shown in Fig. 8, except for the holes 510 and the channel plate 600.
• the channel plate 600 includes different shaped channels 610, which are used to distribute the electrolyte 100 in a serial manner to the openings 250 ofthe mask 80.
• Fig. 10 illustrates a side view of an apparatus in accordance with the third preferred embodiment of the present invention.
• Fig. 10 shows the electrolyte 100 coming into a reservoir 110 that resides on the top portion of the anode assembly 90.
• the electrolyte 100 makes contact with the surface of the wafer 350 through holes 250 in the mask 80.
• the electrolyte can be discharged from the reservoir 100 through bleeding holes 200.
• the power supply used in the present invention may be pulsed or DC power supply, but preferably it is a DC power supply.
• the power supply can be used in the current controlled or voltage controlled mode, i.e., it either keeps the applied current constant or applied voltage constant.
• a current controlled mode it is important that the size of the opening(s) in the mask be large enough to cover portions of the field regions as well as portions of the features simultaneously. In other words, when the wafer surface is exposed to the electrolyte through the opening(s), there should not be just the field regions that are exposed to the electrolyte at any given time. For example, if the opening is very small or the number of features on the wafer surface is low (low density features), the field regions are exposed to the electrolyte.
• This invention can be used to fill both small and large features.
• a serial process can also be utilized.
• the first step the mask is pulled away from the wafer surface allowing substantial amount of plating solution between the mask and the wafer surface. In this position, the system acts just like a traditional plating cell. With the help of the additives in the plating solution, the small features are filled during this step and the situation as shown in Fig. 2b occurs.
• the mask and the substrate are moved with respect to each other for uniform deposition. Then the mask is brought in contact with the surface squeezing out the solution from the wafer/mask interface except at the holes/openings on the mask.
• Mask-pulsed plating then commences to preferentially fill the larger features as described earlier. It is important to note that in the mask-pulsed plating technique, there is substantially no plating solution between the mask and the wafer surface except where the mask holes/openings are positioned.
• other conductive materials such as copper alloys, iron, nickel, chromium, indium, lead, tin, lead-tin alloys, nonleaded solderable alloys, silver, zinc, cadmium, ruthenium, their respective alloys may be used in the present invention.
• the present invention is especially suited for the fabrication of high performance and highly reliable chip interconnect, packaging, magnetic, flat panel and opto-electronic applications.
• the "mask-pulsed" plating describes a method and apparatus for mask-pulse plating the conductive material onto the substrate by creating an external influence that removes or changes additive adsorbed onto the top surface of the substrate with respect to the additive on the cavity surface of the substrate.
• This external influence can be created, as described in the preferred embodiment, by intermittently moving the a mask disposed in spaced relation that is proximate to but does not contact the substrate surface and applying power between an anode and the substrate, the mask being positioned in between the anode and the substrate.
• Fig. 5 illustrates a plating cell 30 having therein an anode 31, a cathode 32, and an electrolyte 33.
• the electrolyte 33 is in contact with the top surface of the cathode 32.
• the cathode 32 in the examples provided herein is a wafer (substrate) having various features on its top surface.
• Fig. 6 illustrates a preferred embodiment of the present invention.
• a mask 40 is positioned in close proximity to the cathode wafer 32, which is typically less than .75 mm and preferably in the range of 0.1 to 0.5 mm, and the relative movement is preferably at speeds between the range of 1 to 100 cm/s.
• the mask 40 can include an opening 42 through which the electrolyte 33 can travel, or can have a configuration without openings, but allows for the creation of a differential between additives on a top surface of the substrate and cavity portions of the substrate, as described hereinafter.
• the mask is typically flat, and can also have a textured surface, such that at a microscale level it is rough.
• the opening 42 allows the Cu from the electrolyte 33 to be plated onto the surface of the substrate 32 below the opening 42 in an amount greater than plating that may occur in areas not below an opening.
• a mask as described above is used to come in close proximity to the workpiece surface when creating the external influence.
• An external influence is thus applied using the mask so that the additive adsorbed onto the top surface is removed or otherwise changed with respect to the additive on the cavity surface of the workpiece.
• the mask can be applied in close proximity to the wafer as described above, typically for a period of 1 to 5 seconds or until a differential is created between the resistance of the top surface and the cavity surface resulting from a differential in additives.
• the mask is moved further away from the workpiece surface, preferably at least 0.1 cm, so that plating can occur thereafter.
• plating can then occur.
• the plating period is directly related to the adsorption rates of the additives.
• plating will occur more within features on than on the surface of the workpiece. Since the electrolyte is disposed over the entire workpiece surface, this also assists in lowering the current density and improving thickness uniformity of the plated layer.
• electric field lines can bend in the region between the mask and the surface of the workpiece yielding more uniform film.
• plating can be initiated while the mask is in close proximity to the top portion of the workpiece and the workpiece and mask move relative to each other, and then plating can continue while the mask is no longer in close proximity to the top portion of the workpiece while the sufficient differential exists. Since plating occurs both when there is close proximity between the mask and the workpiece, as well as when there is not, this can provide faster processing. It should be noted that additives should be carefully chosen for this application. Specifically, the additive species that need to be removed by the influence without physical contact should have weak adsorption characteristics so that they can be removed without direct contact between the mask and the wafer.
• the plating current can affect adsorption characteristics of additives.
• adsorption is stronger on surfaces through which an electrical current passes.
• adsorbing species may easily be removed from the surface they were attached to, after power is cut off or reduced from that surface (current passing through is cut off or reduced).
• Loosely bound additives can then be removed easily by the mask. In the cavities, although loosely bound, additives can stay more easily because they do not get influenced by the external influence.
• the distance that the mask can be moved away from the wafer and still be in close proximity, and thereby exert an external influence can increase, or a force that is obtained from something other than a mask can be used, such as, for example, a directed jet of an electrolyte that is used to agitate the additives on the top surface of the wafer.

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• 2001
  • 2001-08-09 EP EP01959666A patent/EP1307905A2/en not_active Withdrawn
  • 2001-08-09 WO PCT/US2001/024890 patent/WO2002015245A2/en not_active Application Discontinuation
  • 2001-08-09 JP JP2002520283A patent/JP2004521186A/ja active Pending
  • 2001-08-09 AU AU8119601A patent/AU8119601A/xx active Pending
  • 2001-08-09 CN CNB018155499A patent/CN1310289C/zh not_active Expired - Fee Related
  • 2001-08-09 KR KR10-2003-7001967A patent/KR20030040394A/ko not_active Application Discontinuation
  • 2001-08-10 TW TW090119667A patent/TW520407B/zh not_active IP Right Cessation

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