WO2002015245A3 - Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence - Google Patents

Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence Download PDF

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Publication number
WO2002015245A3
WO2002015245A3 PCT/US2001/024890 US0124890W WO0215245A3 WO 2002015245 A3 WO2002015245 A3 WO 2002015245A3 US 0124890 W US0124890 W US 0124890W WO 0215245 A3 WO0215245 A3 WO 0215245A3
Authority
WO
WIPO (PCT)
Prior art keywords
workpiece
creates
differential
additive
plating method
Prior art date
Application number
PCT/US2001/024890
Other languages
French (fr)
Other versions
WO2002015245A2 (en
Inventor
Bulent Basol
Original Assignee
Nutool Inc
Bulent Basol
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/740,701 external-priority patent/US6534116B2/en
Priority claimed from US09/919,788 external-priority patent/US6858121B2/en
Application filed by Nutool Inc, Bulent Basol filed Critical Nutool Inc
Priority to AU8119601A priority Critical patent/AU8119601A/en
Priority to EP01959666A priority patent/EP1307905A2/en
Priority to KR10-2003-7001967A priority patent/KR20030040394A/en
Priority to JP2002520283A priority patent/JP2004521186A/en
Publication of WO2002015245A2 publication Critical patent/WO2002015245A2/en
Publication of WO2002015245A3 publication Critical patent/WO2002015245A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/22—Electroplating combined with mechanical treatment during the deposition
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/34—Pretreatment of metallic surfaces to be electroplated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Abstract

The present invention relates to methods and apparatus for plating a conductive material on a substrate surface in a highly desirable manner. The invention removes at least one additive adsorbed on the top portion of the workpiece more than at least one additive disposed on a cavity portion, thereby allowing plating of the conductive material take place before the additive fully re-adsorbs onto the top portion and causing greater plating of the cavity portion relative to the top portion.
PCT/US2001/024890 2000-08-10 2001-08-09 Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence WO2002015245A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU8119601A AU8119601A (en) 2000-08-10 2001-08-09 Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence
EP01959666A EP1307905A2 (en) 2000-08-10 2001-08-09 Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence
KR10-2003-7001967A KR20030040394A (en) 2000-08-10 2001-08-09 Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence
JP2002520283A JP2004521186A (en) 2000-08-10 2001-08-09 Plating method and apparatus for creating a difference between a top surface of a workpiece and an additive deposited on a cavity surface using external influences

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US22473900P 2000-08-10 2000-08-10
US60/224,739 2000-08-10
US09/740,701 2000-12-18
US09/740,701 US6534116B2 (en) 2000-08-10 2000-12-18 Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence
US09/919,788 US6858121B2 (en) 2000-08-10 2001-07-31 Method and apparatus for filling low aspect ratio cavities with conductive material at high rate
US09/919,788 2001-07-31

Publications (2)

Publication Number Publication Date
WO2002015245A2 WO2002015245A2 (en) 2002-02-21
WO2002015245A3 true WO2002015245A3 (en) 2002-07-04

Family

ID=46204222

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/024890 WO2002015245A2 (en) 2000-08-10 2001-08-09 Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence

Country Status (7)

Country Link
EP (1) EP1307905A2 (en)
JP (1) JP2004521186A (en)
KR (1) KR20030040394A (en)
CN (1) CN1310289C (en)
AU (1) AU8119601A (en)
TW (1) TW520407B (en)
WO (1) WO2002015245A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101687462B1 (en) * 2012-02-24 2016-12-16 제이에프이 스틸 가부시키가이샤 Metal material, and surface treatment method and device
CN110453258B (en) * 2019-06-13 2021-10-26 佛山市顺德区巴田塑料实业有限公司 Method for producing electroplated lamp cap

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11238703A (en) * 1998-02-20 1999-08-31 Nec Corp Manufacture for semiconductor device
EP1063696A1 (en) * 1999-06-22 2000-12-27 Interuniversitair Micro-Elektronica Centrum Vzw A method for improving the quality of a metal-containing layer deposited from a plating bath
EP1122989A2 (en) * 2000-02-01 2001-08-08 Shinko Electric Industries Co. Ltd. Method of plating for filling via holes

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1075515A (en) * 1992-02-20 1993-08-25 海阳县刺绣厂 A kind of cut work embroidery

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11238703A (en) * 1998-02-20 1999-08-31 Nec Corp Manufacture for semiconductor device
US6245676B1 (en) * 1998-02-20 2001-06-12 Nec Corporation Method of electroplating copper interconnects
EP1063696A1 (en) * 1999-06-22 2000-12-27 Interuniversitair Micro-Elektronica Centrum Vzw A method for improving the quality of a metal-containing layer deposited from a plating bath
EP1122989A2 (en) * 2000-02-01 2001-08-08 Shinko Electric Industries Co. Ltd. Method of plating for filling via holes

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 13 30 November 1999 (1999-11-30) *

Also Published As

Publication number Publication date
WO2002015245A2 (en) 2002-02-21
CN1559081A (en) 2004-12-29
TW520407B (en) 2003-02-11
KR20030040394A (en) 2003-05-22
CN1310289C (en) 2007-04-11
JP2004521186A (en) 2004-07-15
AU8119601A (en) 2002-02-25
EP1307905A2 (en) 2003-05-07

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