Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/32—Circuit design at the digital level
  • G06F30/33—Design verification, e.g. functional simulation or model checking
  • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/32—Circuit design at the digital level
  • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

• This invention relates to a method for improving the design and layout processes for integrated circuits, particularly very large scale integrated circuits.
• VLSI circuits The design of VLSI circuits consists of three major steps. In the first step circuit schematics are created by designers. The next step confirms the correct logical behavior and timing by analog, digital or mixed signal simulation. Usually these two steps are iterated many times, before the layout work, which is the third step, starts.
• a VLSI such as a high-density, high speed dynamic random access memory (DRAM)
• DRAM high speed dynamic random access memory
• the blocks are intended to operate simultaneously and independently of each other. But because of the dense spacings of the blocks and very short signal pulse rise times (e.g., 20 picoseconds or so), particular care must be taken to minimize the ill effects of parasitic conditions since otherwise the operation of one block may adversely affect the operation and timing of another block and the DRAM will not operate with best efficiency or optimum speed.
• the present invention addresses this problem. Summary of the Invention
• an improved method for the design and layout of integrated circuits particularly very large scale integrated circuits (VLSIs) such as high-density, high speed dynamic random access memories (DRAMs) having a plurality of blocks for increased efficiency of operation.
• VLSIs very large scale integrated circuits
• DRAMs high speed dynamic random access memories
• the blocks are designed and laid out separately, using computer-aided-design and computer simulation, and are then combined into an overall chip layout.
• An integral part of the computer-aided-design and simulation process is simultaneous identification of parasitic elements being generated during layout.
• parasitic elements are recognized and from these elements parasitic extractions (i.e., calculated values of the parasitic elements in each block) are provided for all blocks on an immediate and continuing basis.
• the present is directed to a method for design and layout of an integrated circuit having parasitic elements.
• the method comprising the steps of: making initial designs of various portions of the integrated circuit; evaluating the designs by computer simulations; making extractions of parasitic elements as soon as available in the initial design and simulation steps and storing such extractions in a database common to all portions of the integrated circuit; back annotating the information stored in the database on an ongoing basis to benefit immediately the initial design and simulation, and subsequent steps; making layouts with parasitic extractions of the various portions of the integrated circuit before and after successful simulations; and making a full chip layout of the integrated circuit with parasitic extractions and simulating same.
• the present is directed to a method for design and layout of a very large scale integrated circuit (VLSI) having a plurality of blocks and having parasitic elements.
• the method comprises the steps of: initially designing each of the blocks in separate parallel efforts; initially simulating each block design; simultaneously making extractions of parasitic elements identified in each block and storing the information thus obtained in a database common to all blocks; back annotating the parasitic extractions on a continual basis to each of the blocks to benefit the initial design, simulation, and subsequent steps; making a layout with parasitic extractions for each block design after successful simulation thereof; making a full chip layout with parasitic extraction; and simulating with back annotation of parasitic elements the full chip layout to optimize the design thereof.
• VLSI very large scale integrated circuit
• VLSI very large scale integrated circuit
• DRAM dynamic random access memory
• the method comprises the steps of: making initial designs of various portions of the VLSI; evaluating the designs by computer simulations; making extractions of parasitic elements as part of the initial design and simulation steps and storing such extractions in a database common to all portions of the VLSI; back annotating the information stored in the database on an ongoing basis to optimize the initial design, simulation, and subsequent steps and to minimize the effects of parasitic elements; making layouts with parasitic extractions of the various portions of the VLSI after successful simulations; and making a full chip layout of the VLSI with parasitic extractions and simulating same such that the operation of the VLSI is optimized.
• the present invention is directed to a method for design and layout of a dynamic random access memory (DRAM) having a plurality of blocks and having parasitic elements which can affect signal timings.
• the method comprises the steps of: initially designing each of the blocks in separate parallel efforts; initially simulating each block design; making extractions of parasitic elements identified in each block and storing the information thus obtained in a database common to all blocks; back annotating the parasitic extractions on a continual basis to each of the blocks to optimize the initial design, simulation, and subsequent steps and to minimize the effects of parasitic elements; making a layout with parasitic extractions for each block design after successful simulation thereof; making a full chip layout with parasitic extraction; and simulating with back annotation of parasitic elements the full chip layout to optimize the design thereof.
• DRAM dynamic random access memory
• the present invention is directed to a method for design and layout of very large scale integrated circuit (VLSI) , including high-density dynamic random access memories each having a plurality of blocks and having signal delay dominated by wire delay instead of gate delay.
• VLSI very large scale integrated circuit
• the method comprises the steps of: initially designing blocks in separate efforts; initially simulating each block design; making extractions of parasitic elements block-by-block on an ongoing basis and storing the extractions in a database common to all blocks; back annotating the parasitic extractions on an ongoing basis to each of the blocks to benefit initial design, simulation, and subsequent steps; repeating the initial design and simulation steps in a block if a shortcoming is discovered; making a layout with parasitic extractions for each block design after successful simulation thereof; making a full chip layout with parasitic extraction; and simulating with back annotation of parasitic elements the full chip layout to minimize the effects of parasitic elements on operation of the VLSI .
• the present invention is directed to an improved integrated circuit or very large scale integrated circuit, including a dynamic random access memory, made in accordance with any of the above described methods .
• FIG. 1 is a schematic representation of a prior art method for design and layout, and computer simulation of a very large scale integrated circuit (VLSI) having a plurality of circuit blocks;
• VLSI very large scale integrated circuit
• FIG. 2A is a schematic representation of an enlarged part of the circuit of FIG. 1 illustrating parasitic resistance and capacitance in the layout;
• FIG. 2B is a schematic illustration of the relative size of parasitic capacitance coupling from one layer of the circuit of FIG. 2A to an adjacent layer of the circuit;
• FIG. 3A is a schematic representation of the circuit of FIG. 2A showing a change in a wire layout on one layer of the circuit;
• FIG. 3B is a schematic illustration of the relative size of parasitic capacitance coupling from one layer of the circuit of FIG. 3A to an adjacent layer of the circuit, the parasitic capacitance here being relatively larger than that illustrated in FIG. 2B;
• FIG. 4 is a schematic representation of a method, provided in accordance with the present invention, for design and layout, and computer simulation of a VLSI having a plurality of circuit blocks.
• FIG. 1 there is shown a schematic diagram 10 of a prior-art method for computer-aided-design, layout, and computer simulation of a very large scale integrated circuit (VLSI) having a plurality of circuit blocks 12 (respectively identified as "A”, “B", to “n” and which are to be integrated on an overall circuit chip, not shown here.
• VLSI very large scale integrated circuit
• the design flow indicated by the diagram 10 starts with a first step for each respective block 12 of entering a schematic circuit diagram for the block, as indicated by a respective box 14 titled "schematic entry”.
• each block 12 evaluates the respective circuits represented by the blocks 12 by using a computer (not shown) to simulate the circuit-logic and timing, as indicated by a box 16 titled "SIMULATION". If the design appears satisfactory, as indicated by a box 18 titled “OK”, the design proceeds to a layout stage, indicated by a respective box 20. If, on the other hand, a design shortcoming is uncovered by the simulation at the box 16, the design is modified and reentered as indicated by a return line 22 from the box 18 to the box 14.
• the design proceeds to the overall circuit layout of all the blocks 12 (A, B,...n) on an entire chip, as indicated by the box 24 (Full Chip layout) .
• parasitic extraction (indicated by a box 26) for the entire circuit is carried out by computer calculation of values of parasitic capacitances and resistances. These values are then entered into a parasitic database, indicated by a box 28.
• a box 28 Up to this point in the overall design and layout process, as represented by the schematic diagram 10, there has been no effective way in this prior-art method to take into account the parasitic elements and their cumulative effects on the operation of the full chip circuit.
• parasitic elements can have important and adverse effects on the operations of the individual blocks 12, and on the performance, and speed of the full chip circuit. Except perhaps for a local effort, indicated by a dashed-line box 30 (parasitic extraction) , a dashed line box 32 (local database) , and a dashed line box 34 (back annotation) shown adjacent the block 12 (A) and made by the engineer-designer laying out that particular block, there is no overall way provided in the diagram 10 for the designers of the various blocks 12 to take into account, prior to the full chip layout of box 24, the combined and interrelated effects of parasitic elements. This is a serious limitation of the method and causes difficulties in subsequently optimizing the operation and timing of the full chip circuit, as well as the respective blocks themselves.
• the parasitic values are used in conjunction with the full chip layout (box 24) in a "back annotation" step, indicated by a box 36, to modify the design and/or layout of the full chip so that a full-chip computer simulation, indicated by a box 38, can be made. Needed modifications or changes indicated by the simulation are than referenced back to the beginning of each respective block 12, as indicated by a dashed line 39, and the design process with changes, is repeated. Such design process is iterated as many times as deemed necessary to optimize the performance of the full chip.
• FIG. 2A there is shown an enlarged schematic representation in plan view, of a small part of a VLSI circuit 40 on a semiconductor chip 42 (shown in dashed outline) .
• the circuit 40 has a lower insulating layer 44 (only a portion of which is shown) containing a circuit trace or "wire" 46 connecting a point "A" to a point "B". Lying on top of the layer 44 and its wire 46 is an insulation layer 48 (only a portion of which is shown) containing a wire 50 which is shown cross-hatched to indicate it lies on a level higher than the wire 46. Where the wire 50 crosses above the wire 46, in a region indicated by a small circle 52, there is some parasitic capacitance between the two wires.
• FIG. 2B there is shown, connected between the wire 46 and the wire 50, a capacitor 54 representing the parasitic capacitance between the wires in the region 52 (FIG 2A) .
• a capacitor 54 representing the parasitic capacitance between the wires in the region 52 (FIG 2A) .
• the operation of that portion of the VLSI circuit 40 on the layer 44 will affect to a greater or smaller degree that portion of the circuit 40 on the upper layer 48.
• parasitic elements such as the parasitic resistances and capacitances of the wires 46 and 50, are created, and quite possibly changed in different, uncoordinated ways .
• an engineer in the course of laying out a respective block 12 may decide that a wire, such as the wire 50, which happens to be in his layout of that block has too much parasitic resistance.
• the engineer may then change the configuration of that wire to lower its resistance, though this change also affects an adjacent block 12 (e.g., block B) .
• Such layout changes can result in significant and unforeseen changes in the operations of the blocks 12, and in the overall operation of the full VLSI circuit 40.
• FIG. 3A there is shown a schematic circuit 56, which is closely similar to the circuit 40 (FIG. 2A) .
• the circuit 56 however has an upper wire 58 reconfigured from the wire 50 (FIG. 2A) to lower the parasitic resistance of the wire 50 by making the wire 58 substantially wider.
• the parasitic capacitance here between the wires 46 and 58 is substantially higher than the parasitic capacitance between the wires 46 and 50 as indicated by the small circle 52 in FIG. 2A.
• FIG. 3B there is shown connected between the wire 46 and the wire 58, a capacitor 62 representing the parasitic capacitance between the wires in the oval area 60 (FIG. 3A) .
• the capacitor 62 will be substantially larger than the capacitor 54. This in turn further increases the delay of a signal on the wire 46 in going from point A to point B in the circuit 56 of FIG. 3A.
• the illustrations given in FIGs . 2A, 2B, 3A, and 3B highlight the problems caused by parasitic elements, and of changes thereof made during a prior-art design and layout process of a VLSI as schematically shown by the diagram 10.
• FIG. 4 there is shown a schematic diagram 70 of a method, provided in accordance with the present invention, for computer-aided-design, layout, and computer simulation of a very large scale integrated circuit (VLSI) having a plurality of circuit blocks 72 (respectively identified as Block “1", Block “2”, Block “n”, and which are to be integrated to form an integrated circuit (IC, not shown here) .
• VLSI is a type of integrated circuit (IC) .
• the design flow indicated by the diagram 70 starts with a first step for each block 72 of entering a schematic circuit diagram of that block, as indicated by a respective box 74 titled "SCHEMATIC ENTRY".
• each block 72 evaluates the respective circuits represented by the blocks 72 by using a computer (not shown) to simulate the circuit-logic and timing as indicated by a respective box 76 titled "SIMULATION" .
• a computer not shown
• "back annotation" of values of parasitic elements which values have become available in the various blocks 72 during the overall design process as it progresses in any or all of the blocks 72, is immediately provided by an information feedback loop indicated by a common lead 78 connected to the boxes 74 and 76 in each of the blocks 72.
• This continual and global feedback of information regarding parasitic elements will be explained in greater detail hereinafter. Such information provided in the earliest stages of design is of great importance and value to the success of the overall method as illustrated by the diagram 70.
• the layout (box 82) of each individual block 72 is combined into a full chip layout (box 86), as is indicated by the arrows 96.
• Parasitic extraction from the full chip layout (box 86) is also applied to the parasitic database 90, as indicated by an arrow 98, so that back annotation (box 94) of all parasitic extractions can be applied, as is indicated by an arrow 100 to the final step of full chip simulation (box 102) .
• the providing of information on all parasitic elements as soon as known, and well before full chip simulation, greatly aids the optimizing of a VLSI and its component blocks . This also considerably shortens the time required by the engineers in doing or re-doing the various steps of design, layout and full chip simulation of the VLSI.

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• 2001
  • 2001-07-02 TW TW090116396A patent/TW518488B/zh not_active IP Right Cessation
  • 2001-07-02 WO PCT/US2001/021162 patent/WO2002003266A2/en not_active Ceased
  • 2001-07-02 EP EP01952407A patent/EP1307835A2/de not_active Withdrawn

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