EP1307835A2 - Procede de conception et d'implantation de circuits integres - Google Patents

Procede de conception et d'implantation de circuits integres

Info

Publication number
EP1307835A2
EP1307835A2 EP01952407A EP01952407A EP1307835A2 EP 1307835 A2 EP1307835 A2 EP 1307835A2 EP 01952407 A EP01952407 A EP 01952407A EP 01952407 A EP01952407 A EP 01952407A EP 1307835 A2 EP1307835 A2 EP 1307835A2
Authority
EP
European Patent Office
Prior art keywords
parasitic
design
extractions
layout
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01952407A
Other languages
German (de)
English (en)
Inventor
Gerd Frankowsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies North America Corp
Original Assignee
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies North America Corp filed Critical Infineon Technologies North America Corp
Publication of EP1307835A2 publication Critical patent/EP1307835A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Abstract

Procédé servant à améliorer la conception, l'implantation et la capacité d'un circuit intégré à très grande échelle (VLSI) possédant une pluralité de blocs et comportant des éléments parasites, ce qui consiste initialement à concevoir chacun des blocs de façon séparée et parallèle, à simuler chaque conception de bloc et à extraire des éléments parasites identifiés dans chaque bloc, puis à mémoriser les informations obtenues dans une base de données commune à la totalité des blocs. Ce procédé consiste, de plus, à reporter la notation des extractions parasites sur une base continue pour chacun des blocs afin de tirer avantage de la conception initiale, de la simulation et des étapes suivantes, à élaborer une implantation comportant des extractions parasites pour chaque conception de bloc après la simulation réussie de ce dernier, à réaliser une implantation totale de puce avec extraction parasite et à simuler au moyen de l'annotation des éléments parasites, l'implantation totale de la puce afin d'en optimiser la conception.
EP01952407A 2000-06-30 2001-07-02 Procede de conception et d'implantation de circuits integres Withdrawn EP1307835A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US60854200A 2000-06-30 2000-06-30
US608542 2000-06-30
PCT/US2001/021162 WO2002003266A2 (fr) 2000-06-30 2001-07-02 Procede de conception et d'implantation de circuits integres

Publications (1)

Publication Number Publication Date
EP1307835A2 true EP1307835A2 (fr) 2003-05-07

Family

ID=24436957

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01952407A Withdrawn EP1307835A2 (fr) 2000-06-30 2001-07-02 Procede de conception et d'implantation de circuits integres

Country Status (3)

Country Link
EP (1) EP1307835A2 (fr)
TW (1) TW518488B (fr)
WO (1) WO2002003266A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7137088B2 (en) 2004-05-04 2006-11-14 Hewlett-Packard Development Company, L.P. System and method for determining signal coupling coefficients for lines
US8001514B2 (en) * 2008-04-23 2011-08-16 Synopsys, Inc. Method and apparatus for computing a detailed routability estimation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629860A (en) * 1994-05-16 1997-05-13 Motorola, Inc. Method for determining timing delays associated with placement and routing of an integrated circuit
JP2002526908A (ja) * 1998-09-30 2002-08-20 ケイデンス デザイン システムズ インコーポレイテッド ブロックをベースとする設計方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0203266A2 *

Also Published As

Publication number Publication date
TW518488B (en) 2003-01-21
WO2002003266A2 (fr) 2002-01-10
WO2002003266A3 (fr) 2003-02-27

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Legal Events

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Effective date: 20040524

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Effective date: 20050825