TW518488B - Method for design and layout of integrated circuits - Google Patents

Abstract

A method, which improves the design, layout, and performance of a very large scale integrated circuit (VLSI) having a plurality of blocks and having parasitic elements, includes initially designing each of the blocks in separate parallel efforts; initially simulating each block design; and making extractions of parasitic elements identified in each block and storing the information thus obtained in a database common to all blocks. The method further includes back annotating the parasitic extractions on a continual basis to each of the blocks to benefit the initial design, simulation, and subsequent steps; making a layout with parasitic extractions for each block design after successful simulation thereof; making a full chip layout with parasitic extraction; and simulating with back annotation of parasitic elements the full chip layout to optimize the design thereof.

Description

518488 A7 B7

The invention relates to the method of the bureau. The invention relates to the design and layout of an improved integrated circuit. In particular, the invention relates to a very large integrated circuit. BACKGROUND OF THE INVENTION As integrated circuits (ICs) should be stimulated by the use of Hachichi ’s and different applications, integrated circuits have become more and more complex,

The installation of individual small semiconductor wafers includes billions of them. The design and layout of 4 large and 3 integrated circuits (VLSIs) that are installed in the summer, are simpler than in the past. The early integrated circuits in μ are complicated and time-consuming. . In view of the costly production of very large-scale integrated circuits and trial operation of small-scale practical circuits, the design and layout methods currently adopt monthly electricity supplementary calculation (CA) and computer simulations to evaluate actual electrical performance. The design of a very large integrated circuit includes three main steps. The first step is for the designer to create a schematic circuit diagram. The second step is to use analog, number Z, or mixed signals to determine error-free logic activities and timing. Usually, after repeating these two steps, the third step—layout work—is started. At present, one of the biggest problems in the design of submicron ultra-large integrated circuits is the influence of parasitic elements, such as the resistance and capacitance of wires (ie, circuit traces) are becoming more and more important, and must be carefully considered. The signal delay in the path is derived from the internal delay, which is related to the logic gate delay. 'The delay in the 4th path is called the delay of the pole.' The "wire delay" is related to the connector (wire )related. Old-fashioned, low-density technology, that is, integrated circuits designed with 3.5 micron signals, mostly derives from the gate delay, which accounts for about 80% of the typical path total delay. However, due to high-density integration, this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 518488 A7 B7 V. Description of the invention (2 Remedy this situation. Density technology, ie. 1.8 micron design For integrated circuits, most of the ^ delays are derived from wire delays, which account for about 70% of the total delay. This shows the importance of calculating parasitic elements, and it should be included in the simulation as soon as possible. The conductors are estimated by the designer and shown in the circuit diagram. However, this method is limited, because it is impossible to consider all parasitic components during layout. After the layout step, it can be extracted from the layout data and incorporated into it. Simulation (reverse annotation). The main problem in this design process is to maintain the consistency between the design and the parasitic database. Very large and integrated circuits, such as high-density, high-speed dynamic random access memory (DRAM), must be decomposed into Multiple blocks, or sub_divisions, to improve operating efficiency. Blocks are designed to work simultaneously and independently, given the tight block space and the rise time of signal pulses Short (that is, about 20 picoseconds), so the negative effects of parasitic processing must be particularly reduced, otherwise the operation of this block may adversely affect the operation and timing of other blocks' and dynamic random access memory will not be most efficient The operation or reach the optimal rate. The present invention illustrates this problem. Summary of the Invention According to an embodiment of the present invention, an improved method for providing the design and layout of integrated circuits, especially very large integrated circuits (VLSIs), such as High-density, high-speed dynamic random access memory (DRAMs), which has a plurality of blocks to increase operating efficiency. The blocks are designed and arranged separately, using computer-aided design and computer simulation, and then combined into a whole Layout. An integrated part of computer-aided design and computer simulation methods, which is used to identify parasitic elements at the same time when decorating. When designing and layout each block, send ~ 5-This paper standard applies to China National Standard (CNS) A4 size (21 × 297 mm)-'1- 518488

The raw parts are identified and all blocks are provided immediately and continuously by the parasitic age information of these elements (ie the calculated values of the parasitic elements in each block). Here, the parasitic capture information is transmitted to the Central Corruption Repository in an initial and continuous manner. In this way, the design and layout of each block and all block mixes benefit the acquisition of information about all parasitic element mixes. Finally, the total time, which is used for the design, layout, and computer simulation of the complete chip, can be reduced, and the speed and operation of the chip are optimal. From a method standpoint, the narrative refers to a method of designing and arranging integrated circuits with parasitic elements. The method includes the following steps

Installation · Make a preliminary design of each part of the integrated circuit; evaluate it by computer simulation; once it can be obtained from the preliminary design and simulation steps, retrieve the parasitic component information and store the retrieved information In a database shared by all parts of the integrated circuit; continuously reverse-annotate the information stored in the database to immediately benefit the design, simulation and subsequent steps; use the integrated body before and after successfully simulating the block design Parasitic capture information for various parts of the circuit

Making a layout; and using the parasitic capture information to make a full-chip layout of the integrated circuit and simulate it. From a second method standpoint, the narrative refers to a method for the design and layout of a very large integrated circuit (VLSI), which has a plurality of blocks and multiple parasitic elements. The method includes the following steps: a preliminary design of each block in a parallel and parallel manner; a preliminary simulation of the design of each block; the simultaneous retrieval of the information of the parasitic elements identified in each block 'will be used in this way The obtained information is stored in a database shared by all the blocks; each block is reverse-annotated in a continuous manner. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 518488

Parasitic capture tribute to benefit from the initial design, simulation and subsequent steps; After successfully simulating the block design, use the parasitic capture information to make the layout of each block design; use the parasitic capture information to make a complete Wafer layout; and back-annotation of the parasitic elements to simulate the full wafer layout to optimize the wafer design. From a third method standpoint, the narrative refers to a method for the design and layout of a very large integrated circuit (VLSI). The very large integrated circuit includes a circuit with a width of less than 0.2 microns and a significant influence on signal timing. Parasitic elements of dynamic random access memory (DRAM). The method includes the following steps: making a preliminary design of each part of the very large integrated circuit; planning to evaluate the design by a computer; extracting the parasitic elements as part of the preliminary design and simulation steps, and The captured information is stored in a database common to all parts of the ultra-large integrated circuit; the annotations stored in the shell database are continuously reverse-annotated to optimize the preliminary design, simulation, and subsequent steps, so that The effect of the special parasitic component is minimized; after successful simulation, the layout is made using the parasitic capture information of each part of the super large integrated circuit, and the full chip of the super large integrated circuit is manufactured using the parasitic captured information. Layout and simulate it to make the super large integrated circuit operate optimally. From the perspective of a fourth method, the present invention refers to a method for designing and arranging a dynamic random access memory (DRAM). The dynamic random access memory has a plurality of blocks and has a plurality of significant influences on signal timing. Parasitic element. The method includes the following steps: preliminary design of each block in a parallel and parallel manner; preliminary simulation of the design of each block; extraction from each block; the paper size applies the Chinese National Standard (CNS) A4 specification (21 °). x 297 mm)

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V. Invention Description G

Of the parasitic elements identified in the ^ .. 70 pieces of Bexun 'ya will store the information obtained in this way-in a database of all blocks; in a continuous way-the block Reverse annotate the parasitic # | Get information to optimize the preliminary calculation, verification, and subsequent steps to minimize the impact of these parasitic elements; use the parasitic to capture information after successfully simulating the block design Fabricate the layout of each-block design; use the parasitic capture information to make a full-chip layout; and use the back annotations of the parasitic elements to simulate the full-chip layout to optimize the chip design. Order

From the perspective of a fifth method, the invention refers to a method and layout of a very large integrated circuit (JLSI). The very large integrated circuit includes a plurality of high-density dynamic random access memories, each dynamic The random access memory has a plurality of blocks 1 each having a signal delay mainly due to a wire delay and a pole delay. The method includes the following steps: using a head-to-head parallel method to initially count each block and initially simulate the design of each block; continue to manipulate the parasitic component information one by one, and store the captured information in all areas In the database shared by the blocks; annotate the parasitic capture information for each block in a continuous manner to benefit the preliminary design, simulation and subsequent steps; if defects are found, then in a block Repeat the preliminary design and simulation steps; after successfully simulating the block design, use the parasitic capture information to make a layout for each block design; use the parasitic capture information to make a full-chip layout; and use the parasitic components inversely Annotate to simulate the full-chip layout to minimize the impact of parasitic elements such as plutonium on the operation of very large integrated circuits. From a device standpoint, the present invention refers to an improved integrated circuit or superconductor.

A7 B7 V. Description of the Invention A large integrated circuit including a dynamic random access memory is made by any of the methods described above. It is based on the above, which combines a good contribution of the present invention with all the advantages. The full contribution is obtained from the following description, and is accompanied by the attached legend and the scope of the patent application. It is simply illustrated for design. Brother 1 in the layout is a schematic diagram showing a prior art method bureau and computer simulation of a very large integrated circuit (VLSI), block; Figure 2 A is a schematic diagram showing the enlarged circuit parasitics in Figure 1 'Resistance and capacitance; Figure 2B is a schematic diagram illustrating the relative size of the parasitic capacitance, which is interconnected from one layer in the circuit of Figure 2 to an adjacent layer; Figure 3A is a schematic diagram showing the circuit of Figure 28, illustrating the wires in one layer of the circuit Layout changes; Figure 3B is a schematic diagram illustrating the relative size of the parasitic capacitance, which is interconnected from one layer in the circuit of Figure 38 to an adjacent layer, which is larger than the parasitic capacitance of Figure 2] 3; and Figure 4 is a schematic diagram Shows a method, according to the present invention, providing design, layout, and computer simulation of a very large integrated circuit with a plurality of blocks. Detailed description of the invention with reference to FIG. A schematic diagram of a prior art method 10 is for design, layout, and computer simulation of a very large integrated circuit (VLSI), which has a plurality of circuit blocks 12 (represented by "A", "B", to " η "difference), and the entire paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 518488 A7 B7 5. Description of the invention (7) Combined into a complete circuit chip 'not shown in the figure. The design flow shown in Fig. 丨 begins with the first step 'for the mother-to-respective block 12 to add a schematic circuit diagram, which is shown in the respective blocks marked "Schematic Addition' 1 4. So each block 1 2 ( That is, A, B ... η) The designer uses a computer (not shown in the figure) to simulate the logic and timing of the circuit to evaluate the individual circuits represented by block 12. The simulation operation is shown in the box labeled "Simulation" 1 6 . If the design is satisfactory, such as box 18 marked “0κ,”, the design is in the layout stage, as shown in box 20. If the simulation of box 16 finds shortcomings, the design must be modified and re-added, such as from the box workers. 8 to the turning line 2 of block 14 2. Once the layout of the individual blocks 12 is completely satisfactory, the design is on an overall chip, shown in block 2 4 (full chip layout) for all blocks 丨 2 (ie a, Β ... η) complete circuit layout. After the full chip layout is completed, the parasitic capture of the entire circuit is performed (shown in box 26). The computer calculates the parasitic resistance and capacitance. These calculated values are added to the parasitic data. The library is shown in block 28. At this point in the overall design and layout, according to the schematic diagram 10, the prior art method still cannot effectively consider the total impact of parasitic elements and their operation on the full-chip circuit. As described in detail below, parasitic elements The operation of block 丨 2 has a significant and adverse effect on the nature and speed of the full-chip circuit. Unless it is locally operated, the dotted line (parasitic extraction) box 30 shown next to block 12 and the dotted line (local database)Block 32, dashed line (reverse note) Box 34, is a special block 12 designed by the engineer but laid out; before the full-chip layout block 24, designers of different blocks 12 (A) cannot consider the parasitics with the schematic diagram 10 The influence of component mixing and interaction. This is a serious limitation of this method, which causes the subsequent full-chip and individual block operation and timing to reach the optimal level of difficulty. I_____-10-This paper size_ 关 家 鲜 丨 21GX297_ 518488

After adding data to the parasitic database (block 2 8), the parasitic value together with the full chip layout (block 2 4) enters "reverse annotation," step 36, to modify the design and / or layout of the full chip. The computer simulation of the chip 38 can be completed. The corrections and changes required for the simulation display are transmitted back to the input of each individual block 12, such as the dotted line 39, so the changed design is repeated. The process is repeated again and again until the performance of the full chip is optimal.

Referring to FIG. 2A, it shows an enlarged schematic plan view of a small portion (shown in dotted lines) of a very large integrated circuit 40 on a semiconductor wafer 42. The circuit 40 has a lower, sloping edge layer 4 4 (only part shown), which includes a stitch, or a “wire” 4 6 connecting the two points A and B. The insulating layer 44 and the other insulating layer 48 (only a part shown) on the conductive wire 46 include a conductive wire 50. Since it is one layer higher than the conductive wire 46, it is indicated by a dotted line. The portion of the lead 50 that crosses the lead 46 is shown as a small circle 52, indicating that there is a parasitic capacitance between the two wires. Order

Referring to FIG. 2B, the capacitor 54 is shown between the lead 46 and the lead 50, and the capacitor 54 represents the parasitic capacitance 52 between the two wires (FIG. 2a). Depending on the size of the parasitic capacitance 54, the part of the super-large integrated circuit 40 on the insulating layer 44 affects the weight of the upper part 48 of the circuit 40. When designing and arranging the individual blocks 2 (Figure 丨), it is obvious that multiple parasitic elements are formed, such as the parasitic resistance and capacitance of the wires 46 and 50, and it is very likely to be changed by different and unadjustable methods. In this way, an engineer is laying out a separate block 12 (ie, block A) and may decide that the lead, such as lead 50, is in the block in which it is laid out, and its parasitic resistance is too large. The engineer may change the configuration of the wire to reduce its resistance, but this change also affects the neighboring block 12 (i.e. block B). This layout change can lead to the serious and unpredictable operation of block 12 and the entire ultra-large integrated circuit 40. _____-11-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

Change. Referring to Fig. 3A, a schematic circuit diagram 56 similar to circuit 40 (Fig. 2A) is shown. The circuit is not intended to have a reconfiguration of a lead 58 that is a lead 50 (Fig. 2A); the lead 58 is significantly widened to reduce the parasitic resistance of the lead 50. However, for the entire area 60, the parasitic capacitance value between the wires 46 and 58 is significantly larger than the parasitic capacitance value between the wires 46 and 50, as shown by the small circle 52 in FIG. 2. Referring to Fig. 3B, it is shown that the capacitor Q connected between the leads 46 and 58 represents the parasitic capacitance between the lines in the entire area 60 (Fig. 3A). As mentioned earlier, since the entire area 60 is larger than the area 52 (FIG. 2A), the capacitor 62 is also significantly larger than the capacitor 54. As a result, in the circuit 5613A, the signal delay on the wire 46 connecting the two points a and b is increased. Figures 2A, 2B, 3A, and 3B emphasize the problems caused by parasitic elements. When the previous technology design and layout of large-scale integrated methods, as shown in Figure 10 changes. / Refer to Figure 4, which shows the schematic diagram of the method 7 (), according to the present invention, for computer-aided design, layout, and computer simulation of a very large integrated circuit, 'It has a plurality of circuit blocks 72 ( Take blocks "丨", 'block one ... block n㉟other])' and integrate to form an integrated circuit (ic, not shown in the figure). -Very large integrated circuits are a type of integrated circuits. The design flow shown in FIG. 7G starts at step _ for each _ individual block 72 to be added-a schematic circuit diagram is shown in each block 74 labeled "Schematic Addition," so each-block 72 (ie block 1,2, ... n) The designer uses a computer (not shown) to simulate the logic and timing of the circuit to evaluate the individual circuits represented by block 72. The simulation operation is shown in the% of simulation, . 518488

When these initial steps are performed at the same time, the "reverse annotation" of the parasitic it values is immediately provided by the 72-per-block 'connection block 74 and 76 to jointly connect the information feedback loop provided' and when the entire design process is carried out in Any—or all blocks at 720 'The values of these parasitic elements are obtained from different blocks & this continuous and wide-ranging information feedback on parasitic elements is described in detail below. The availability of this information early in the design phase has a significant relationship and value to the success of the overall approach shown in Figure 70. If after the "simulation," step is marked in the box%, the design is satisfactory, such as ("OK"), the output of the box 80 is marked "YES", then this stage is shown in the box 82 of the "generate capture layout '". This allows you to worry about parasitic capture even before the chip layout. If the simulation of block 76 finds a disadvantage, that is, the output of block 80 is No., the design must be modified and re-added, such as the line of revolution 84 from block 80 to block 74. At the same time, any parasitic extraction information in the respective blocks 72 has been changed in advance, and it is also fed back to the design flow by the loop 78. Before performing the full-chip layout step, shown in "Parasitic Capture Full-Chip Layout," box 86, the parasitic elements of all blocks 72 are fed to a common or wide-range parasitic database (box 90), as in Arrow 92. All parasitic extraction information (and any changes therein) originating from the respective block 72 are simultaneously retrieved from the database 90, "reversely annotated, (block 94) to the feedback loop 78, and immediately feed To separate block 72, as described above. Thus, even before the full layout, the design and layout of these individual blocks 72 can still benefit from being aware of the presence of parasitic elements and inadvertently or adversely affecting the block or the entire super-large integrated circuit. According to the method of the circuit diagram 70 provided by the present invention, the designer can avoid or reduce the influence of parasitic components in the early stage of design and layout. _______- 13-This paper size applies to China National Standard (CNS) A4 (210 X 297) (Centimeter)

Binding

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ring. In this way, a larger parasitic capacitance is inadvertently caused due to the reduction of the parasitic resistance alone, as shown in Figures 2A, 2B, 3A and 3B. Avoid it before it occurs. ; The layout of the mother-individual block 72 (block 82) is mixed with the full-chip layout (square! Block 86), such as arrow 96. Parasitic extraction from full-chip layout (box 86): Import parasitic database 90, such as arrow 98, so that all parasitic acquisitions can be applied; Reverse Annotation (box 94) of Beixun, such as arrow 100 to The last φ step of the full-chip simulation (block 102). Provide all parasitics at any time before full-chip simulation |

The most important thing is that the optimal degree of the ultra-large integrated circuit and its component blocks is very important. This also shortens the engineer's design and layout of the ultra-large integrated circuit. Time to repeat the job. f The above description is for explanation only and shall not limit the present invention. Those who are familiar with this can: change and modify the methods described without departing from the spirit and scope of the present invention. In particular, the present invention is not limited to very large integrated circuits of a specific Ar size or type, or—blocks with Tesselmes, and the present invention is not limited to the same order and number of steps described. ·--14-This paper is suitable for household use ®

Claims (1)

518488 A8 B8 C8 The method and method of designing and laying out an integrated circuit with parasitic elements includes the following steps: 1. Initially design each part of the integrated circuit; Evaluate the design by computer simulation;-Once the preliminary design and simulation steps are completed , That is, manipulating parasitic elements Install the training information, and store the extracted information in a database shared by all parts of the integrated circuit; continuously reverse-comment the information stored in the database to facilitate the design simulation and subsequent steps; successful simulation area Before and after the block design, the layout is made using the parasitic capture information of each part of the integrated circuit; and the full chip layout of the integrated circuit is manufactured and simulated using the "parasitic capture information of the integrated circuit". 2 A method for the design and layout of a very large integrated circuit (VLSI). The very large integrated circuit has a plurality of blocks and multiple parasitic elements. The method includes the following steps. One block; preliminary simulation of the design of each block; the same as 4 to extract the information of the parasitic components identified in each block, and store the information obtained in this way in the data shared by all blocks In the library; annotate the parasitic capture information for each block in a continuous manner to facilitate the initial design, simulation and subsequent steps; after successfully simulating the block design, use the parasitic capture information to make each area -15-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) C8 C8 . The layout of the block design; using the parasitic capture information to make a s ^ clothing 丨 the king of the Japanese film layout; and using the parasitic elements of the reverse < Π 4 release to plan the full chip cloth to optimize the wafer design. 3 If the scope of the patent application is the 2nd item, the parasitic capture information is also derived from the Wang Yue film layout, and all the capture information of the reverse annotation disk stored in the database is applied to the full chip Layout steps. ^ 4-An improved ultra-large integrated circuit made by the method described in item 2 of the patent application. A method for the design and layout of a very large integrated circuit (VLSI). The very large integrated circuit includes a dynamic random access memory (DRAM) having a plurality of parasitic elements with a width of less than 0.2 microns and a significant influence on signal timing. The method includes the following steps: preliminary design of each part of the ultra large integrated circuit; evaluation of the design by computer simulation; extraction of the parasitic elements as part of the preliminary design and simulation steps, and the extraction The information is stored in a database that is shared by all parts of the ultra-large integrated circuit. The information in the database is continuously reverse-annotated. The information in the library is used to optimize the preliminary design, simulation and subsequent steps to make the parasites The influence of the components is minimized; after successful simulation, the parasitics of each part of the ultra-large integrated circuit are used to make the layout; and the parasitic capture information is used to make and simulate the full-scale of the ultra-large integrated circuit. 16-This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297mm) • The layout of the chip makes the operation of this ultra-large integrated circuit reach the maximum Good degree. 6 The design and layout of a dynamic random access memory (DRAM). The dynamic random access memory has a plurality of blocks and has a plurality of parasitic elements with significant time series. The method includes the following steps. · 'Initially design each block in a parallel and parallel manner; Initially simulate the design of each block; Extract the information of the parasitic elements identified in each block, and set 2 = The information is stored in data shared by all blocks. The parasitic capture information is reverse-annotated for each block in a continuous manner to optimize the initial design, simulation and subsequent steps, so that the impact of the parasitic elements is reduced. To the minimum; after successfully simulating the block design, use the parasitic capture information to make the layout of each block design; use the parasitic capture information to make a full-chip layout; and use the reverse annotation of the parasitic elements to simulate This full-wafer layout to optimize the wafer design. For example, the method in the sixth item of the patent application, wherein the parasitic operation information is also stored in the database, and the reverse annotation and all the extracted information are applied to the full-chip layout step. For example, Fang Mu ^, < 10,000 & of the scope of patent application, wherein the width of the dynamic random access memory is less than 0.2 micrometers, and the sigh of sigh is mainly due to the delay of the wire rather than the delay of the wire. Gate delay. The improved dynamics produced by the method follow a kind of patent application scope No. 6 A BCD 518488 Sixth, patent application scope. Machine access memory. 10 — A method for the design and layout of a very large integrated circuit (VLSI). The very large integrated circuit includes multiple high-density dynamic random access memories, each of which has a plurality of blocks. And has a signal delay mainly derived from wire delay rather than gate delay, the method includes the following steps: preliminary design of each block in a parallel manner; preliminary simulation of each block design; continuous acquisition of parasites block by block Component information, and store the extracted information in a database shared by all blocks; in a continuous manner, annotate the parasitic retrieved information for each block in a continuous manner to facilitate the initial design, simulation and follow-up Steps; If defects are found, repeat the preliminary design and simulation steps in one block; After successfully simulating the block design, 'use the parasitic capture information to make the layout of each block design; use the parasitic capture information to make a Full-chip layout; and back-annotation of the parasitic elements to simulate the full-chip layout so that the parasitic elements can The effect of circuit operation is minimized. -18-This paper size is in accordance with Chinese National Standard (CNS) A4 (21 × 297 mm)