EP1291878A2 - Steuereinrichtung zur Steuerung von Burst-Zugriffen - Google Patents
Steuereinrichtung zur Steuerung von Burst-Zugriffen Download PDFInfo
- Publication number
- EP1291878A2 EP1291878A2 EP02102326A EP02102326A EP1291878A2 EP 1291878 A2 EP1291878 A2 EP 1291878A2 EP 02102326 A EP02102326 A EP 02102326A EP 02102326 A EP02102326 A EP 02102326A EP 1291878 A2 EP1291878 A2 EP 1291878A2
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- European Patent Office
- Prior art keywords
- access
- address
- memory
- burst
- memory bank
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
Definitions
- the invention relates to a control device for controlling burst accesses to a Synchronous dynamic, at least two memory banks having semiconductor memory device. Moreover, the invention relates to a method for controlling burst accesses.
- SDRAMs Synchronous Dynamic Semiconductor Memory Devices
- preparation cycles pre-loading (precharge) and activate (activate)
- activate activate
- random burst accesses d. H. for read or write accesses to the memory, where with a Command several data words are to be read out or written in the memory This can be very disturbing, since just such burst accesses to enable a fast data access.
- the invention is therefore based on the object of specifying a control device and a method for controlling and readdressing burst accesses to a synchronous dynamic semiconductor memory device having at least two memory banks, with which these time losses can be largely reduced or even completely avoided.
- a control device which has an address conversion unit for converting a logical access address into physical access addresses by splitting the burst access into at least two sub-burst accesses, wherein a first physical access address comprises a first memory area of a first memory bank addressed for a first partial burst access and wherein a second physical access address addresses a second memory area of a second memory bank for a second partial burst access.
- a first physical access address comprises a first memory area of a first memory bank addressed for a first partial burst access
- a second physical access address addresses a second memory area of a second memory bank for a second partial burst access.
- the invention is based on the finding that it is advantageous for each burst access the memory bank being accessed will switch, regardless of whether a page change (page or row change) takes place or not.
- the invention a readdressing that ensures that the memory bank between two is switched to successive accesses and the resulting virtual (logical) address space completely on a correspondingly large, real existing (physical) address space maps, if possible without any flaws or double assignments arise.
- a burst access to a specific logical access address the memory area is converted into two sub-burst accesses, each of the two Part-Burst accesses to another memory bank and therein each one specific Memory area addressed. This can be ensured that no or only minimal Delays caused by preparation cycles. Namely while the first Partial burst access is already performed, that is already written to the first memory bank or read from the first memory bank, can simultaneously prepare of the second partial burst access.
- control device is in the Subclaims specified. Due to the advantageous embodiment according to claim 2, after which the column addresses of the first and second physical access addresses Connecting to each other can be achieved in a simple way that the physical Address space, d. H. the memory area present in the semiconductor memory device, is fully occupied without causing any defects or duplicate documents. The logical one Address space of the logical access addresses can thus easily to a correspondingly large physical address space can be completely mapped.
- the greatest possible time savings can be achieved in particular by the fact that - like already mentioned and as stated in claim 3 - during a first partial burst access a second partial burst access is already prepared. If the first part burst access is finished, thus directly the second partial burst access can be executed be, d. H. be read or written without any delay through preparation cycles arises.
- a first burst is divided into first and second sub-burst accesses to a first and second memory area of the first and second memory banks
- a second burst access is divided into first and second partial burst accesses each to the same two memory banks, but to other memory areas be addressed.
- the addressing is done so that the memory areas in the first and second memory bank connect to each other to the simple and to achieve complete filling of the physical memory area.
- a compression of the physical address space d. H.
- physical addresses have a larger number of bits, preferably one more bit, than logical addresses.
- M memory banks of the physical address space on N / 2 memory banks in the logical address space are mapped by the logical addressing a bit, namely, for example, the memory bank of the physical Address space determining bit is omitted.
- the inventive Control unit for read and write accesses always a burst with the same even number be made of words. It should be a dedicated or exclusive storage area be provided for the accesses that is used only with this type of bursts, otherwise the data of the memory could be overwritten by mistake.
- the inventive method is particularly useful when transferring large amounts of data and in hardware architectures that do not need a cache must, d. h. where re-sorting the data prior to memory access is not possible or makes sense. Benefits result in particular with close successive accesses, d. H. with time-critical data throughput to different areas within the dedicated memory and frequent paging (row or page change) as well as bursts of size 4 onwards.
- control arrangement according to the invention with the semiconductor memory device can Particularly advantageous for video applications are used in which the Speed advantage that the arrangement offers is particularly important as a video data stream under no circumstances must tear off, otherwise it comes immediately to image disturbances.
- FIG. 1 shows a schematic block diagram of a control of a synchronous dynamic semiconductor memory (SDRAM).
- SDRAM synchronous dynamic semiconductor memory
- a control device 1 which receives the following signals as input signals: chip select signal CS, read-write signal W / R , Address signal via an address bus ADDR0-21 with (in the present example) 22-bit width.
- Data can be written in via a data write bus DW0-15 having (in the present example) 16-bit width
- read data can be output via a data read bus DR0-15 with (in the present example) 16-bit width.
- the control device 1 As output signals, the control device 1 generates the following signals: chip selection signal CS, row activation strobe RAS, column activation signal (column address strobe) CAS, write enable WE, address signal above an address bus ADDR0-11 with (in this example) 12-bit width and memory bank select signal (bank) BA0-1. Via a data write bus DOUT0-15 with (in this Example) 16-bit width data can be output for writing, while via a data read bus DIN0-15 with (in this example) 16 bit width Data can be read.
- the signals output by the control device 1 are sent to a memory unit (shell). 2, which surrounds the actual semiconductor memory device (SDRAM) 3. This essentially sets the data write bus DOUT0-15 and the data read bus DIN0-15 to a common data bus DQ0-15. Possibly. can also have another test logic in the memory unit 2 to be integrated.
- a memory unit shell
- SDRAM semiconductor memory device
- FIG. 2a shows the address to which each should be accessed, where "*" as a placeholder for non-representable components the address philngiert.
- FIG. 2b shows the memory bank selection signal BA, where 0 or 1 is the Number of the selected memory bank.
- FIG. 2c shows the chip selection signal CS
- Figure 2d shows the row address signal RAS
- Figure 2e shows the column address signal CAS
- Figure 2f shows the write signal WE.
- figure 2g shows a clock signal RCLK.
- FIG. 2h shows the data write bus DOUT, where concrete Data is shown.
- Figure 2i shows the data read bus DIN, where also data are shown.
- a control device 10 according to the invention is shown in FIG. Entrance and Output signals are identical to the input and output signals described in FIG the control device 1, so that compatibility with all synchronous dynamic Semiconductor memory devices is given.
- the data lines DW0-15 and DR0-15 are "looped through" from the input to the output.
- the control and generation of the control signals of the SDRAM and thus the function of the Splitting of a burst access to at least two partial burst accesses takes one so-called state machine 11 (Finite State Machine).
- state machine 11 Finite State Machine
- the state machine 11 signals the address converter unit 12 also, when to generate which address.
- the address conversion unit 12 converts the incoming via the input address bus ADDR0-21 logical access addresses into physical access addresses and a memory bank signal BA0-1 um, where the physical access addresses are via the output address bus ADDR0-11 be passed to the SDRAM.
- the conversion according to the invention The logical access addresses in physical access addresses should now be determined on the basis of Figures 4 and 5 are explained in more detail.
- FIG. 4 shows a first possibility of an address conversion according to the invention, namely the so-called cross-addressing.
- This is a logical address space 4, which is also as original or virtual address space, with four memory banks in the present case (Bank 0 to Bank 3).
- This logical address space 4 is defined by logical access addresses addressed to the memory device 10, for example, if accessed in a burst access to a memory area of the SDRAM shall be.
- FIG. 4 a physical address space 5, which is also referred to as a real address space, is shown.
- This physical address space also has four memory banks (Bank 0 to Bank 3), which, however, does not necessarily have to be the case.
- Individual memory cells of the SDRAM are explicitly addressed in this physical address space 5 by physical access addresses.
- the conversion of the logical access addresses of the logical address space 4 into physical access addresses of the physical address space 5 takes place according to the invention by the address converter unit 12. In the example shown in FIG. 4, two burst accesses a and b, each of length four, are to take place one after the other.
- first the first burst access a which addresses a logical address area of the memory bank 0 of the logical address space 4, is split into two partial burst accesses 1a and 2a, each of length two.
- the first partial burst access 1a addresses a first memory area of the first memory bank 0, while the second partial burst access 2a addresses a second memory area of the second memory bank 1.
- the sub-burst accesses 1a and 2a are thus executed one after the other, ie, the memory area 0 and the memory bank 1 of the physical memory are successively accessed.
- the advantage lies in the fact that during the execution of the first partial burst access 1a, the second partial burst access 2a can already be prepared, since in this case another memory bank is accessed. A waiting time through preparation cycles is thus eliminated.
- Burst access b is again split into two sub-burst accesses 1b and 2b.
- the Adressumwandlung takes place in such a way that the first partial burst access 1b to a second memory area of the memory bank 0 of the physical address space 5 accesses, during the second partial burst access 2b a memory area of the memory bank 1 of physical address space 5 addressed.
- the addressing is preferably carried out such that the data of the sub-burst accesses 1a and 1b or 2a and 2b respectively to each other connect so that in both memory banks 0 and 1 of the physical address space 5 the same memory areas are described or read after both Burst accesses a and b were executed.
- the address conversion according to the invention is a logical Access address A of a memory bank X in a burst access of length N such that a first partial burst access of length N / 2 to a first physical access address B a first memory bank Y and a second partial burst access of length N / 2 to one second physical access address C of a second memory bank Y + Z, where Z an integer other than 0, preferably +1, if Y is an even integer, or -1, if Y is an odd integer.
- the first memory bank Y corresponds the physical addressing of the memory bank X of the logical addressing; the first physical access address B of the physical addressing preferably corresponds the logical access address A of the logical addressing and the second physical Access address C preferably corresponds to the logical access address A + N / 2.
- FIG. 5 shows a second possibility according to the invention for converting logical access addresses shown in physical access addresses.
- This is a logical one again Address space 4 'and a physical address space 5 shown, wherein the logical address space 4 'but with respect to the physical address space 5 and with respect to the in FIG 4 logical address space 4 is compressed, in the example by a factor of 2.
- N memory banks of the physical address space N / 2 memory banks in the logical address space 4 'or from A physical access addresses become A / 2 logical access addresses with a reduction of the address space by a factor of 2. This corresponds to the omission of a bit in the addressing in the logical address space 4 ' towards the addressing in the physical address space 5.
- a burst access a in which in the logical address space 4 'a logical access address A a memory bank I is addressed in this embodiment of the invention
- the partial burst access 1a is a physical access address B of a first memory bank Y
- the partial burst accesses 1a and 2a are thereby again in turn, while performing the first sub-burst access 1a, the second sub-burst access 2a is prepared to be unnecessary Waiting times for preparation commands to avoid.
- the conversion according to the invention of the logical access addresses into physical access addresses takes place in the method described in Figure 5 by adding a bits; in other words, the logical access addresses arise from the physical Access addresses by omitting a bit, in particular of the memory banks in the physical Address space 5 identifying memory bank bits.
- FIG. There is shown a logical access address 6, consisting of 22 address bits a0-a21, the is supplied via the address bus of the control device in a burst access.
- the address converter unit generated physical address 7 which consists of several components 71 to 74 exists.
- the lowest eight bits a0 to a7 of the logical access address 6 to the column address 71 with the column address bits c0 to c7, and the next 12 bits a8 to a18 of the logical access address 6 become the row address 72 implemented with the row address bits r0 to r11.
- the top two address bits a20 and a21 correspond to the memory bank bits 73, 74 of the SDRAM, with the uppermost address bit a21 on the upper bank bit 74 (b1) is mapped while the lower address bit a20 outmasked becomes.
- the memory bank bit 73 according to the invention only in the Adresswandler worn created or added, d. H.
- FIG. 5 Signal curves in a control device according to the invention are shown in FIG the case of the address compression described in Figures 5 and 6.
- Read accesses R1a, R2a, R1b, R2b are shown, wherein in the read accesses R1a and R1b to the Memory bank 0 (see memory bank signal in Figure 7b) and read accesses R2a and R2b is accessed on the Speicherbank1.
- the Memory bank 0 prepared by precharge P and activate A before the first read access R1a to the memory bank 0 takes place.
- each burst access is split to more than two sub-burst accesses, and the different physical access addresses of the different memory banks in the Also, physical address space does not necessarily have to be connected to each other.
- the partial burst accesses can also have a different length; however, an implementation with sub-burst accesses of the same length is simpler.
- the invention is not limited to certain types of SDRAMs, but for any SDRAMs with at least 2 memory banks applicable, since, as in Figure 3 has been shown, with respect to the input and output signals of the controller no Change has been made to existing control facilities.
- the essential Elements of the control device for carrying out the inventive Incidentally, the method could also be surrounded by the SDRAM (3 in FIG. 1) Memory unit (2 in Figure 1) to be integrated.
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Abstract
Description
Diese Aufgabe wird erfindungsgemäß durch eine Steuereinrichtung gemäß Anspruch 1 gelöst, welche eine Adresswandlereinheit aufweist zur Umwandlung einer logischen Zugriffsadresse in physikalische Zugriffsadressen durch Aufspaltung des Burst-Zugriffs in wenigstens zwei Teil-Burst-Zugriffe, wobei eine erste physikalische Zugriffsadresse einen ersten Speicherbereich einer ersten Speicherbank für einen ersten Teil-Burst-Zugriff adressiert und wobei eine zweite physikalische Zugriffsadresse einen zweiten Speicherbereich einer zweiten Speicherbank für einen zweiten Teil-Burst-Zugriff adressiert. Die genannte Aufgabe wird außerdem gelöst durch ein Verfahren gemäß Anspruch 7.
- Figur 1
- ein Blockschaltbild mit einer Steuereinrichtung für eine Halbleiterspeichervorrichtung,
- Figur 2
- Signalverläufe bei einem bekannten wahlfreien sequentiellen Verfahren,
- Figur 3
- ein Blockschaltbild einer erfindungsgemäßen Steuereinrichtung,
- Figur 4
- ein Diagramm zur Erläuterung der erfindungsgemäßen Kreuzadressierung,
- Figur 5
- ein Diagramm zur Erläuterung der erfindungsgemäßen Kompression des Adressraumes,
- Figur 6
- die Adresszuordnung von logischem und physikalischem Adressraum, und
- Figur 7
- Signalverläufe bei dem erfindungsgemäßen Verfahren.
In dem in Figur 4 gezeigten Beispiel sollen zwei Burst-Zugriffe a und b jeweils der Länge vier nacheinander erfolgen. Erfindungsgemäß wird zunächst der erste Burst-Zugriff a, der einen logischen Adressbereich der Speicherbank 0 des logischen Adressraumes 4 adressiert, in zwei Teil-Burst-Zugriffe 1a und 2a jeweils der Länge zwei aufgespalten. Der erste Teil-Burst-Zugriff 1a adressiert dabei einen ersten Speicherbereich der ersten Speicherbank 0, während der zweite Teil-Burst-Zugriff 2a einen zweiten Speicherbereich der zweiten Speicherbank 1 adressiert. Zur Ausführung des Burst-Zugriffes a werden somit nacheinander die Teil-Burst-Zugriffe 1a und 2a ausgeführt, d. h., es wird nacheinander auf die Adressbereiche der Speicherbank 0 und der Speicherbank 1 des physikalischen Speichers zugegriffen. Der Vorteil liegt dabei darin, dass während der Durchführung des ersten Teil-Burst-Zugriffes 1a bereits der zweite Teil-Burst-Zugriff 2a vorbereitet werden kann, da dabei ja auf eine andere Speicherbank zugegriffen wird. Eine Wartezeit durch Vorbereitungszyklen entfällt somit.
Claims (8)
- Steuereinrichtung (10) zur Steuerung von Burst-Zugriffen auf eine synchrone dynamische, wenigstens zwei Speicherbänke aufweisende Halbleiterspeichervorrichtung (3) mit einer Adresswandlereinheit (12) zur Umwandlung einer logischen Zugriffsadresse in physikalische Zugriffsadressen durch Aufspaltung des Burst-Zugriffs in wenigstens zwei Teil-Burst-Zugriffe, wobei eine erste physikalische Zugriffsadresse einen ersten Speicherbereich einer ersten Speicherbank für einen ersten Teil-Burst-Zugriff adressiert und wobei eine zweite physikalische Zugriffsadresse einen zweiten Speicherbereich einer zweiten Speicherbank für einen zweiten Teil-Burst-Zugriff adressiert.
- Steuereinrichtung nach Anspruch 1,
dadurch gekennzeichnet, dass die Steuereinrichtung (10) derart ausgestaltet ist, dass die Spaltenadressen der ersten und zweiten physikalischen Zugriffsadressen aneinander anschließen. - Steuereinrichtung nach Anspruch 1,
dadurch gekennzeichnet, dass die Steuereinrichtung (10) derart ausgestaltet ist, dass während eines Teil-Burst-Zugriffs auf den durch die erste physikalische Zugriffsadresse adressierten Speicherbereich einer ersten Speicherbank ein anderer Teil-Burst-Zugriff auf einen durch eine weitere physikalische Zugriffsadresse adressierten Speicherbereich einer anderen Speicherbank vorbereitet wird. - Steuereinrichtung nach Anspruch 1,
dadurch gekennzeichnet, dass die Adresswandlereinheit (12) derart ausgestaltet ist, dass ein Burst-Zugriff der Länge N auf eine logische Zugriffsadresse A einer Speicherbank X aufgeteilt wird in einen ersten Teil-Burst-Zugriff der Länge N/2 auf eine erste physikalische Zugriffsadresse B, vorzugsweise die Zugriffsadresse A, einer ersten Speicherbank Y, vorzugsweise die Speicherbank X, und einen zweiten Teil-Burst-Zugriff der Länge N/2 auf eine zweite physikalische Zugriffsadresse C, vorzugsweise die Zugriffsadresse A+N/2 einer zweiten Speicherbank Y+Z, vorzugsweise die Speicherbank X+Z, wobei Z eine ganze Zahl ungleich Null ist, vorzugsweise +1, wenn Y eine gerade ganze Zahl ist, oder -1, wenn Y eine ungerade ganze Zahl ist. - Steuereinrichtung nach Anspruch 1,
dadurch gekennzeichnet, dass die Adresswandlereinheit (12) derart ausgestaltet ist, dass ein Burst-Zugriff der Länge N auf eine logische Zugriffsadresse A einer Speicherbank X aufgeteilt wird in einen ersten Teil-Burst-Zugriff der Länge N/2 auf eine erste physikalische Zugriffsadresse B einer ersten Speicherbank Y und einen zweiten Teil-Burst-Zugriff der Länge N/2 auf eine zweite physikalische Zugriffsadresse B einer zweiten Speicherbank Y+Z, wobei Z eine ganze Zahl ungleich Null ist und wobei vorzugsweise A gleich B ist. - Steuereinrichtung nach Anspruch 5,
dadurch gekennzeichnet, dass die Adresswandlereinheit (12) zur Umwandlung der logischen Zugriffsadressen in physikalische Zugriffsadressen durch Hinzufügen wenigstens eines Bits zur Bestimmung der Speicherbank ausgestaltet ist. - Verfahren zur Steuerung von Burst-Zugriffen auf eine synchrone dynamische, wenigstens zwei Speicherbänke aufweisende Halbleiterspeichervorrichtung (3), wobei eine logische Zugriffsadresse in physikalische Zugriffsadressen durch Aufspaltung des Burst-Zugriffs in wenigstens zwei Teil-Burst-Zugriffe umgewandelt wird, wobei eine erste physikalische Zugriffsadresse einen ersten Speicherbereich einer ersten Speicherbank für einen ersten Teil-Burst-Zugriff adressiert und wobei eine zweite physikalische Zugriffsadresse einen zweiten Speicherbereich einer zweiten Speicherbank für einen zweiten Teil-Burst-Zugriff adressiert.
- Video-Speicheranordnung mit einer Steuereinrichtung nach einem der Ansprüche 1 bis 7, wobei die Halbleiterspeichervorrichtung (3) zum Speichern von Videodaten vorgesehen ist.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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DE10143999 | 2001-09-07 | ||
DE10143999 | 2001-09-07 | ||
DE2001150125 DE10150125A1 (de) | 2001-10-11 | 2001-10-11 | Steuereinrichtung zur Steuerung von Burst-Zugriffen |
DE10150125 | 2001-10-11 |
Publications (3)
Publication Number | Publication Date |
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EP1291878A2 true EP1291878A2 (de) | 2003-03-12 |
EP1291878A3 EP1291878A3 (de) | 2008-11-19 |
EP1291878B1 EP1291878B1 (de) | 2013-04-17 |
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Application Number | Title | Priority Date | Filing Date |
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EP02102326.2A Expired - Lifetime EP1291878B1 (de) | 2001-09-07 | 2002-09-06 | Steuereinrichtung zur Steuerung von Burst-Zugriffen |
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US (1) | US6912615B2 (de) |
EP (1) | EP1291878B1 (de) |
JP (1) | JP2003216482A (de) |
CN (1) | CN1280734C (de) |
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US9128632B2 (en) | 2009-07-16 | 2015-09-08 | Netlist, Inc. | Memory module with distributed data buffers and method of operation |
KR20160038034A (ko) | 2013-07-27 | 2016-04-06 | 넷리스트 인코포레이티드 | 로컬 동기화를 갖는 메모리 모듈 |
JP7235389B2 (ja) * | 2019-03-29 | 2023-03-08 | ラピスセミコンダクタ株式会社 | 半導体記憶装置 |
CN112885385B (zh) * | 2021-02-23 | 2022-07-29 | 长江存储科技有限责任公司 | 非易失性存储器及其读取方法 |
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US5636173A (en) | 1995-06-07 | 1997-06-03 | Micron Technology, Inc. | Auto-precharge during bank selection |
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EP0124799B1 (de) * | 1983-04-13 | 1990-10-31 | Nec Corporation | Speicherzugriffseinrichtung in einem Datenverarbeitungssystem |
US5485594A (en) * | 1992-07-17 | 1996-01-16 | International Business Machines Corporation | Apparatus and method using an atomic fetch and add for establishing temporary ownership of a common system resource in a multiprocessor data processing system |
JPH06301596A (ja) * | 1993-04-09 | 1994-10-28 | Mitsubishi Electric Corp | マイクロプロセッサ |
US5611071A (en) * | 1995-04-19 | 1997-03-11 | Cyrix Corporation | Split replacement cycles for sectored cache lines in a 64-bit microprocessor interfaced to a 32-bit bus architecture |
US5751979A (en) * | 1995-05-31 | 1998-05-12 | Unisys Corporation | Video hardware for protected, multiprocessing systems |
JP2970513B2 (ja) * | 1996-01-30 | 1999-11-02 | 日本電気株式会社 | 半導体記憶装置およびその制御方法 |
DE69727465T2 (de) * | 1997-01-09 | 2004-12-23 | Hewlett-Packard Co. (N.D.Ges.D.Staates Delaware), Palo Alto | Rechnersystem mit Speichersteuerung für Stossbetrieb-Übertragung |
US5960468A (en) * | 1997-04-30 | 1999-09-28 | Sony Corporation | Asynchronous memory interface for a video processor with a 2N sized buffer and N+1 bit wide gray coded counters |
GB2332539B (en) * | 1997-12-17 | 2003-04-23 | Fujitsu Ltd | Memory access methods and devices for use with random access memories |
US6138214A (en) * | 1997-12-19 | 2000-10-24 | Siemens Aktiengesellschaft | Synchronous dynamic random access memory architecture for sequential burst mode |
US6415374B1 (en) * | 2000-03-16 | 2002-07-02 | Mosel Vitelic, Inc. | System and method for supporting sequential burst counts in double data rate (DDR) synchronous dynamic random access memories (SDRAM) |
-
2002
- 2002-09-04 CN CNB021472912A patent/CN1280734C/zh not_active Expired - Lifetime
- 2002-09-06 US US10/236,176 patent/US6912615B2/en not_active Expired - Lifetime
- 2002-09-06 EP EP02102326.2A patent/EP1291878B1/de not_active Expired - Lifetime
- 2002-09-09 JP JP2002262572A patent/JP2003216482A/ja active Pending
Patent Citations (1)
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US5636173A (en) | 1995-06-07 | 1997-06-03 | Micron Technology, Inc. | Auto-precharge during bank selection |
Also Published As
Publication number | Publication date |
---|---|
EP1291878A3 (de) | 2008-11-19 |
CN1409226A (zh) | 2003-04-09 |
JP2003216482A (ja) | 2003-07-31 |
US6912615B2 (en) | 2005-06-28 |
US20030074517A1 (en) | 2003-04-17 |
EP1291878B1 (de) | 2013-04-17 |
CN1280734C (zh) | 2006-10-18 |
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