EP1259978A2 - Procede et dispositif permettant de produire des structures de composants groupe-iii-n, groupe-iii-v-n et metal-azote sur des substrats si - Google Patents

Procede et dispositif permettant de produire des structures de composants groupe-iii-n, groupe-iii-v-n et metal-azote sur des substrats si

Info

Publication number
EP1259978A2
EP1259978A2 EP01921151A EP01921151A EP1259978A2 EP 1259978 A2 EP1259978 A2 EP 1259978A2 EP 01921151 A EP01921151 A EP 01921151A EP 01921151 A EP01921151 A EP 01921151A EP 1259978 A2 EP1259978 A2 EP 1259978A2
Authority
EP
European Patent Office
Prior art keywords
layer
temperature
layers
group iii
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01921151A
Other languages
German (de)
English (en)
Inventor
Armin Dadgar
Alois Krost
Michael Heuken
Assadulah Alam
Oliver SCHÖN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aixtron SE
Original Assignee
Aixtron SE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aixtron SE filed Critical Aixtron SE
Publication of EP1259978A2 publication Critical patent/EP1259978A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth

Definitions

  • the invention relates to a method for producing group III-N, group III-V-N and metal-nitrogen component structures on Si substrates and to a corresponding device.
  • a high level of homogeneity of the layers is also necessary.
  • a layer thickness variation in the monolayer range with an active In x Ga N_ x N quantum well layer, such as is used in LEDs can lead to a shift of the maximum emission wavelength by several nanometers. With lasers, such a variation in wavelength is completely unacceptable.
  • the indium concentration which is strongly dependent on the deposition temperature and the temperature of the surrounding walls.
  • the low-temperature seed or buffer layers on the Si substrate must also have the best possible homogeneity so that the layer above has a constant quality over the wafer.
  • the invention is based on the object of specifying a method and a device for the cost-effective production of group III-N or group III-VN component structures on Si substrates.
  • a solution to this problem according to the invention is specified in the independent claims directed to a method or a device.
  • a horizontal MOCVD reactor is used in a manner known per se which, owing to the structure of the growth chamber and the rotating susceptors, ensures great homogeneity and reproducibility of the deposited layers. Possible embodiments of such MOCVD reactors are described below.
  • the advantage of the susceptors rotating on a gas cushion is the improved homogeneity of the layers with virtually no abrasion. In other, mechanically driven systems, particles are created by the abrasion
  • Layer growth or the purity of the layers can negatively affect.
  • MOCVD systems used according to the invention and Si substrates inexpensive production of Group III-N components is possible with a high component yield and low use of source materials.
  • the efficiency of Group III elements e.g. B. Ga is over 10% in a multi-disk reactor.
  • the precise control of the substrate temperature as well as the temperature of the surrounding walls or the ceiling of the growth chamber is very important for high reproducibility and homogeneity, since the installation depends very sensitively on these parameters.
  • a special gas inlet geometry is used, which is distinguished by the fact that undesired cross-reactions between the gases do not take place.
  • the special temperature profile in the The reactor and the temperature management and control system are designed in such a way that any interactions of the gases are suppressed, so that reproducibility is guaranteed and the efficiency of the raw materials is increased.
  • the use of a low-temperature seed and / or a buffer layer enables the substrate in the MOCVD system described to be uniformly grown or grown over.
  • the device is therefore designed in such a way that precise control of the static and dynamic temperature distribution on the Si substrates is possible.
  • the temperature interval is 300-1600 ° C. This system is necessary for both the seed and active layers.
  • the germ layer is understood to mean a three-dimensional layer or three-dimensional islands which are not necessarily closed and which are a few nanometers thick and which, in spite of possibly poor crystalline and / or stoichiometric properties, form the basis for the subsequent one
  • Layer growth serves or from which the further layer growth starts.
  • epitaxy on Si it is often necessary so that a preferred orientation from non-polar Si to, for example, polar GaN is given and the buffer or component layer can be deposited on it in the first place.
  • growth on Si is also possible, for example directly with a low-temperature buffer layer as the first layer.
  • Such seed and / or buffer layers on Si are - according to the invention of great importance - for the successful growth of Group III-N and Group III-VN layers on Si. Because only a closed germ and / or buffer layer, for example made of a Group III-V material such as z. B.
  • the method according to the invention is made possible on large-area substrates or m multi-wafer systems by the homogeneity of the layers deposited in these systems, because a uniformly thick seed and / or buffer layer is e.g. necessary to avoid silicon nitriding in partial areas of the substrate due to a locally too thin seed and / or buffer layer. Furthermore, the homogeneity of the inferior germ and / or buffer layer from the crystalline point of view is important in order to ensure a uniform quality of the applied layers over a large area. If the thickness is inhomogeneous, the seed and / or buffer layer does not crystallize uniformly at higher temperatures and then leads to fluctuations in the crystalline quality and thus e.g. in the case of LED structures, fluctuations in the light output over large areas of the wafer.
  • the m-situ measurement of the reflectivity which is advantageously used serves to monitor the layer growth. Examples of such m-situ reflective Activity measurements are described in connection with the drawings. This allows the thickness and composition of the layer to be monitored during growth and, for example, to adjust the parameters in the event of a slight drift, so that the layers produced can be used or, for example, a decision can be made before the end of growth whether the layers continue to grow or later should be processed further.
  • the reflectivity measurement is very helpful in the growth of the low-temperature seed layer and / or the low-temperature buffer and the Group III-N layer deposited on the seed or buffer layer at higher temperatures.
  • the layer thickness and the smoothness or closeness of the deposited layers can be assessed very well.
  • Si tends to nitridate under NH 3 or other nitrogen starting materials which are used, for example, in group III-N layer growth for the nitrogen component at higher temperatures.
  • group III-N layer growth for the nitrogen component at higher temperatures.
  • growth of, for example, crystalline Group III-N layers is not possible on such nitrided Si. In most cases there is then no growth or of polycrystalline material which has a modified or low reflectivity, which can be observed in the measurement. If, for example, due to poor pretreatment of the substrate or poor substrate quality, the Group III-N layer deposited thereon is not completely closed, the underlying Si partially extends below the already deposited layer and thus leads to a unusable
  • Possibilities are specified in the subclaims as to how the variation in the layer and growth parameters can reduce the dislocation density and the formation of cracks in the applied component layer. These options can be used individually, or in combination, but also multiple and multiple combined. Since Si and, for example, GaN have different lattice constants and crystal lattices, dislocations are formed at the interface, among other things. The thermal lattice mismatch of these materials also leads to the formation of cracks from a layer thickness of approx. 1 ⁇ m, for example when cooling the layer [Monemar] or during growth when setting different temperatures for e.g. B. InGaN growth and AlGaN or GaN.
  • the temperature in MOCVD growth is often varied by several hundred degrees Celsius.
  • Nikishin et al. have shown that growth in the MBE can avoid the formation of cracks by growing a germ or buffer layer of, for example, A1N made alternately from metal and then nitriding [Nikishin].
  • This layer does not necessarily have to have a stoichiometric ratio of Group III to Group V components.
  • the materials mentioned in a subclaim also include so-called layer grids such as WSe 2 , which are soft in one direction, ie have sliding planes. This makes it possible to deposit layers with little dislocation and cracks.
  • Li et al. showed that by partially masking a group III nitride layer using methods such as ELO, ELOG or LEO, the layer deposited on it is at least less dislocated above the masked areas [Li]. Multiple combinations of this process can lead to layers with little dislocation. Furthermore, by applying such masks with a suitable expansion coefficient, the formation of cracks in the deposited Group III nitride layer can be reduced. The reduction m of the dislocation density can also be achieved with the method described by Iwaya et al. described growth of low-temperature intermediate layers take place [Iwaya]. The author describes how the dislocation density can be greatly reduced by layers that do not require any further processing, i.e.
  • the thermally induced stress and thus the cracking can be reduced or reduced.
  • the Si band gap is only about 1.1 eV
  • the photon energies generated with, for example, GaN-based components are usually significantly higher, in contrast to the use of sapphire substrates, a considerable part of the emitted photons is absorbed in Si.
  • the methods described in further subclaims can be used.
  • a metal of sufficient thickness is deposited on the substrate by means of evaporation, sputtering or
  • a partial high-quality overgrowth such as, for example, is preferably achieved by applying a partial masking, for example of SiO 2 and / or SiN x or metal strips from, for example, W on an AlN or GaN seed or buffer layer and the subsequent overgrowth in Kawaguchi et al. described enables [Kawaguchi].
  • the method according to the invention advantageously serves to reduce dislocations. This masking can also be carried out several times and also in a staggered arrangement, so that the efficiency of this layer as a reflector but also as a material-improving method is increased.
  • Light wavelength by applying one or more layers with different refractive indices to each other and / or to the epitaxial layer and / or the surrounding medium, which is usually air or at a LED is often a plastic.
  • the combination of two Bragg mirrors to create a vertical light beam is also very suitable for the lower mirror.
  • intermediate layers can be provided between the silicon substrate and active components for optimal adaptation to the respective task or use of the component structure to be produced.
  • Fig. 2 cross section through a multi-disc MOCVD
  • 1 shows a cross section through a MOCVD reactor used in the context of the invention for the coating of GaN compounds on (for example) 2 inch silicon wafers.
  • 1 designates a gas inlet with which gases for the production of a layer or buffer layer or the reflective layer m the reaction chamber are let in.
  • 2 denotes the area in which a substrate 4 on a rotating susceptor on a gas cushion and the gas inlet arrangement are arranged to avoid nitriding of the Si substrate.
  • a coil 3 is provided, which provides sufficient temperature homogeneity at 300 ° C, 530 ° C, 700 ° C, 1000 ° C, 1100 ° C and at 1600 ° C.
  • Reference numeral 5 designates an implementation for checking the substrate temperature.
  • Reference numeral 6 denotes thermostatting of the ceiling and the walls.
  • Reference numeral 7 designates optical windows for an m-situ measurement.
  • FIG. 2 shows a cross section through a further exemplary embodiment of a multi-disk MOCVD reactor for the coating of several silicon wafers with GaN compounds.
  • Reference numeral 1 designates a special gas inlet for a layer or buffer layer or the reflective layer.
  • Reference numeral 2 denotes a substrate and a gas outlet arrangement in order to avoid nitriding of the Si substrate.
  • Reference numeral 3 denotes a coil with sufficient temperature homogeneity at the same time at 300 ° C, 530 ° C, 700 ° C, 1000 ° C and 1100 ° C, 1600 ° C.
  • Numeral 4 denotes a rotating susceptor on a gas cushion.
  • Reference numeral 5 denotes an implementation for checking the substrate temperature.
  • Reference numeral 6 denotes thermostatting of the ceiling and the walls.
  • Reference numeral 7 designates optical windows for an m-situ measurement.
  • Figure 3 shows an embodiment of a detail of the growth observation window.
  • FIG. 4a, b, c show exemplary reflectivity measurements of GaN on a Si wafer.
  • the following layer structure and parameters apply to FIG. 4a:
  • FIGS. 3 and 4 correspond to those m of the previous FIGS. 1 and 2.
  • Group III elements from the third main group of the Periodic Table of the Elements
  • Group V elements from the fifth main group of the Periodic Table of the Elements except nitrogen
  • Group III-V compound semiconductors from elements of the third and fifth main group of the periodic table of the elements except nitrogen
  • Group III-VN compound semiconductors from elements of the third main group of the periodic table of elements with nitrogen and another element of the fifth main group of the periodic table of elements In Indium LED Light Emitting Device
  • NH 3 ammonia P phosphor sapphire A1 2 0 3 , aluminum oxide includes corundum
  • Si silicon In addition to ordinary Si substrates, substrates such as e.g. Silicon-on-insulator substrates included

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Led Devices (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

L'invention concerne un procédé et un dispositif de production de structures de composants groupe-III-N, groupe-III-V-N et métal-azote sur des substrats de Si par épitaxie en phase gazeuse organo-métallique. Le procédé ou le dispositif selon l'invention sont caractérisés en ce qu'une couche de germination basse température et/ou une couche tampon basse température est/sont réalisée(s) à partir d'un semi-conducteur du groupe III-V et/ou d'un semi-conducteur intermétallique métal-groupe-V ainsi qu'une couche de composant ou une séquence de couches composée de semi-conducteurs du groupe III-N, du groupe III-V-N ou de métal-groupe-V dans une chambre de croissance horizontale, de telle façon que l'on conserve une différence de température latérale minimale inférieure à 5 k, de préférence inférieure à 1K, une température de couvercle et/ou une température de paroi réglable(s) et une température d'un porte-substrat mis en rotation par un coussin gazeux. Les gaz réactionnels sont admis de telle façon qu'aucune interaction indésirable n'ait lieu entre les gaz de départ, et que le procédé puisse être observé sans perturber le processus de croissance.
EP01921151A 2000-03-02 2001-03-02 Procede et dispositif permettant de produire des structures de composants groupe-iii-n, groupe-iii-v-n et metal-azote sur des substrats si Withdrawn EP1259978A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10009945 2000-03-02
DE10009945 2000-03-02
PCT/DE2001/000777 WO2001065592A2 (fr) 2000-03-02 2001-03-02 Procede et dispositif permettant de produire des structures de composants groupe-iii-n, groupe-iii-v-n et metal-azote sur des substrats si

Publications (1)

Publication Number Publication Date
EP1259978A2 true EP1259978A2 (fr) 2002-11-27

Family

ID=7633093

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01921151A Withdrawn EP1259978A2 (fr) 2000-03-02 2001-03-02 Procede et dispositif permettant de produire des structures de composants groupe-iii-n, groupe-iii-v-n et metal-azote sur des substrats si

Country Status (5)

Country Link
US (1) US20030070610A1 (fr)
EP (1) EP1259978A2 (fr)
JP (1) JP2003526203A (fr)
KR (1) KR20020086595A (fr)
WO (1) WO2001065592A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10163394A1 (de) * 2001-12-21 2003-07-03 Aixtron Ag Verfahren und Vorrichtung zum Abscheiden kristalliner Schichten und auf kristallinen Substraten
US6818061B2 (en) * 2003-04-10 2004-11-16 Honeywell International, Inc. Method for growing single crystal GaN on silicon
JP5656401B2 (ja) * 2006-05-08 2015-01-21 フライベルガー・コンパウンド・マテリアルズ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツングＦｒｅｉｂｅｒｇｅｒ Ｃｏｍｐｏｕｎｄ Ｍａｔｅｒｉａｌｓ Ｇｍｂｈ Ｉｉｉ−ｎバルク結晶及び自立型ｉｉｉ−ｎ基板の製造方法、並びにｉｉｉ−ｎバルク結晶及び自立型ｉｉｉ−ｎ基板
US7825432B2 (en) * 2007-03-09 2010-11-02 Cree, Inc. Nitride semiconductor structures with interlayer structures
US8362503B2 (en) * 2007-03-09 2013-01-29 Cree, Inc. Thick nitride semiconductor structures with interlayer structures
KR102140789B1 (ko) 2014-02-17 2020-08-03 삼성전자주식회사 결정 품질 평가장치, 및 그것을 포함한 반도체 발광소자의 제조 장치 및 제조 방법
US20170352536A1 (en) * 2014-12-23 2017-12-07 Integrated Solar A method of epitaxial growth of a material interface between group iii-v materials and silicon wafers providing counterbalancing of residual strains
JP6903857B2 (ja) * 2017-06-02 2021-07-14 住友電工デバイス・イノベーション株式会社 半導体基板の製造方法

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GB8606748D0 (en) * 1986-03-19 1986-04-23 Secr Defence Monitoring surface layer growth
US5838029A (en) * 1994-08-22 1998-11-17 Rohm Co., Ltd. GaN-type light emitting device formed on a silicon substrate
US6348096B1 (en) * 1997-03-13 2002-02-19 Nec Corporation Method for manufacturing group III-V compound semiconductors
DE19725900C2 (de) * 1997-06-13 2003-03-06 Dieter Bimberg Verfahren zur Abscheidung von Galliumnitrid auf Silizium-Substraten
US6271104B1 (en) * 1998-08-10 2001-08-07 Mp Technologies Fabrication of defect free III-nitride materials
SG94712A1 (en) * 1998-09-15 2003-03-18 Univ Singapore Method of fabricating group-iii nitride-based semiconductor device
US6255198B1 (en) * 1998-11-24 2001-07-03 North Carolina State University Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby

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Title
See references of WO0165592A2 *

Also Published As

Publication number Publication date
WO2001065592A3 (fr) 2001-12-06
US20030070610A1 (en) 2003-04-17
KR20020086595A (ko) 2002-11-18
JP2003526203A (ja) 2003-09-02
WO2001065592A2 (fr) 2001-09-07

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