EP1234330A2 - Procede concernant les liaisons anodiques - Google Patents

Procede concernant les liaisons anodiques

Info

Publication number
EP1234330A2
EP1234330A2 EP00973305A EP00973305A EP1234330A2 EP 1234330 A2 EP1234330 A2 EP 1234330A2 EP 00973305 A EP00973305 A EP 00973305A EP 00973305 A EP00973305 A EP 00973305A EP 1234330 A2 EP1234330 A2 EP 1234330A2
Authority
EP
European Patent Office
Prior art keywords
bonding
wafer
silicon
sections
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP00973305A
Other languages
German (de)
English (en)
Inventor
Leif Bergstedt
Gert Andersonn
Britta Ottosson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Imego AB
Original Assignee
Imego AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9903798A external-priority patent/SE522141C2/sv
Application filed by Imego AB filed Critical Imego AB
Publication of EP1234330A2 publication Critical patent/EP1234330A2/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Definitions

  • the present invention relates to a method of bonding at least a first member to a second silicon member through anodic bonding.
  • EP 742 581 for example, relates to a method of making sealed cavities on silicon wafer surfaces by anodic bonding and with electrically insulated conductors through the sealing areas to connect functional devices inside the cavities to electrical terminals outside said cavities.
  • the conductors are provided through the use of doped buried crossings in a single crystal silicon substrate, thereby also allowing production of different kinds of integrated silicon devices, e.g. sensors.
  • Borosilicate glass plates are bonded onto a silicon (Si) wafer using so-called anodised bonding.
  • a plate of glass is arranged on a Si wafer under an amount of pressure.
  • the Si wafer and the glass are then heated up to some hundred degrees and a voltage is applied across the plates (glass and wafer) whereby the glass, which contains sodium (Na) ions migrate into the Si wafer, and a hermetic junction is obtained.
  • the object intended to be bonded to Si must contain Na-ions. usually through doping a glass with Soda lime glass.
  • borosilicate glass is that it matches the Si wafer characteristics, specially with respect to coefficient of expansion.
  • the electrical connection path is from one of an outside wire bonding area via a first contact diffusion down to a buried conductor which crosses below the sealing area of the cavity, and via a second contact diffusion to a second aluminium interconnection line which establishes connections to two piezo-resistors.
  • the main object of the present invention is to provide a method of providing a hermetical sealing between a first substrate and a silicon substrate.
  • the initially mentioned method comprises the steps of selectively depositing on said first member at least one bondable section before bringing said first and second members together for anodic bonding.
  • the first member is a glass wafer, specially a borosilicate glass wafer and said second wafer is a silicon wafer or the first member is a carrier wafer specially one of glass, ceramics or glass composite, such as LTCC (Low Temperature Cofired Ceramic) and said second wafer is a silicon wafer.
  • the bondable section comprises a paste containing Na ions.
  • the selective deposition is provided through screen printing or photo image forming.
  • said bonding is hermetical.
  • said first member comprises of a cover, that said second silicon member is a carrier for a functional device and said first member bonded to said second member provides a sealing for said functional device.
  • a third member is arranged as a carrying member for supporting said second member.
  • electrical connections are arranged out of said cover through said bonding sections and/or said third supporting member.
  • connections through said bonding sections are arranged on one of said first, second or third members before applying the bonding paste.
  • the bonding sections are provided on said first member.
  • a method of selectively bonding a first member to a second silicon member through anodic bonding comprises the steps of: providing the said first and second members, arranging said first member with bonding sections in predetermined sections, arranging said first and second members in a contacting position, pressing and heating said first and second members in said contacting position, and applying a voltage to said first and second members.
  • the second member is a silicon wafer comprising one or more active sections.
  • the first member is a glass wafer provided with frames corresponding to said active sections.
  • the invention also concerns a sensor comprising a lid, a silicon substrate and a carrying substrate, wherein said lid, silicon substrate and carrying substrate are bonded through the method f the invention.
  • the invention also concerns a biological circuit hermetically connected to a substrate using the method f the invention.
  • FIG. 1 schematically illustrates an arrangement produced according to the teachings of the invention
  • Figs. 2a, 2b shows the wafers for anodic bonding process according to the invention in plan view
  • Fig. 3 shows a cross-section along line III-III in figs. 2a and 2b, in a preassembled form
  • Figs. 4a, 4b,4c are cross-sections through different schematic embodiments showing wiring according to the invention
  • Fig. 5 is a cross-section through yet another embodiment
  • Fig. 6 is a schematic cross-section through a device bonded according to another aspect of the invention.
  • paste e.g. of thick or thin film is through, e.g. screen printing or photo image forming, with doping containing Na ions, provided with conductive and non conductive sections which are bondable through anodic bonding.
  • the carrier section may be one of glass, ceramics or glass composite, such as LTCC (Low Temperature Cofired Ceramic).
  • Fig. 1 is a cross section through a device 100, e.g. a sensor according to above mentioned sensor of EP 742 581.
  • the device comprises a cover or lid 110, e.g. of borosilicate glass or other glass composition, a semiconducting wafer 120, a substrate 130, preferably a multi layer substrate including conductors 140 and vias 150 arranged therein and solder pads 160.
  • the lid 110 is bonded to the Si wafer 120 through bonding areas 170a, provided in accordance with the teachings of the present invention.
  • the substrate 130 is also bonded to the Si wafer 120 through bonding areas 170b, provided in accordance with the teachings of the present invention.
  • the bonding areas 170 and 170b are provided as a paste on the lid 110 and carrier substrate 130, respectively, as closed frames through screen printing and/or photo image forming or the like.
  • the electronic circuitry or functional devices 180 arranged on the silicon (Si) wafer 120 are connected to the conductors 140, e.g. through connections 185 via the Si wafer. It is also possible to arrange connections that pass the bonding paste of the connection areas 170a and/or 170b, which will be exemplified in the following embodiments.
  • the electronic circuitry 180 is further connected to other circuits through solder pads 160.
  • both the lid 110 and the substrate 130 can be provided with cavities 190a and 190b, respectively.
  • Fig. 2a is a plane view of lid wafer 210 of glass on which a number of sealing frames 270 of a paste material containing Na-ions are printed, e.g. through screen printing.
  • the frames provide a closed space building the cavities 290.
  • functional devices 280 are realised on a Si wafer 220, which can be arranged on a carrying substrate 230 (fig. 3), which also is provided with bonding frames or sections 270b.
  • Fig. 3 illustrates the moment before the glass wafer 210 of fig. 2a is bonded onto the Si wafer 220 of fig. 2b. After the bonding process packaged units are formed, and each unit is cut out later in a suitable way well known for a skilled person.
  • the functional devices 280 may also be countersunk in the substrate 220 through micro-machining or the like depending on the application and/or the material of the substrate.
  • the bonding process is performed in a known way, i.e. the Si wafer 220 and the lid glass wafer 210 or carrier 230 are combined and exposed to a pressure and heat up to a specific level, for example 350 °C (not limited) and then a voltage, e.g. 800 V (not limited), is applied through the stack comprising the Si wafer and the lid wafer and/or the carrier.
  • a voltage e.g. 800 V (not limited
  • a substrate 420a is provided with conductors 440a, e.g. through etching or the like. Then the paste 470a (thin film paste) applied onto the glass 410 is pressed on the substrate 420a.
  • a thick-film paste 470b is applied through, e.g. screen printing onto the glass 410.
  • Conductors 440b having substantially the same thickness as the paste are arranged through a suitable method on the substrate 430b, e.g. alumina.
  • a so-called biological circuit 600 is connected to a substrate 610.
  • the biological circuit comprises a conduit 601 for transporting fluid or gas. It is possible to connect and seal the circuit to an external substrate 610 of, e.g. LTCC of another circuit likewise provided with a conduit 611 using the teachings of the invention, i.e. arranging a ring shaped paste bonding means 620 and anodically bonding the circuit to the substrate or other circuits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Joining Of Glass To Other Materials (AREA)
  • Micromachines (AREA)
  • Pressure Sensors (AREA)

Abstract

La présente invention concerne un procédé destiné à la liaison d'un premier élément (110, 210, 130, 230, 410, 430, 510, 530, 610) sur un second élément de silicium (120, 220, 420a, 420b, 600) par liaison anodique. Ce procédé consiste à déposer de façon sélective des section susceptibles d'être liées (170a, 170b, 270, 470a, 470b, 470c, 570, 620) sur ledit premier élément avant de mettre le premier et le second élément ensemble pour la liaison anodique.
EP00973305A 1999-10-19 2000-10-17 Procede concernant les liaisons anodiques Ceased EP1234330A2 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US16041199P 1999-10-19 1999-10-19
SE9903798 1999-10-19
US160411P 1999-10-19
SE9903798A SE522141C2 (sv) 1999-10-19 1999-10-19 Method relating to anodic bonding
PCT/SE2000/002012 WO2001029890A2 (fr) 1999-10-19 2000-10-17 Procede concernant les liaisons anodiques

Publications (1)

Publication Number Publication Date
EP1234330A2 true EP1234330A2 (fr) 2002-08-28

Family

ID=26663664

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00973305A Ceased EP1234330A2 (fr) 1999-10-19 2000-10-17 Procede concernant les liaisons anodiques

Country Status (4)

Country Link
EP (1) EP1234330A2 (fr)
JP (1) JP2003512723A (fr)
AU (1) AU1183101A (fr)
WO (1) WO2001029890A2 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6809424B2 (en) 2000-12-19 2004-10-26 Harris Corporation Method for making electronic devices including silicon and LTCC and devices produced thereby
WO2003097552A1 (fr) 2002-04-30 2003-11-27 Agency For Science Technology And Research Un procede de collage plaquette/substrat
US7259466B2 (en) 2002-12-17 2007-08-21 Finisar Corporation Low temperature bonding of multilayer substrates
US7361593B2 (en) 2002-12-17 2008-04-22 Finisar Corporation Methods of forming vias in multilayer substrates
GB2439403B (en) * 2003-10-24 2008-06-04 Miradia Inc Method and system for hermetically sealing packages for optics
GB2443352B (en) * 2003-10-24 2008-07-16 Miradia Inc Method and system for hermetically sealing packages for optics
GB2443573B (en) * 2003-10-24 2008-08-27 Miradia Inc Method and system for hermetically sealing packages for optics
US7303645B2 (en) 2003-10-24 2007-12-04 Miradia Inc. Method and system for hermetically sealing packages for optics
US7153759B2 (en) 2004-04-20 2006-12-26 Agency For Science Technology And Research Method of fabricating microelectromechanical system structures
US7344956B2 (en) 2004-12-08 2008-03-18 Miradia Inc. Method and device for wafer scale packaging of optical devices using a scribe and break process
US7473616B2 (en) * 2004-12-23 2009-01-06 Miradia, Inc. Method and system for wafer bonding of structured substrates for electro-mechanical devices
US7349140B2 (en) 2005-05-31 2008-03-25 Miradia Inc. Triple alignment substrate method and structure for packaging devices
JP2011049324A (ja) * 2009-08-26 2011-03-10 Seiko Instruments Inc 陽極接合方法、及び圧電振動子の製造方法
KR102552470B1 (ko) 2017-12-21 2023-07-05 쇼오트 글라스 테크놀로지스 (쑤저우) 코퍼레이션 리미티드. 접합 가능한 유리 및 자가형광성이 낮은 물품 및 이의 제조 방법

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JPS5544786A (en) * 1978-09-27 1980-03-29 Hitachi Ltd Pressure sensor
US4746893A (en) * 1985-01-31 1988-05-24 Motorola, Inc. Pressure transducer with sealed conductors
JPH0693972A (ja) * 1992-09-11 1994-04-05 Seiko Epson Corp マイクロポンプ及びその製造方法
JPH0786313A (ja) * 1993-09-09 1995-03-31 Asahi Kasei Denshi Kk 小型素子のボンディング法
JPH07283419A (ja) * 1994-04-06 1995-10-27 Nikon Corp 半導体センサ及びその製造方法
JP3406940B2 (ja) * 1994-07-14 2003-05-19 キヤノン株式会社 微小構造体およびその形成方法
US5591679A (en) * 1995-04-12 1997-01-07 Sensonor A/S Sealed cavity arrangement method
JPH0918017A (ja) * 1995-06-30 1997-01-17 Omron Corp 半導体加速度センサおよび半導体圧力センサ
JP3139339B2 (ja) * 1995-09-13 2001-02-26 株式会社村田製作所 真空封止デバイスおよびその製造方法
JPH10200128A (ja) * 1997-01-16 1998-07-31 Toyota Motor Corp 半導体センサの製造方法
JPH10256285A (ja) * 1997-03-06 1998-09-25 Toray Ind Inc 半導体パッケージ用封止枠体付基板の製造方法およびその装置
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See references of WO0129890A3 *

Also Published As

Publication number Publication date
WO2001029890A2 (fr) 2001-04-26
JP2003512723A (ja) 2003-04-02
WO2001029890A3 (fr) 2001-09-07
AU1183101A (en) 2001-04-30

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