EP1234329A1 - Verfahren zur herstellung eines bipolartransistors und verfahren zur herstellung einer integrierten schaltungsanordnung mit einem solchen bipolartransistor - Google Patents
Verfahren zur herstellung eines bipolartransistors und verfahren zur herstellung einer integrierten schaltungsanordnung mit einem solchen bipolartransistorInfo
- Publication number
- EP1234329A1 EP1234329A1 EP00985129A EP00985129A EP1234329A1 EP 1234329 A1 EP1234329 A1 EP 1234329A1 EP 00985129 A EP00985129 A EP 00985129A EP 00985129 A EP00985129 A EP 00985129A EP 1234329 A1 EP1234329 A1 EP 1234329A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- collector
- contact
- produced
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000005530 etching Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 29
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 27
- 238000011065 in-situ storage Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 258
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 52
- 229920005591 polysilicon Polymers 0.000 claims description 52
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- 239000002019 doping agent Substances 0.000 claims description 16
- 125000006850 spacer group Chemical group 0.000 claims description 15
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 230000001681 protective effect Effects 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 3
- 238000000407 epitaxy Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 description 20
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 238000000151 deposition Methods 0.000 description 10
- 239000013256 coordination polymer Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 238000002513 implantation Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/01—Manufacture or treatment
- H10D10/051—Manufacture or treatment of vertical BJTs
- H10D10/054—Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/01—Manufacture or treatment
- H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
Definitions
- the invention relates to a method for producing a bipolar transistor.
- a highly n-doped terminal region of a collector is produced on a p-doped silicon substrate. Over the termination region of the collector, the low n-doped collector made of silicon is applied.
- an insulating structure is created consisting of trenches filled with insulating material and highly p-doped channel stop regions arranged underneath. The insulating structure surrounds the bipolar transistor to be generated laterally within the substrate.
- a first Sic> 2 layer, above a polysilicon layer, above a second SiO 2 layer and above a layer of silicon nitride are produced.
- a first depression which extends to the first insulating layer
- a second depression which extends to the connection region of the collector
- silicon nitride is deposited and etched back so that side surfaces of the first recess and the second recess remain covered by the auxiliary layer and bottoms of the recesses are exposed.
- Si ⁇ _> 2 is etched isotropically, so that a part of the first SiO 2 ⁇
- a third SiC> 2 layer and a second polysilicon layer are deposited.
- the second polysilicon layer is etched back anisotropically selectively to the third SiO 2 layer, so that spacers are formed.
- Exposed parts of the third Sic ⁇ layer are selectively removed by isotropic etching to the spacers.
- a third polysilicon layer is deposited and etched back, so that in the first recess an emitter and in the second recess a contact to the collector are generated.
- a third depression is created, which extends to the first layer of polysilicon.
- conductive material is deposited and planarized, so that in the first recess a contact with the emitter, in the second well another contact with the collector and in the third well a contact to the base are generated.
- the invention has for its object to provide a method for producing a bipolar transistor, wherein the base resistance is less than the external emitter resistor is. Furthermore, a method for producing an integrated circuit arrangement with at least one such bipolar transistor is to be specified.
- the object is achieved by a method for producing a bipolar transistor in which a collector doped by a first conductivity type is produced in a substrate made of semiconductor material. On the substrate, a first insulating layer is formed covering the collector. On the first insulating layer, a layer of polysilicon doped with a second conductivity type opposite to the first conductivity type is produced. On the layer of polysilicon, a second insulating layer is produced. A first recess is formed which cuts through the second insulating layer and the layer of polysilicon and is disposed over the collector. After the formation of the first recess, a first auxiliary layer and above it a second auxiliary layer are produced which are so thin that they do not fill up the first recess.
- the second auxiliary layer is anisotropically etched until the first auxiliary layer is exposed.
- the first auxiliary layer is selectively isotropically etched to the second auxiliary layer until a portion of the first insulating layer is exposed.
- a portion of the first insulating layer is selectively removed by isotropic etching to the first auxiliary layer so that portions of the layer of polysilicon and portions of the collector are exposed.
- By selective epitaxial growth of second conductivity type in situ doped silicon the removed portion of the first insulating layer is replaced by a base. After creating the base, a third auxiliary layer is created. On the third auxiliary layer, spacers are produced in the first recess by deposition and re-etching of material.
- the third auxiliary layer is selectively isotropically etched to the pacers.
- the base is then exposed.
- Polysilicon doped with the first conductivity type and above this a separating layer are deposited and jointly structured in such a way that an emitter covered by the separating layer is produced, partially disposed in the first recess, adjacent to the base, and partially overlapping the second insulating layer.
- the second insulating layer is anisotropically etched selectively to the release layer until the layer of polysilicon is exposed.
- a silicide layer is produced on the layer of polysilicon but not on the release layer.
- a contact of the base is generated.
- the release layer is at least partially removed after the formation of the silicide layer, and contact of the emitter is made on the emitter.
- the base adjoins the layer of polysilicon. Between the layer of polysilicon and the contact with the base, the silicide layer is arranged. Consequently, the base resistance is smaller compared to a bipolar transistor without silicide layer.
- the layer of polysilicon is undercut by the isotropic etching of the first insulating layer.
- the undercut contributes to the overlap between the base and the collector. Since the undercut can be accurately controlled, the overlap can be small, so that a capacitance formed by the base and the collector can be very small.
- a horizontal cross section of the emitter is larger than a horizontal cross section of the first recess, so that the emitter partially overlaps the second insulating layer.
- a mask having a larger opening than the first recess is used. This is advantageous since a misalignment of the mask with respect to the first depression does not result in a horizontal surface of the emitter forming within the first depression. On such a horizontal surface, a silicide would form because it is not covered by the separation layer, so that the contact with the emitter would be adjacent to silicide, resulting in a lower external emitter resistance.
- the structuring of the second auxiliary layer by anisotropic etching is less critical, since the ions used in addition to the first insulating layer would also have to pass through the first auxiliary layer in order to reach the substrate. In the case of anisotropic etching of the second auxiliary layer, consequently fewer defects are produced than in structuring the first auxiliary layer by anisotropic etching.
- the analogous applies to the third auxiliary layer and to the spacers. In this case, the third auxiliary layer corresponds to the first auxiliary layer and the spacers to the second auxiliary layer.
- the Generating the base uses a mask that covers the first contact of the collector.
- a second contact hole which extends to the emitter and a third contact hole, which extends to the second contact of the collector, are generated.
- the contact of the base is generated.
- the contact of the emitter is generated.
- the third contact the third contact of the collector is generated.
- the substrate consists for example of silicon, germanium or SiGe.
- an insulating structure is produced in the substrate which laterally surrounds the part of the bipolar transistor to be generated, which is arranged in the substrate. If the bipolar transistor is part of an integrated circuit arrangement, then the insulating structure isolates the bipolar transistor from other semiconductor components of the integrated circuit arrangement arranged in the substrate.
- the insulating structure can be made of insulating trenches filled with insulating material or of an insulation which is produced by thermal oxidation, and of an insulation which is produced by thermal oxidation. lying and adjacent thereto diffusion area.
- the diffusion region is doped by a second conductivity type opposite to the first conductivity type.
- parts of the bipolar transistor and parts of the further bipolar transistor are preferably generated simultaneously in order to reduce the process outlay.
- a further part of the first insulating layer in the region of the further bipolar transistor is removed.
- the removed further part of the first insulating layer is replaced by at least part of an emitter of the further bipolar transistor.
- the bipolar transistor is an npn bipolar transistor and the further bipolar transistor is a pnp bipolar transistor.
- the bipolar transistor is a pnp bipolar transistor and the further bipolar transistor is an npn bipolar transistor.
- the base has a lower dopant concentration than the layer of polysilicon.
- FIG. 1 shows a cross section through a first substrate after a terminal region of a collector, a collector, a first contact of the collector, an insulation, a further insulation, a diffusion region, a first insulating layer, a layer of polysilicon, a second insulating layer, a Protective layer, a layer of amorphous silicon and a first mask of photoresist were generated.
- FIG. 2 shows the cross section from FIG. 1 after a first recess and a first part of a second recess have been produced.
- FIG. 4 shows the cross section from FIG. 3 after a first auxiliary layer, a second auxiliary layer and a protective mask have been produced.
- FIG. 6 shows the cross section from FIG. 5 after the first auxiliary layer and the protective layer have been removed and a third insulating layer, a third auxiliary layer and spacers have been produced.
- FIG. 7 shows the cross section from FIG. 6 after the spacers and the third auxiliary layer have been removed and an emitter, a second contact of the collector and a separating layer have been produced.
- FIG. 8 shows the cross-section from FIG. 7 after a silicide layer has been produced.
- FIG. 9 shows the cross section from FIG. 8, after an intermediate oxide, a contact of the base, a contact of the
- FIG. 10 shows a cross-section through a second substrate after terminal regions of collectors, collectors, a first contact to one of the collectors, a base, a well, a connection region to the well, an insulation, a further insulation, diffusion regions, a first insulating layer, a first mask, a second part of a second recess and further depressions were generated.
- FIG. 12 shows the cross section from FIG. 11 after a first recess and a first part of the second recess have been produced.
- An approximately 1500 nm thick n-doped terminal region A of a collector C adjoins a surface of the first substrate 1.
- the dopant concentration of the terminal region A of the collector C is about 10 20 cm -3 .
- the dopant concentration of the collector C is about 10 17 c ⁇ T 3 .
- the diffusion region D is generated by implantation.
- the diffusion region D is p-doped and has a dopant concentration of about 10 ⁇ 7 cm -3 .
- a first contact Kl of the collector C is produced on the terminal region A of the collector C (see FIG. 1).
- the first contact Kl of the collector C has a dopant concentration of about 10 ⁇ 0 cm -3 au f un ⁇ ⁇ s ⁇ between see the further insulation I 'and a part of the insulation I arranged.
- a first insulating layer II is produced (see FIG. 1).
- polysilicon P By depositing in situ p-doped polysilicon, an approximately 200 nm thick layer of polysilicon P is produced.
- the dopant concentration of the layer of polysilicon P is about 10 21 cm -3 .
- a second insulating layer 12 is produced.
- a protective layer SS is generated.
- a layer of amorphous silicon and silicon nitride ARC is produced (see FIG. 1).
- photoresist is applied in a thickness of approximately 800 nm, exposed and patterned.
- the layer of amorphous silicon and silicon nitride ARC prevents the formation of stray light during exposure.
- etching is first carried out as far as the layer of polysilicon P which acts as an etch stop.
- the first mask PI is removed.
- polysilicon is etched selectively to SiO 2 and silicon nitride anisotropically, so that the layer of polysilicon P is severed and the first insulating layer II acts as an etch stop.
- the layer of amorphous silicon and silicon nitride ARC is removed.
- the first recess VI is disposed above the collector C.
- the first part of the second depression V2 is arranged next to the first depression VI and above the first contact Kl of the collector C.
- the first recess VI has a square horizontal cross section with a side length of about 400 nm.
- the second recess V2 has a rectangular horizontal cross section whose side lengths are approximately 1300 nm and 400 nm.
- the first recess VI and the second recess V2 have a distance of approximately 1.4 ⁇ m from each other.
- a second part of the second depression V2 is created, which extends as far as the first contact K1 of the collector C (see FIG. 3).
- the second part of the second depression V2 is arranged between the further insulation I 1 and the insulation I.
- the second photoresist mask P2 is removed. Subsequently, by deposition of silicon nitride in a thickness of about 30 nm, a first auxiliary layer Hl is produced (see FIG. 4). In addition, SiO 2 is deposited in a thickness of approximately 80 nm to produce a second auxiliary layer H 2.
- the second auxiliary layer H2 is anisotropically etched until the first auxiliary layer Hl is exposed.
- the protective mask P3 covers the second depression V2 (see FIG. 4).
- Parts of the first auxiliary layer H1 are removed by isotropic etching with, for example, phosphoric acid selectively to the second auxiliary layer H2.
- the protective layer SS and the first insulating layer II are partially exposed (see FIG. 5).
- Insulation I is arranged removed, so that the layer of polysilicon P is undercut and partially exposed.
- the first auxiliary layer Hl and the protective layer SS protect the second insulating layer 12 and parts of the first insulating layer II, which are arranged in the region of the second recess V2. In isotropic etching, the second auxiliary layer H2 is also removed.
- the removed part of the first insulating layer II is replaced by a p-doped base B (see FIG. 5).
- the base B consists essentially of monocrystalline silicon and only in the vicinity L o o MN) P> P 1 ⁇ o C ⁇ o ⁇ o C ⁇
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19958062 | 1999-12-02 | ||
| DE19958062A DE19958062C2 (de) | 1999-12-02 | 1999-12-02 | Verfahren zur Herstellung eines Bipolartransistors und Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit einem solchen Bipolartransistor |
| PCT/EP2000/012112 WO2001041205A1 (de) | 1999-12-02 | 2000-12-01 | Verfahren zur herstellung eines bipolartransistors und verfahren zur herstellung einer integrierten schaltungsanordnung mit einem solchen bipolartransistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1234329A1 true EP1234329A1 (de) | 2002-08-28 |
Family
ID=7931152
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP00985129A Withdrawn EP1234329A1 (de) | 1999-12-02 | 2000-12-01 | Verfahren zur herstellung eines bipolartransistors und verfahren zur herstellung einer integrierten schaltungsanordnung mit einem solchen bipolartransistor |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6635545B2 (de) |
| EP (1) | EP1234329A1 (de) |
| JP (1) | JP2003515953A (de) |
| DE (1) | DE19958062C2 (de) |
| WO (1) | WO2001041205A1 (de) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10142690A1 (de) * | 2001-08-31 | 2003-03-27 | Infineon Technologies Ag | Kontaktierung des Emitterkontakts einer Halbleitervorrichtung |
| US6683366B1 (en) * | 2002-06-04 | 2004-01-27 | Newport Fab, Llc | Bipolar transistor and related structure |
| WO2004090988A1 (de) | 2003-04-10 | 2004-10-21 | Infineon Technologies Ag | Verfahren zur herstellung eines bipolaren halbleiterbauelements, insbesondere eines bipolartransistors, und entsprechendes bipolares halbleiterbauelement |
| DE10318422B4 (de) | 2003-04-23 | 2006-08-10 | Infineon Technologies Ag | Hochfrequenz-Bipolartransistor mit Silizidregion und Verfahren zur Herstellung desselben |
| DE10327709A1 (de) | 2003-06-21 | 2005-01-13 | Infineon Technologies Ag | Integrierte Schaltungsanordnung mit npn- und pnp-Bipolartransistoren sowie Herstellungsverfahren |
| DE10328008B4 (de) * | 2003-06-21 | 2008-04-03 | Infineon Technologies Ag | Integrierte Schaltungsanordnung mit pnp- und npn-Bipolartransistoren sowie Herstellungsverfahren |
| US6979884B2 (en) * | 2003-12-04 | 2005-12-27 | International Business Machines Corporation | Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border |
| DE10358047A1 (de) * | 2003-12-05 | 2005-06-30 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Komplementäre Bipolar-Halbleitervorrichtung |
| DE102004053394B4 (de) * | 2004-11-05 | 2010-08-19 | Atmel Automotive Gmbh | Halbleiteranordnung und Verfahren zur Herstellung einer Halbleiteranordnung |
| DE102004053393B4 (de) * | 2004-11-05 | 2007-01-11 | Atmel Germany Gmbh | Verfahren zur Herstellung einer vertikal integrierten Kaskodenstruktur und vertikal integrierte Kaskodenstruktur |
| US7442616B2 (en) * | 2006-06-15 | 2008-10-28 | Freescale Semiconductor, Inc. | Method of manufacturing a bipolar transistor and bipolar transistor thereof |
| US7638386B2 (en) * | 2006-06-15 | 2009-12-29 | Freescale Semiconductor, Inc. | Integrated CMOS and bipolar devices method and structure |
| US7611955B2 (en) * | 2006-06-15 | 2009-11-03 | Freescale Semiconductor, Inc. | Method of forming a bipolar transistor and semiconductor component thereof |
| US8026146B2 (en) * | 2006-08-31 | 2011-09-27 | Nxp B.V. | Method of manufacturing a bipolar transistor |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3127455B2 (ja) * | 1990-08-31 | 2001-01-22 | ソニー株式会社 | 半導体装置の製法 |
| JPH04373133A (ja) * | 1991-06-24 | 1992-12-25 | Hitachi Ltd | 半導体装置 |
| EP0809279B1 (de) * | 1991-09-23 | 2003-02-19 | Infineon Technologies AG | Verfahren zur Herstellung eines MOS-Transistors |
| US5321301A (en) * | 1992-04-08 | 1994-06-14 | Nec Corporation | Semiconductor device |
| JP2630237B2 (ja) * | 1993-12-22 | 1997-07-16 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| JP3646387B2 (ja) * | 1996-01-19 | 2005-05-11 | ソニー株式会社 | バイポーラトランジスタ |
| DE19609933A1 (de) * | 1996-03-14 | 1997-09-18 | Daimler Benz Ag | Verfahren zur Herstellung eines Heterobipolartransistors |
| US5773350A (en) * | 1997-01-28 | 1998-06-30 | National Semiconductor Corporation | Method for forming a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base |
| KR100245813B1 (ko) * | 1997-05-28 | 2000-03-02 | 윤종용 | 자기정합형 더블 폴리실리콘 바이폴라 트랜지스터및 그의 제조방법 |
-
1999
- 1999-12-02 DE DE19958062A patent/DE19958062C2/de not_active Expired - Fee Related
-
2000
- 2000-12-01 EP EP00985129A patent/EP1234329A1/de not_active Withdrawn
- 2000-12-01 WO PCT/EP2000/012112 patent/WO2001041205A1/de not_active Ceased
- 2000-12-01 JP JP2001542379A patent/JP2003515953A/ja not_active Ceased
-
2002
- 2002-06-03 US US10/160,630 patent/US6635545B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| See references of WO0141205A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003515953A (ja) | 2003-05-07 |
| US6635545B2 (en) | 2003-10-21 |
| DE19958062C2 (de) | 2002-06-06 |
| US20020168829A1 (en) | 2002-11-14 |
| WO2001041205A1 (de) | 2001-06-07 |
| DE19958062A1 (de) | 2001-07-05 |
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Legal Events
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| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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| 17P | Request for examination filed |
Effective date: 20020507 |
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