EP1178322A3 - Integrierter Schaltkreis mit Selbsttest-Schaltung - Google Patents
Integrierter Schaltkreis mit Selbsttest-Schaltung Download PDFInfo
- Publication number
- EP1178322A3 EP1178322A3 EP01000340A EP01000340A EP1178322A3 EP 1178322 A3 EP1178322 A3 EP 1178322A3 EP 01000340 A EP01000340 A EP 01000340A EP 01000340 A EP01000340 A EP 01000340A EP 1178322 A3 EP1178322 A3 EP 1178322A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- circuit
- test
- application circuit
- self
- application
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31813—Test pattern generators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31816—Soft error testing; Soft error rate evaluation; Single event testing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10038327A DE10038327A1 (de) | 2000-08-05 | 2000-08-05 | Integrierter Schaltkreis mit Selbsttest-Schaltung |
DE10038327 | 2000-08-05 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP1178322A2 EP1178322A2 (de) | 2002-02-06 |
EP1178322A3 true EP1178322A3 (de) | 2003-09-24 |
EP1178322B1 EP1178322B1 (de) | 2005-11-02 |
Family
ID=7651480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01000340A Expired - Lifetime EP1178322B1 (de) | 2000-08-05 | 2001-08-02 | Integrierter Schaltkreis mit Selbsttest-Schaltung |
Country Status (4)
Country | Link |
---|---|
US (1) | US6789221B2 (de) |
EP (1) | EP1178322B1 (de) |
JP (1) | JP2002122639A (de) |
DE (2) | DE10038327A1 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10201554A1 (de) * | 2002-01-17 | 2003-08-21 | Philips Intellectual Property | Integrierter Schaltkreis mit Selbsttest-Schaltung |
DE10209078A1 (de) * | 2002-03-01 | 2003-09-18 | Philips Intellectual Property | Integrierter Schaltkreis mit Testschaltung |
US7234092B2 (en) | 2002-06-11 | 2007-06-19 | On-Chip Technologies, Inc. | Variable clocked scan test circuitry and method |
US7058869B2 (en) * | 2003-01-28 | 2006-06-06 | Syntest Technologies, Inc. | Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits |
KR20060095969A (ko) * | 2003-09-19 | 2006-09-05 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 비밀 서브 모듈 조립체를 포함하는 전자 회로 |
US7093174B2 (en) * | 2004-02-17 | 2006-08-15 | Mentor Graphics Corporation | Tester channel count reduction using observe logic and pattern generator |
CN101014869A (zh) | 2004-06-30 | 2007-08-08 | 皇家飞利浦电子股份有限公司 | 电路装置及在所述电路装置中设置的应用电路的测试方法 |
TWI363756B (en) * | 2004-12-07 | 2012-05-11 | Du Pont | Method for preparing n-phenylpyrazole-1-carboxamides |
US7610527B2 (en) * | 2005-03-16 | 2009-10-27 | Nec Laboratories America, Inc. | Test output compaction with improved blocking of unknown values |
ATE485525T1 (de) * | 2007-04-05 | 2010-11-15 | Nxp Bv | Prüfbare integrierte schaltung und verfahren zur generierung von testdaten |
US7818643B2 (en) * | 2008-02-20 | 2010-10-19 | Nec Laboratories America, Inc. | Method for blocking unknown values in output response of scan test patterns for testing circuits |
TWI401456B (zh) * | 2008-10-30 | 2013-07-11 | Atomic Energy Council | 燃料電池自動化測試程序之監控裝置 |
WO2010060012A1 (en) | 2008-11-23 | 2010-05-27 | Mentor Graphics Corporation | On-chip logic to support in-field or post-tape-out x-masking in bist designs |
US8103925B2 (en) * | 2008-11-24 | 2012-01-24 | Mentor Graphics Corporation | On-chip logic to support compressed X-masking for BIST |
US8112686B2 (en) * | 2008-12-01 | 2012-02-07 | Mentor Graphics Corporation | Deterministic logic built-in self-test stimuli generation |
DE102016119750B4 (de) * | 2015-10-26 | 2022-01-13 | Infineon Technologies Ag | Vorrichtungen und Verfahren zur Mehrkanalabtastung |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0780767A2 (de) * | 1995-12-22 | 1997-06-25 | AT&T Corp. | Verfahren und Einrichtung zum pseudozufälligen Prüfen mittels boundary-scan |
US5784383A (en) * | 1997-10-02 | 1998-07-21 | International Business Machines Corporation | Apparatus for identifying SMP bus transfer errors |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4503537A (en) * | 1982-11-08 | 1985-03-05 | International Business Machines Corporation | Parallel path self-testing system |
US5043986A (en) * | 1989-05-18 | 1991-08-27 | At&T Bell Laboratories | Method and integrated circuit adapted for partial scan testability |
US5349587A (en) | 1992-03-26 | 1994-09-20 | Northern Telecom Limited | Multiple clock rate test apparatus for testing digital systems |
EP0642083A1 (de) * | 1993-09-04 | 1995-03-08 | International Business Machines Corporation | Prüfschaltkreis und Verfahren zum Prüfen von Chipverbindungen |
US6374370B1 (en) * | 1998-10-30 | 2002-04-16 | Hewlett-Packard Company | Method and system for flexible control of BIST registers based upon on-chip events |
US6625688B1 (en) * | 1999-05-10 | 2003-09-23 | Delphi Technologies, Inc. | Method and circuit for analysis of the operation of a microcontroller using signature analysis of memory |
US6442722B1 (en) * | 1999-10-29 | 2002-08-27 | Logicvision, Inc. | Method and apparatus for testing circuits with multiple clocks |
-
2000
- 2000-08-05 DE DE10038327A patent/DE10038327A1/de not_active Withdrawn
-
2001
- 2001-08-02 DE DE50107889T patent/DE50107889D1/de not_active Expired - Lifetime
- 2001-08-02 JP JP2001235328A patent/JP2002122639A/ja not_active Withdrawn
- 2001-08-02 EP EP01000340A patent/EP1178322B1/de not_active Expired - Lifetime
- 2001-08-03 US US09/922,140 patent/US6789221B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0780767A2 (de) * | 1995-12-22 | 1997-06-25 | AT&T Corp. | Verfahren und Einrichtung zum pseudozufälligen Prüfen mittels boundary-scan |
US5784383A (en) * | 1997-10-02 | 1998-07-21 | International Business Machines Corporation | Apparatus for identifying SMP bus transfer errors |
Non-Patent Citations (1)
Title |
---|
KIEFER G ET AL: "USING BIST CONTROL FOR PATTERN GENERATION", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE. ITC '97. WASHINGTON, DC, NOV. 1 - 6, 1997, INTERNATIONAL TEST CONFERENCE, NEW YORK, NY: IEEE, US, vol. CONF. 28, 1 November 1997 (1997-11-01), pages 347 - 355, XP000800332, ISBN: 0-7803-4210-0 * |
Also Published As
Publication number | Publication date |
---|---|
DE10038327A1 (de) | 2002-02-14 |
US20020069387A1 (en) | 2002-06-06 |
EP1178322B1 (de) | 2005-11-02 |
US6789221B2 (en) | 2004-09-07 |
DE50107889D1 (de) | 2005-12-08 |
JP2002122639A (ja) | 2002-04-26 |
EP1178322A2 (de) | 2002-02-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1178322A3 (de) | Integrierter Schaltkreis mit Selbsttest-Schaltung | |
DE4110151C2 (de) | Integrierte Schaltungsvorrichtung | |
ATE327587T1 (de) | Verfahren und vorrichtung zur diagnose von ausfällen in einer integrierten schaltung unter verwendung von techniken des typs design-for- debug (dfd) | |
US9766289B2 (en) | LBIST debug controller | |
DE60225898D1 (de) | Mehrfacherfassungs-dft-system zum detektieren oder auffinden von überschreitenden taktbereichsfehlern während der selbstprüfung oder scan-prüfung | |
Hiraide et al. | BIST-aided scan test-A new method for test cost reduction | |
EP1224482B1 (de) | Verfahren und vorrichtung zum datenschützenden selbsttest für mikrokontroller | |
DE102005026403B4 (de) | Verfahren zum Liefern von Abtastmustern zu einer elektronischen Vorrichtung | |
ATE485525T1 (de) | Prüfbare integrierte schaltung und verfahren zur generierung von testdaten | |
Huang et al. | Compressed pattern diagnosis for scan chain failures | |
DE102015110144B4 (de) | Chip und Verfahren zum Testen einer Verarbeitungskomponente eines Chips | |
US20190041459A1 (en) | Re-programmable self-test | |
ATE420373T1 (de) | Schaltungsanordnung und verfahren zum prüfen einer in der schaltungsanordnung bereitgestellten anwendungsschaltung | |
US8423845B2 (en) | On-chip logic to log failures during production testing and enable debugging for failure diagnosis | |
DE102005026402A1 (de) | Verfahren und Vorrichtungen zum Programmieren und Betreiben einer automatischen Testausrüstung | |
DE10335164A1 (de) | Vorrichtung und Verfahren zum Testen von integrierten Schaltungskreisen | |
EP1179738A3 (de) | Anordnung zum Testen eines integrierten Schaltkreises | |
EP1179737A3 (de) | Anordnung zum Testen eines integrierten Schaltkreises | |
DE10322726A1 (de) | Verfahren und Vorrichtung zum Verbessern einer Testfähigkeit von I/O-Treiber/Empfängern | |
Mir et al. | Built-in self-test approaches for analogue and mixed-signal integrated circuits | |
EP1239293A3 (de) | Anordnung und Verfahren zum Testen von integrierten Schaltkreisen | |
Yogi et al. | Spectral rtl test generation for microprocessors | |
WO2003060534A3 (en) | Integrated circuit with self-testing circuit | |
EP1186900A3 (de) | Anordnung zum Testen von integrierten Schaltkreisen | |
CN108572311A (zh) | 半导体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: PHILIPS CORPORATE INTELLECTUAL PROPERTY GMBH Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V. |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V. Owner name: PHILIPS INTELLECTUAL PROPERTY & STANDARDS GMBH |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
AX | Request for extension of the european patent |
Extension state: AL LT LV MK RO SI |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: 7G 01R 31/3185 B Ipc: 7G 01R 31/3187 A |
|
17P | Request for examination filed |
Effective date: 20040324 |
|
AKX | Designation fees paid |
Designated state(s): DE FR GB |
|
17Q | First examination report despatched |
Effective date: 20040901 |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REF | Corresponds to: |
Ref document number: 50107889 Country of ref document: DE Date of ref document: 20051208 Kind code of ref document: P |
|
GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20060125 |
|
ET | Fr: translation filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20060803 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: TP |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: GC |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20090618 AND 20090624 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: GC |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20090730 Year of fee payment: 9 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20101007 AND 20101013 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20100824 Year of fee payment: 10 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 50107889 Country of ref document: DE Effective date: 20110301 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20110301 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: GC |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20111013 AND 20111019 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20110728 Year of fee payment: 11 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: AU Effective date: 20120126 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST Effective date: 20120430 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20110831 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20120802 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20120802 |