EP1171907A1 - Procede de rechauffement au plasma de plaquettes semi-conductrices - Google Patents

Procede de rechauffement au plasma de plaquettes semi-conductrices

Info

Publication number
EP1171907A1
EP1171907A1 EP01903051A EP01903051A EP1171907A1 EP 1171907 A1 EP1171907 A1 EP 1171907A1 EP 01903051 A EP01903051 A EP 01903051A EP 01903051 A EP01903051 A EP 01903051A EP 1171907 A1 EP1171907 A1 EP 1171907A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor wafer
present
plasma
temperature
recited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01903051A
Other languages
German (de)
English (en)
Inventor
Calvin Todd Gabriel
Edward K. Yeh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Philips Semiconductors Inc
Original Assignee
Koninklijke Philips Electronics NV
Philips Semiconductors Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV, Philips Semiconductors Inc filed Critical Koninklijke Philips Electronics NV
Publication of EP1171907A1 publication Critical patent/EP1171907A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0209—Pretreatment of the material to be coated by heating

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing. More specifically, the present disclosure relates to semiconductor wafer temperature, and to the use of inert gas plasma for stabilizing wafer temperature prior to plasma processing. In particular, a method for performing plasma warm-up on semiconductor wafers is disclosed.
  • Wafer temperature is one of the most important variables for a plasma etch or deposition process. It can affect the rate at which the process progress and can also affect other parameters such as etch selectivity, profile control, and film quality. But the plasma itself heats the wafer surface above the setpoint of the temperature-controlled chuck on which the wafer sits. Even a state-of-the-art electrostatic chuck with He backside cooling cannot prevent this heating. Thus, any wafer that is conventionally plasma processed experiences temperatures ranging from the initial chuck temperature to the final equilibrium temperature.
  • shallow sihcon trench etch is typically performed by assuming a constant etch rate and then etching for a set amount of time to reach a
  • shallow silicon trench etch is typically performed by assuming a constant etch rate and then etching for a set amount of time to reach a desired depth.
  • the assumption of a fixed etch rate is not correct since the wafer temperature itself is not fixed throughout the etch. As the wafer is initially heated by the plasma, the etch rate can vary, resulting in an off-target trench depth.
  • etching of materials such as Cu or Pt
  • the etch products have low volatility.
  • the wafer temperature to be relatively high. If etching begins at a lower than desired temperature, for a period of time there can be blocked etch and surface roughening that might affect the final result even after the wafer temperature stabilizes.
  • Temperature control during plasma-assisted film deposition is also important. Film deposited during the initial stages of the deposition, when the wafer is cooler than its equilibrium temperature, will not have the same properties as the remainder of the film.
  • the present invention provides a method to reduce wafer temperature variability during semiconductor process steps.
  • the present invention further provides a method which reduces the difficulty in controlling process conditions due to initial heating of the semiconductor wafer.
  • the present invention introduces a semiconductor wafer into an processing environment. Prior to subjecting the semiconductor wafer to a conventional semiconductor process, the present invention performs a plasma warm-up step.
  • the aforementioned plasma warm-up step of the present invention is comprised of the following steps. First, the present invention subjects the semiconductor wafer to an inert gas plasma within the processing environment. Next, the present invention continues to subject the semiconductor wafer to the inert gas plasma until the semiconductor wafer achieves a desired temperature.
  • the present invention includes the steps of the above-described embodiment, and further recites that the inert gas is selected from the group consisting of He, Ne, Ar, Kr, and Xe.
  • the present invention includes the steps of the first of the above-described embodiments, and further recites that the semiconductor wafer is subjected to the inert gas plasma until the semiconductor wafer approaches the maximum temperature to which the semiconductor wafer would be heated during a subsequent conventional semiconductor process step.
  • FIGURE 1 is a flow chart of steps performed in accordance with one embodiment of the present claimed invention.
  • FIGURE 2 is a schematic illustration of semiconductor wafer in an processing environment adapted to perform a plasma warm-up step in accordance with one embodiment of the present claimed invention.
  • FIGURE 3 is a graph of semiconductor wafer temperature vs. time (includ ng deviation from stable temperature) during a plasma warm-up step in accordance with one embodiment of the present claimed invention.
  • semiconductor wafer temperature is one of the hidden parameters in plasma processing that significantly impacts process results and can cause variation between presumably identical process tools. Understanding and controlling the actual wafer temperature, as opposed to simply controlling the temperature setpoint of the wafer chuck, is critical for preventing resist burning; controlling vertical and lateral etch rates of temperature-sensitive films, such as AlCu or organic polymers; and minimizing the effect of charging damage on gate oxide.
  • the present invention reduces the variability associated with uncontrolled semiconductor wafer heating.
  • the present embodiment provides a method for stabilizing the temperature of a semiconductor wafer.
  • a stabilization can be used, for example, to reduce variability in an etching process, or to selectively pre-heat a semiconductor wafer to a desired temperature.
  • semiconductor wafer will refer to a semiconductor substrate alone, and also to a semiconductor substrate having additional materials disposed thereon. Such materials include, but are not limited to, oxides, dielectrics, passivation materials, metals, and the like.
  • step 102 of Figure 1 introduces a semiconductor wafer 202 into an processing environment 200, both of Figure 2. It will be understood that numerous well-known features of an processing environment are not shown in Figure 2 for purposes of clarity.
  • the present embodiment prior to subjecting semiconductor wafer 202 to a conventional semiconductor process (e.g. an etching process), the present embodiment performs a plasma warm-up step. More specifically, in the present embodiment, the plasma warm-up step comprises subjecting semiconductor wafer 202 to an inert gas plasma 204 generated within processing environment 200.
  • the inert gas used to create the inert gas plasma is selected from the group consisting of He, Ne, Ar, Kr, and Xe.
  • inert gas plasma is intended to refer to a plasma which does not deleteriously affect, to a significant extent, semiconductor wafer 200 (or various materials disposed thereon) during the plasma warm-up step. That is, the present invention is not limited to use solely with the "inert” elements (i.e. the noble elements) of the periodic table.
  • the present embodiment continues to subject semiconductor wafer 202 to inert gas plasma 202 until a desired condition is met.
  • the plasma warm-up step is continued until semiconductor wafer 202 approaches the maximum temperature to which semiconductor wafer 202 would be heated during a subsequent conventional semiconductor process. For example, when semiconductor wafer 202 is subsequently going to be subjected to an etching process which will heat semiconductor wafer to a temperature of 70 degrees Celsius, the present embodiment continues the aforementioned plasma warm-up step until semiconductor wafer 202 reaches 70 degrees Celsius.
  • the plasma warm-up step is continued for a duration of approximately 10-30 seconds. Still referring to step 104, the plasma warm-up step of the present invention is performed under flow rates and parameters which tire easily obtained in a standard processing environment.
  • the aforementioned plasma warm-up step is performed in an processing environment wherein the inert gas introduced at a flow rate of approximately 50-5000 standard cubic centimeters per minute (SCCM); wherein the processing environment is at a pressure in the range of 50 mTorr to 5 Torr; wherein the processing environment is at a power in the range of 100 Watts to 3000 Watts; wherein the plasma warm-up step is performed for a duration in the range of 5 seconds to 150 seconds; and wherein the low electrode setpoint is at a temperature in the range of -60 degrees Celsius to 600 degrees Celsius.
  • SCCM standard cubic centimeters per minute
  • FIG. 3 a graph 300 of semiconductor wafer temperature vs. time (including deviation from stable temperature) during the plasma warm-up step 104 of Figure 1 is shown.
  • the temperature of semiconductor wafer 202 of the present embodiment is almost completely stabilized after approximately 20 seconds.
  • the present invention accurately controls one of the hidden parameters in plasma processing that significantly impacts process results and causes variation between presumably identical process tools.
  • the present invention minimizes variation, allows for a wider process window for other parameters, and improves process control.
  • the present invention provides a method to reduce wafer temperature variability during semiconductor process steps.
  • the present invention further provides a method which reduces the difficulty in controlling process conditions due to initial heating of the semiconductor wafer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

L'invention se rapporte à un procédé permettant de stabiliser la température d'une plaquette semi-conductrice. Dans une réalisation, la présente invention consiste à introduire une plaquette semi-conductrice dans un environnement de traitement. Avant de soumettre ladite plaquette semi-conductrice à un procédé classique pour semi-conducteur, le procédé de la présente invention consiste en une étape de réchauffement au plasma. Cette étape de réchauffement au plasma consiste elle-même, tout d'abord, en ce que la plaquette semi-conductrice est soumise à un plasma gazeux inerte au sein de l'environnement de traitement, puis en ce que ladite plaquette semi-conductrice continue à être soumise à ce plasma gazeux inerte jusqu'à ce qu'elle ait atteint une température souhaitée.
EP01903051A 2000-01-13 2001-01-11 Procede de rechauffement au plasma de plaquettes semi-conductrices Withdrawn EP1171907A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US483512 1990-02-22
US48351200A 2000-01-13 2000-01-13
PCT/US2001/001058 WO2001052310A1 (fr) 2000-01-13 2001-01-11 Procede de rechauffement au plasma de plaquettes semi-conductrices

Publications (1)

Publication Number Publication Date
EP1171907A1 true EP1171907A1 (fr) 2002-01-16

Family

ID=23920355

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01903051A Withdrawn EP1171907A1 (fr) 2000-01-13 2001-01-11 Procede de rechauffement au plasma de plaquettes semi-conductrices

Country Status (4)

Country Link
EP (1) EP1171907A1 (fr)
JP (1) JP2003520431A (fr)
KR (1) KR20020019001A (fr)
WO (1) WO2001052310A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4490704B2 (ja) * 2004-02-27 2010-06-30 株式会社日立ハイテクノロジーズ プラズマ処理方法
JP5411105B2 (ja) * 2004-06-23 2014-02-12 株式会社日立ハイテクノロジーズ ドライエッチング装置
JP4490938B2 (ja) * 2006-04-20 2010-06-30 株式会社日立ハイテクノロジーズ プラズマ処理装置
JP2009194194A (ja) * 2008-02-15 2009-08-27 Sumitomo Precision Prod Co Ltd プラズマ処理方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH088232A (ja) * 1994-06-22 1996-01-12 Sony Corp プラズマ処理方法
US6030666A (en) * 1997-03-31 2000-02-29 Lam Research Corporation Method for microwave plasma substrate heating
JP3524763B2 (ja) * 1998-05-12 2004-05-10 株式会社日立製作所 エッチング方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0152310A1 *

Also Published As

Publication number Publication date
KR20020019001A (ko) 2002-03-09
JP2003520431A (ja) 2003-07-02
WO2001052310A1 (fr) 2001-07-19

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