Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
  • G01R31/318558—Addressing or selecting of subparts of the device under test

Definitions

• the present invention relates to the field of electrical integrated circuit testing. More particularly, the present invention relates to a scan test observation system and method to enhance test observability in integrated circuits utilizing scan test methodologies.
• Electronic systems and circuits have made a significant contribution towards the advancement of modem society and are utilized in a number of applications to achieve advantageous results.
• Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment.
• electronic systems designed to provide these results comprise a variety of components or devices including microelectronic integrated circuits.
• components or devices of an electronic system are required to operate properly in order for the desired results to be realized.
• An efficient and reliable integrated circuit (IC) testing system and method is very important for assuring an IC operates properly.
• SOC system-on-chip
• BIST built in self test
• Modern BIST techniques typically include the insertion of a scan test architecture in an IC to provide controllability and observability of IC components.
• scan test architectures include scan test components or devices (e.g., scan test cells) that interact with functional logic utilized to perform non-test or normal operations of the IC.
• Scan testing of complex electronic systems and circuits often requires analysis of measurements from test points (e.g., appropriately selected circuit nodes at the outputs or inputs of functional logic) after the application of test vectors to stimulate certain aspects of a circuit (e.g., a functional logic component).
• test points e.g., appropriately selected circuit nodes at the outputs or inputs of functional logic
• test vectors to stimulate certain aspects of a circuit (e.g., a functional logic component).
• microelectronic IC chips typically have numerous signal transmission path connections to external devices and connections between internal functional logic components. These signal transmission path connections are often appropriate circuit nodes for testing activities such as
• Boundary scan testing is a very common method of scan testing included in typical BIST schemes.
• International Electrical and Electronic Engineering (IEEE) Standard 1149.1 also referred to as Joint Task Action Group (JTAG) boundary scan compliant architecture is one of the most prevalent boundary scan schemes.
• the IEEE 1149.1 boundary scan architecture is primarily utilized to detect and isolate interconnect faults between components.
• a typical JTAG IEEE 1149.1 boundary scan compliant chip includes a boundary scan test cell or register at input/output (I/O) pins of a chip.
• I/O input/output
• a JTAG scan test operation includes placing a known value or test vector on an output buffer of one device and observing the input buffer of another interconnected device to determine if the are electrically connected.
• boundary scan testing is somewhat limited in its ability to provide control and observability of internal connections and devices or components of an IC.
• full scan testing As a general proposition, it is desirable to have significant internal scan test coverage of numerous scan test points. Usually the greater the test coverage the greater the capacity of a scan test system and method to detect faults. Having both internal and boundary scan capability is often referred to as full scan testing. At this time there is no dominant standard with respect to full scan testing architectures. However, most full scan testing techniques rely on scan test cells included in the IC. Typically, the scan test cells are designed to scan or shift scan test information (e.g., test vectors) to appropriate locations in a circuit and capture scan test information from scan test points.
• scan test information e.g., test vectors
• a particular logical value is shifted via scan test cells to the input of a functional component
• the functional component performs a normal operation based upon the shifted scan test information
• a scan test cell captures the output of the functional component and the captured information is shifted off the chip via scan test cells.
• the scan test cells are incorporated in the IC during the design.
• typical automated design processes do not adequately accommodate and incorporate sufficient scan test devices (e.g., scan test cells coupled to internal scan test points) to achieve desirable full scan testing coverage levels.
• Scan test coverage and observability is often limited by difficulties encountered in the actual incorporation of scan test architecture components during IC manufacturing processes. Large portions of a design are often considered untestable as a practical matter primarily because faults in a section of the logic cannot be clearly observed by typical automated test pattern generation (ATPG) tools. Most ATPG tools are capable of identifying appropriate observation points necessary to enhance the maximum fault coverage. However, this information is not typically available until the design has progressed through place and route (P&R) manufacturing processes. Not having the information identifying appropriate observation points until after the place and route process makes it very difficult to implement large logic changes that are often required to accommodate the addition of the appropriate observation points. ATPG tools typically offer significant scan testing advantages (e.g., automation, cost efficiencies, etc.) and even though it is difficult, it is desirable to increase the observability of some sections of logic to aid an ATPG tool achieve desirable targeted fault coverage.
• P&R place and route
• test point coverage problems include multiplexing internal logic signals to primary input/output (I/O) pads of the device.
• I/O primary input/output
• this conventional approach or solution to alleviating test point coverage problems results in various drawbacks. For example, the conventional solution often adds excessive delays to critical timing paths during normal (non-test) operations.
• Conventional solutions typically require extensive post layout modifications to the physical design of an IC and making these modifications after layout results in many of the observations points being unreachable or inaccessible as a practical matter by typical ATPG tools.
• the system and method should support efficient scan testing of integrated circuit components with an ATPG tool while providing effective observation of scan test points.
• the electronic system and method should accommodate utilization of existing testing scan architectures and minimization of adverse redesign impacts to existing IC designs.
• the present invention is a system and method that facilitates desirable scan testing of internal components with minimal impacts to normal operations and manufacturing processes.
• the scan test observation system and method of the present invention supports efficient scan testing of integrated circuit components with an ATPG tool while providing effective observation of scan test points.
• the present invention system and method accommodates utilization of existing testing scan architectures and minimization of adverse redesign impacts to existing IC designs.
• the present invention enhances test observability in digital circuits and is compatible with scan test methodologies.
• One embodiment of the present invention includes a scan test observation point system comprising a multiplexer, a control register and an output register.
• the multiplexer selectively provides a communication path from a test point signal to the output register.
• the test point signal is a measurement or logical value captured from a functional component of an IC.
• the control register is utilized to direct the multiplexer which signal to transmit to the output register.
• the output register receives the signal transmitted from the multiplexer and transmits it on a scan test chain.
• the control register and the output register are included in a scan test chain and are utilized to shift scan test information during a scan test shift mode.
• the test point signals are assessable to an ATPG tool via the scan test observation point system.
• Figure 1 is a block diagram of one embodiment of a scan test observation point system of the present invention.
• Figure 2 is a block diagram of another embodiment of a scan test observation point system of the present invention.
• Figure 3 is a block diagram of a present invention integrated circuit including one embodiment of a scan test observation point system.
• Figure 4 is a block diagram of one embodiment of a scan test point system comprising a plurality of multiplexers and output registers.
• Figure 5 is a flow chart of scan test observation point method, one embodiment of the present invention.
• One embodiment of the present invention includes a scan test observation point system and method.
• a scan test observation point system is included in a scan testing chain permitting it to be controlled and observed by normal scan testing methodologies.
• Scan test observation point system logic devices are included in a design at various locations during the initial stages of a manufacturing process as spare logic cells in one embodiment of the present invention. After requisite test points are identified, test point signals are routed to the scan test observation point system.
• the scan test observation point system facilitates scan testing operations by an ATPG tool.
• the scan test observation point system is configured in a manner that is compatible with a scan test architecture familiar to the ATPG tool and easily accessible by the ATPG tool.
• FIG. 1 is a block diagram of scan test observation point system 100, one embodiment of the present invention.
• Scan test observation point system 100 comprises test signal selection component 110, test signal selection control component 120 and output component 130.
• Test signal selection component 110 is coupled to test signal selection control component 120 and output component 130.
• scan test observation point system 100 is included in an IC and efficiently provides observation of test points signals to an ATPG tool with minimal impacts to design processes and minimal design rework.
• Test point signal selection component 110 receives and transmits a scan test signal.
• test signal selection component 110 receives a plurality of test point signals including test point signal 131, test point signal 132 and test point signal 133 and selectively transmits one of the test point signals to output component 130.
• test point signals 131 through 133 are measurements (e.g., logical values) from test points in functional logic (not shown) utilized to perform normal operations of an IC.
• Test signal selection control component 120 controls the receiving and transmitting of the test point signal by test signal selection component 110.
• Output component 130 receives the scan test signals from test signal selection component 110 and transmits them on a scan test chain.
• scan test observation point system 100 is included in a scan test chain.
• test signal selection control component 120 controls test signal component 110 by directing test signal component 110 to transmit a . scan test signal based upon scan test information received by test signal selection control component 120 from a scan test input (e.g., scan input signal 155) on the scan test chain.
• Scan test observation point system 100 is also utilized to shift scan test information on the scan test chain.
• Scan test signal selection control component 120 receives a scan test input signal (e.g., scan input signal 155) and transmits it to output component 130 which forwards the scan test input signal unchanged downstream on the scan test chain.
• Figure 2 is a block diagram of scan test observation point system 200, one embodiment of the present invention.
• Scan test observation point system 200 comprises test signal selection multiplexer (MUX) 210, control register 221, control register 222, control register 223 and output register 231.
• Multiplexer 210 is coupled to control register 221, control register 222, control register 223 and output register 231.
• Multiplexer 210 selectively provides a communication path between one of its inputs to its output.
• the control register 221, control register 222 and control register 223 are utilized to control receiving and transmitting of the input to multiplexer 210 via the output of multiplexer 210 to output register 231.
• control registers 221 through 223 controls the receiving and transmitting of the input to multiplexer 210 by forwarding a signal to multiplexer 210 that selects which input of multiplexer 210 is transmitted out to output register 231.
• Output register 231 transmits the output of multiplexer 210 or scan test input information shifted in via control registers 221 through 223.
• scan test observation point logic devices e.g., scan test observation point logic devices comprising scan test observation point system 200
• scan test observation point logic devices are included in an IC design at various locations as spare logic cells in the initial stages of a manufacturing process.
• the inputs to a multiplexer of a scan test observation point system e.g., multiplexer 210) are coupled to static signals (e.g., logic 1 or logic 0) as a default setting during the initial stages of the manufacturing.
• static signals e.g., logic 1 or logic 0
• test point signals from the identified test points are routed to the multiplexer inputs and replace some or all of the static signals.
• the test point signals are accessible to an ATPG tool via an output register of a scan test observation point system.
• scan test operations include a shift mode and a capture mode.
• a scan input signal (scan-in) representing scan test input data is shifted in a serial fashion into a scan test chain that includes scan test observation system 200.
• the shift mode operations are accomplished by applying the scan_in signal to a scan test input port and asserting a scan enable signal (scan_en).
• scan test data is shifted into the scan test chain
• scan test information is also shifted out of the scan test chain as a scan test output signal (scan_out).
• the scan test architecture including scan test observation point system 200 is synchronous and shifting is controlled by a clock signal (clock).
• the capture mode is accomplished by deasserting the scan test enable signal and asserting a clock pulse.
• the value captured by output register 231 is dependent on the values that are shifted into the control registers 221 through 223.
• a specific set of values in the control registers 221 through 223 selects one of the test point input signals coupled to multiplexer 210 for transmission to the output of multiplexer 210.
• the output of the control registers 221 through 223 are fed back into the respective inputs of control registers 222 through 223.
• the values stored in the control registers do not change during a capture cycle.
• the feed back into the control registers 221 trough 223 is a preferred method for debugging despite some undetectable defaults.
• D inputs of control registers are coupled to another scan test observation point system.
• the D inputs of the control registers are coupled to different outputs of the control registers. To observe the captured information, the scan enable signal is reasserted and the captured data is shifted out while new values are shifted into the scan chain.
• FIG. 3 is a block diagram of integrated circuit 300, one embodiment of the present invention.
• Integrated circuit 300 comprises functional logic 310 and scan test observation point system 320.
• Functional logic 310 is coupled to scan test observation point system 320.
• Functional logic 310 is also coupled to scan enable line 312, clock line 313, scan test point bus 315 and scan output line 314.
• Scan test observation point system 320 is coupled to scan input line 311, scan enable line 312, clock line 313, scan test point bus 315, scan output line 314 and scan output line 321.
• Scan input line 311 provides a communications path for scan input signals (e.g., scan_in).
• Scan enable line 312 provides a communication path for scan enable signals (e.g., scan_en).
• Clock line 313 provides a communication path for clock signals (e.g., clock).
• Scan test point bus 315 provides a communication path for test point signals representing scan test information transmitted from functional logic 310.
• Scan output line 314 and scan output line 321 provide communication paths for scan output signals (e.g., scan_out).
• scan output line 314 carries signals received by functional logic 310 on scan input line 311 and that are passed through functional logic 310 without changing.
• scan output line 321 carries scan output signals that comprise scan output signals from scan output line 314 and for scan test information captured from functional logic 310 and transmitted via scan test point bus 315.
• Scan test observation point 320 includes scan test observation point system 200 and selectively transmits scan test information received from functional logic 310.
• a scan test observation point system receive numerous scan test point signals.
• one embodiment of a scan test observation system includes a larger test signal selection multiplexer.
• Another embodiment of a present invention scan test observation point system includes a plurality of multiplexers and output registers facilitating multiple fault captures during a scan test operation capture cycle.
• FIG. 4 is a block diagram of scan test point system 400, one embodiment of the present invention comprising a plurality of multiplexers and output registers.
• Scan test point system 400 comprises multiplexer 411, multiplexer 413, control register 421, control register 422, control register 423 and output register 431 and output register 433.
• Multiplexer 413 is coupled to control register 421, control register 422, control register 423 and output register 433.
• Multiplexer 411 is coupled to control register 421, control register 422, control register 423 and output register 431.
• Control registers 421 is coupled to control register 422 which is coupled to control reigster 423.
• Control register 423 coupled to output register 431 which is coupled to output register 433.
• scan test operations of scan test point system 400 are similar to scan test point system 200, except scan test point system 400 facilitates multiple fault captures during a scan test operation capture cycle.
• Multiplexer 411 and 413 selectively provide a communication path between one of their respective inputs to their respective outputs.
• the outputs of control register 421, control register 422 and control register 423 are utilized to select which input of multiplexer 411 and 413 are transmitted to output register 431 and 433 respectively.
• Output register 431 and 433 transmit the output of respective multiplexers 411 and 433 or output register 431 and 433 transmit scan test input information.
• FIG. 5 is a flow chart of scan test observation point method 500, one embodiment of the present invention.
• Scan test observation point method 500 facilitates scan testing of functional logic within an IC.
• scan test observation point method 500 is utilized to enhance ATPG tool scan test observation point detection and observation.
• scan test point signals are received from a functional component comprising a test point.
• a scan test point signal is received during a capture mode of a scan test system and is accomplished by deasserting a scan test enable signal and asserting a clock pulse.
• the scan test point signal is a signal received from an output of a functional logic component included in an IC after the functional logic component performs designated operations.
• the functional logic component performs designated operations based upon scan input information shifted in on the scan chain and presented to inputs of the functional component.
• step 520 scan test information is selected for transmission on a scan test chain.
• a scan test point system e.g., scan test point system 200 selects which scan test information is transmitted on the scan test chain based upon scan test input information.
• a multiplxer is utilized to provide a communication path from one of its inputs to its output based upon control values sent to the multiplexer from control logic. Control values that determine the selection of information transmitted on the scan test chain are shifted in on the scan chain to the control logic (e.g., control registers 121 through 123).
• the selection values are stored and retained during capture operations. For example, the selection values are stored in control registers by looping the output of the control registers back into the respective inputs of the control registers (e.g., 121 through 123).
• the scan test information is transmitted on a scan test chain.
• the scan test information comprises test point signals and scan test input information.
• the test point signals include signals captured from test points in functional logic.
• Scan test input information includes scan test information that is received and transmitted unchanged.
• scan test information from the output of a scan test observation point becomes input scan test information for downstream components of a scan test chain during a scan test shifting mode.
• shifting is performed by asserting a scan enable signal (scan_en) and applying an input scan test data signal (e.g., scan_in) to a scan test input port.
• scan test information is also shifted out of the scan test chain as a scan test output signal (scan_out).
• scan test operations are synchronous and shifting is controlled by a clock signal (clock).
• the present invention is a system and method that facilitates desirable scan testing of internal components with minimal impacts to normal operations and manufacturing processes.
• the system and method of the present invention supports efficient scan testing of integrated circuit components with an ATPG tool while providing effective observation of scan test points.
• a scan test observation point system and method of the present invention accommodates utilization of existing testing scan architectures and minimization of adverse redesign impacts to existing IC designs.

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