Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
  • H01L28/40—Capacitors
  • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
  • H01L28/40—Capacitors
  • H01L28/60—Electrodes
  • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
  • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

• the invention relates generally to metal oxide ceramic films used in integrated circuits (ICs) . More particularly, the invention relates to reducing diffusion of a mobile specie into the substrate.
• Metal oxide ceramic materials have been investigated for their use in ICs.
• metal oxide ceramics that are ferroelectrics or are capable of being transformed into ferroelectrics are useful due to their high remanant polarization (2Pr) and reliable long-term storage characteristics.
• Non-ferroelectric metal oxide ceramics, such as superconductors, have also been investigated.
• Metal oxide ceramics are often treated with a post- deposition thermal process at a relatively high temperature in order to produce resulting materials with the desired electrical characteristics.
• some Bi-based oxide ceramics such as strontium bismuth tantalate (SBT) are thermally treated by a "ferroanneal .
• the ferroanneal converts the as-deposited films into the ferroelectric phase. After the as-deposited films are converted into the ferroelectrxc phase, the ferroanneal continues, growing the grain size (e.g., greater than about 180 nm) of the films m order to achieve a good remanent polarization. Otner types of metal oxide ceramics can be deposited as ferroelectrics.
• PZT lead zirconium titanate
• a relatively higher temperature such as greater than 500°C
• a post-deposition thermal process is often still needed to improve its electrical characteristics.
• the metal oxide ceramics comprise a mobile specie.
• the high temperature of the post-deposition heat treatment causes diffusion of the mobile specie out of the metal oxide ceramic layer.
• the amount of mobile specie that diffuses out of the metal oxide ceramic layer is referred to as an "excess mobile specie.”
• the mobile specie can be m the form of atoms, molecules, or compounds. Diffusion of the excess mobile specie can have an adverse impact on yields.
• the excess mobile specie can easily migrate into other regions of the IC, such as the substrate, during the post deposition heat treatment. This can result m shorts and/or alter the electrical properties of other device regions, such as the diffusion regions.
• the invention relates to metal oxide ceramic films and their applications m ICs. More particularly, the invention reduces the diffusion of an excess mobile specie from a metal oxide ceramic into the substrate.
• a barrier layer is provided.
• the barrier layer serves as a diffusion barrier to reduce or minimize tne diffusion of the excess mobile specie.
• tne barrier layer is provided on a substrate separating the metal oxide ceramic and the substrate .
• the barrier comprises a material that reacts with the mobile specie. The reaction traps the mobile specie, preventing it from passing through the barrier layer.
• the barrier layer comprises a dense material m order to inhibit the passage of the mobile specie.
• a barrier layer comprising an amorphous material or a material with very small grain size is useful. Such materials extend the diffusion pathways of the mobile specie, making it more difficult for the mobile specie to diffuse through.
• the barrier layer comprises a grain surface having little or no attractive interaction with the mobile specie.
• a barrier comprising a grain surface having a strong interaction with the mobile specie and high activation energy for the mobile specie to migrate is also useful.
• the stoichio etry or composition of the metal oxide ceramic is selected to reduce or minimize diffusion of the mobile specie without adversely affecting the electrical properties of the material.
• the deposition parameters of the metal oxide ceramic can be controlled to reduce the diffusion of the excess mobile specie from the metal oxide ceramic.
• the ratio of oxidizer to the precursor amount of oxidizer is reduced to reduce diffusion of the mobile specie.
• FIG. 1 shows a schematic diagram of an illustrative embodiment of the invention
• Figs 2 shows a cross-sectional view of one embodiment of the invention
• FIGS. 3a-c show a process for forming a device in accordance with one embodiment of the invention
• Figs. 4a-4d show processes for forming alternative embodiments of the invention
• Figs. 5a-5c show a process for forming another embodiment of the invention
• Figs. 6a-6b show a process for forming an alternative embodiment of tne invention
• Figs. 7a-7b show a process for forming alternative embodiments of the invention.
• the invention relates to metal oxide ceramic films and their applications m ICs. More particularly, the invention relates to reducing the adverse effects resulting from diffusion of an excess mobile specie from a metal oxide ceramic.
• tne invention is described m tne context of a ferroelectric memory cell and a ferroelectric transistor.
• the invention is applicable to the formation of metal oxide ceramics m general.
• Other applications, such as a ferroelectric transistor comprising a metal oxide ceramic layer, are also useful.
• Ferroelectric transistors are described in, for example, Miller and Mc horter, "Physics of ferroelectric non-volatile memory field effect transistor," J. Appl. Physics, 73(12), p 5999-6010 (1992); and co-pending US patent application USSN 09/107,861, titled “Amorphously Deposited Metal Oxide Ceramic Films,” which are herein incorporated by reference for all purposes.
• the memory cell comprises a transistor 110 and a ferroelectric capacitor 150.
• a first electrode 111 of the transistor is coupled to tne bitline 125, and a second electrode 112 is coupled to the capacitor.
• a gate electrode of the transistor is coupled to the wordlme 126.
• the ferroelectric capacitor comprises first and second plates 153 and 157 separated by a ferroelectric layer 155.
• the first plate 153 is coupled to the second electrode of the transistor.
• the second plate typically serves as a common plate in the memory array.
• a plurality of memory cells is interconnected with wordlmes and bitlmes to form an array in a memory IC. Access to the memory cell is achieved by providing the appropriate voltages to the wordlme and bitlme, enabling data to be written or read from the capacitor.
• FIG. 2 a cross-section of a ferroelectric memory cell 100 in accordance with one embodiment of the invention is shown.
• the memory cell comprises a transistor 110 on a substrate 101 such as a semiconductor wafer.
• the transistor includes diffusion regions 111 and 112 separated by a channel 113, above which is located a gate 114.
• a gate oxide (not shown) separates the gate from the channel.
• the diffusion regions comprise dopants which are p-type or n-type.
• dopants chosen is dependent upon the type of transistor desired. For example, n-type dopants such as arsenic (As) or phosphorus (P) are used for n-channel devices, and p-type dopants such as boron (B) are used for p-channel devices.
• n-type dopants such as arsenic (As) or phosphorus (P) are used for n-channel devices
• p-type dopants such as boron (B) are used for p-channel devices.
• dra and the other the “source.”
• the terms “dram” and “source” are herein used interchangeably to refer to the diffusion regions.
• the current flows from the source to dra .
• the gate represents a wordlme, and one of the diffusion regions 111 is coupled to a bitlme by a contact plug (not shown) .
• a capacitor 150 is coupled to diffusion region 112 via a contact plug 140.
• the capacitor comprises bottom and top electrodes 153 and 157 separated by a metal oxide ceramic layer 155.
• the metal ceramic layer, m one embodiment, comprises a ferroelectric phase or is capable of transformation into a ferroelectric.
• the electrodes comprise a conductive material.
• composition or stoichiometry of the metal oxide ceramic layer can be tailored to cause a reduction m the amount of excess mobile specie that diffuses therefrom. By reducing the diffusion of the excess mobile specie, the metal oxide maintains a correct composition to achieve good electrical properties.
• the deposition parameters of the metal oxide ceramic can be controlled to reduce the amount of excess mobile specie diffusing out of the metal oxide ceramic.
• the ratio of oxidizer to the precursor amount of oxidizer is reduced to reduce diffusion of the excess mobile specie.
• An mterlevel dielectric (ILD) layer 160 is provided to isolate the different components of the memory cell.
• the ILD layer comprises, for example, silicate glass such as silicon dioxide (S ⁇ 0 2 ) or silicon nitride (S ⁇ 3 N 4 ) .
• Doped silicate glass such as borophosphosilicate glass (BPSG) , borosilicate glass (BSG) , or phosphosilicate glass (PSG) are also useful.
• Other types of dielectric materials can also be used.
• a barrier layer is provided to act as a diffusion barrier for the excess mobile specie.
• the barrier layer is provided between the metal oxide ceramic layer and the substrate to reduce or minimize the diffusion of the excess mobile specie into the substrate.
• the barrier layer for example, is formed on the ILD around the capacitor, protecting the substrate from the excess mobile specie .
• Figs. 3a-b show a process for forming the memory cell accordance with one embodiment of the invention.
• a substrate 201 comprising a partially formed device is shown.
• the substrate includes a transistor 210.
• the substrate for example, is a semiconductor wafer comprising silicon.
• Other types of substrates such as germanium (Ge) , gallium arsenide (GaAs) , or other semiconductor compounds can also be used.
• the substrate is lightly doped with p-type dopants such as B. More heavily doped substrates are also useful.
• a heavily doped substrate with a lightly doped epitaxial (epi) layer such as a p-/p+ substrate can also be used.
• the doped well is formed by selectively implanting dopants into the substrate the region where the transistor is formed.
• the doped well is formed by implanting p-type dopants such as B into the substrate.
• the p-type doped well (p-well) serves as a doped well for n-channel devices.
• the use of an n-type doped well (n-well) comprising, for example, As or P dopants is also useful for p-channel devices.
• Diffusion regions 211 and 212 are formed by selectively implanting dopants having a second electrical type into the desired portions of the substrate.
• n-type dopants are implanted into the p-type well used for n-channel devices, and p-type dopants are used for p-channel devices.
• An implant may also be performed to implant dopants into the channel region 213 between the diffusion regions to adjust the gate threshold voltage (V ⁇ ) of the transistor. Forming the diffusion regions after gate formation is also useful.
• the gate for example, includes gate oxide and polycrystallme silicon (poly) layers.
• the poly is, for example, doped.
• a metal silicide layer is formed over the doped poly, producing a polysilicon-silicide (polycide) layer to reduce sheet resistance.
• metal silicides including molybdenum (MoS ⁇ x ) , tantalum (TaS ⁇ x ) , tungsten ( S ⁇ x ) , titanium silicide (T ⁇ S ⁇ x ) or cobalt silicide (CoS ⁇ x ) , are useful.
• Aluminum or refractory metals, such as tungsten and molybdenum, can be used alone or m combination with silicides or poly.
• Contact plug 220 coupling diffusion region 211 to a bitlme 225 and contact plug 240 coupled to diffusion region 212 can be formed after completion of the transistor using various known techniques such as, for example, single or dual damascene techniques. Reactive ion etch (RIE) techniques are also useful. A combination of damascene and etch techniques can also be used.
• the contact plugs comprise a conductive material such as doped poly or tungsten ( ) . Other conductive materials are also useful.
• the bitlme for example, comprises aluminum (Al) or other types of conductive materials.
• An ILD layer 260 isolates the different components of the memory cell.
• tne process continues to form the ferroelectric capacitor.
• a conductive electrode barrier layer 251 is deposited on the ILD layer.
• the electrode barrier prevents the passage of oxygen into the plug.
• the electrode barrier can prevent or reduce the migration of atoms between the contact plug 240 and the subsequently formed bottom electrode.
• the electrode barrier layer comprises, for example, titanium nitride (TiN) .
• TiN titanium nitride
• Other materials such as IrS ⁇ x O y , Ce0 2 T ⁇ S ⁇ 2 , or TaS ⁇ N x are also useful.
• a conductive layer 253 is deposited over the electrode barrier layer.
• the conductive layer 253 serves as the bottom electrode.
• the bottom electrode comprises a conductive material that does not react with the subsequently deposited metal oxi ⁇ e ceramic film.
• the bottom electrode comprises a noble metal such as Pt, Pd, Au, Ir, or Rh .
• Other materials such as conducting metal oxides, conducting metal nitrides, or super conducting oxides are also useful.
• the conducting metal oxides, conducting metal nitrides, or super conducting oxides do not react with the ferroelectric layer.
• Conducting oxides include, for example, IrO x/ RhO x , RuO x , OsO ⁇ , ReO x , or WO x (where x is greater than about 0 and less than about 2) .
• Conducting metal nitrides include, for example, TiN, , ZrNv (where x is greater than about 0 and less than about 1.1), WN X , or TaN x (where x is greater than about 0 and less than about 1.7) .
• Super conducting oxides can include, for example, YBa 2 Cu 2 0 7 - x , Bi 2 Sr 2 Ca 2 Cu 3 O x , or Bi 2 Sr 2 CaiCu 2 O y .
• the electrode barrier and conductive layers are pattern to form a bottom electrode stack 280 that is coupled to contact stud 240.
• a metal oxide ceramic layer is formed above the bottom electrode stack.
• the metal oxide ceramic comprises a ferroelectric phase or is capable of transformation into a ferroelectric.
• the metal oxide ceramic layer is formed by CVD.
• the metal oxide ceramic is deposited by low temperature CVD techniques. Low temperature techniques are described in co-pending United States Patent Application USSN 08/975,087, titled “Low Temperature CVD Process using B-Diketonate Bismuth Precursor for the Preparation of Bismuth Ceramic Thin Films for Integration into Ferroelectric Memory Devices," which is herein incorporated by reference for all purposes.
• the metal oxide ceramic layer is deposited in amorphous form using CVD.
• CVD amorphously deposited metal oxide layers are described m co-pending United States Patent Application USSN 09/107,861, titled “Amorphously Deposited Metal Oxide Ceramic Films” (attorney docket number 98P7422) , which is herein incorporated by reference for all purposes.
• the metal oxide ceramic comprises a Bi-based metal oxide ceramic.
• the Bi-based metal oxide layer is generally expressed by Y a Bi b X 2 ⁇ c , where Y comprises a 2-valent cation and X comprises a 5-valent cation.
• Y is equal to one or more elements selected from Sr, Ba, Pb, and Ca.
• X, m one embodiment, is equal to one or more elements selected from Ta and Nb .
• the subscript "a” refers to the number of Y atoms for every 2X atoms; subscript "b” refers to the number of Bi atoms for every 2X atoms; and subscript "c” refers to the number of oxygen atoms for every 2X atoms.
• a Bi-based oxide comprising Sr and Ta is
• the Bi-oxide comprises SBT
• the ferroelectric SBT comprises a layered perovskite structure having negatively charged perovskite layers of Sr and Ta oxide separated by positively charged Bi oxide layers.
• the stoichiometry of the Sr and Ta oxide is for example [SrTa 2 O ⁇ 1 2n" n
• the stoichiometry of the Bi oxide layers is for example [B ⁇ 2 0 2 ] 2n+ n . creating a structure of alternating .
• SBT derivatives include Sr,3i s Taj-vNo,0 c ( 0 ⁇ x ⁇ 2 ) , Sr a B ⁇ b NbaO c/ Sr a 3 b Ta 2 O c , Sr a -
• tne Bi-based oxide ceramic comprises B ⁇ T ⁇ 3 0 ⁇ 2 or its derivatives.
• Derivatives of Bi 4 Ti 3 0i 2 include, for example, PrB ⁇ 3 T ⁇ 3 0 ⁇ 2 , HoB ⁇ 3 T ⁇ 3 0 ⁇ 2 , LaBi 3 Ti 3 0.
• the Bi-based metal oxide ceramic is deposited by low temperature CVD techniques.
• the Bi-based metal oxide is deposited amorphously by CVD.
• the temperature at which the Bi-based metal oxide is deposited is, for example about 430°C or less and preferably about 385-430°C.
• the precursors can be individually dissolved in a solvent system and stored in a respective reservoir of the delivery subsystem.
• the precursors are mixed in the correct ratio prior to deposition. Mixing the precursors in a single reservoir is also useful.
• the precursors should be highly soluble in the solvent system.
• the solubility of the precursors in the solvent system is, for example, about 0.1 - SM. Solubility of about 0.1 - 2M or about 0.1 - 1M is also useful.
• the composition of the Bi-based metal oxide can be tailored to reduce diffusion of the mobile specie.
• the mobile specie of the Bi-based metal oxide ceramic comprises Bi such as, for example, Bi or Bi 2 0 3 . From experiments, it has been found that the composition of the Bi-based metal oxide ceramic layer influences the amount of mobile specie (Bi) that diffuses out of the layer.
• a Bi- based metal oxide ceramic layer comprising a composition having a Bi ratio to 2X (b in the formula Y a Bi D X 2 0 : ) of greater than 2.4 results in significant Bi loss or diffusion.
• the Bi-based metal oxide ceramic comprises a composition wherein b is less than or equal to about 2.4 to reduce diffusion of the excess mobile specie.
• the composition of the metal oxide ceramic layer comprises a value of b of about 1.95 to 2.2 and more preferably about 2.0 to 2.2.
• the content of Y molecules also influence Bi loss from the Bi-based metal oxide ceramic. It is believed that decreasing that amount of Y atoms (e.g., Y deficient composition) provides additional sites for the Bi atoms to occupy, thereby reducing the amount of Bi that can diffuse out of the metal oxide ceramic layer. This is also advantageous as the resulting layer comprises a structure which produces good electrical properties.
• the composition of the metal oxide ceramic layer comprises a Y to 2X ratio (a in the formula Y a Bi b X 2 O c ) of about 0.8 to 1.0.
• a value of a equal to about 0.9-1.0 has also been found to be useful in reducing the diffusion of the excess mobile specie and without degrading the electrical properties of the Bi-based metal oxide ceramic layer.
• the Bi-based metal oxide ceramic comprises SBT.
• the SBT comprises a b value of less than about 2.4.
• the composition of the SBT comprises a b value of about 1.95 to 2.2, preferably about 2.0 to 2.2.
• the Sr to 2Ta (a) ratio of the SBT is about 0.8 to 1.0.
• An anneal is performed after the formation of the metal oxide ceramic layer.
• the anneal transforms the as- deposited metal oxide ceramic into a layer having the desired electrical characteristics.
• the anneal transforms the as-deposited metal oxide into the ferroelectric phase.
• the anneal also grows the grains of the ferroelectric phase to produce good electrical properties, such as high 2Pr.
• the anneal is typically performed at about 750-800°C for about 1-60 minutes m an oxygenated ambient. Lower temperatures are also useful. For example, the anneal can be performed at about 650-750°C. Lower temperatures, however, may require a longer anneal (e.g., about 30-120 minutes) to achieve the desired electrical properties.
• the duration of the anneal can vary depending on the electrical properties desired.
• a conductive layer 257 is deposited over the metal oxide ceramic layer to form the top electrode.
• the conductive layer comprises, for example, a noble metal such as Pt, Pd, Au, Ir, or Rh. Other materials such as those used to form the bottom electrode are also useful. It is often useful to perform an anneal after the deposition of the top electrode to ensure a well define interface between the metal oxide ceramic and electrode. The anneal to recover the interface between the metal oxide ceramic and electrode can be typically performed at about 500-800°C for about 1-30 minutes in oxygen ambient with 0 2 flow rate of about 5 slm. Having a well-defined interface between the electrode and metal oxide ceramic is advantageous as this reduces, for example, leakage currents.
• the pre-anneal typically is performed at a temperature of less than about 750°C. In one embodiment, the pre-anneal is performed at about 700-750°C. The duration of the pre- anneal is about 5-10 minutes. In another embodiment, the pre-anneal is performed at less than 700°C. At lower temperatures, a longer per-anneal may be required to partially or fully transform the metal oxide ceramic into the ferroelectric phase.
• the top electrode typically serves as a common electrode, connecting other capacitors m the memory array. The top electrode, along with the other layers underneath, can be patterned as necessary to provide contact openings to the bitl es and wordlmes. Additional processing is performed to complete the ferroelectric memory IC. Such additional processing is known in the art. For example, the additional processing includes forming support circuitry, final passivation layer, contact openings the passivation layer for testing and connecting to lead frame, and packaging.
• a substrate 201 comprises a partially formed memory cell similar to that already described, with similar reference numbers designating similar features.
• a barrier layer 275 is deposited over the ILD layer 260.
• the barrier layer comprises a material which reacts with the excess mobile specie.
• the barrier layer comprises an oxide that reacts with the Bi mobile specie.
• the barrier layer comprises an oxide selected from the group containing early transitional metals. Such oxides include, for example, Sc 2 0 3 , Y 2 0 3 , T ⁇ 0 2 , Zr0 2 , Hf0 2 , V 2 0 5 , Nb 2 0 5 , Ta 2 0 5 , and T ⁇ 0 2 .
• the barrier layer comprises T ⁇ 0 2 , and Ta 2 0 5 -
• the barrier layer comprises a transitional metal oxide combined with a lanthanide oxide such as Pr 2 0 3 , HO20J, or La 2 0 3 to form respective barrier layers PrB ⁇ 3 T ⁇ 3 0 ⁇ 2 , HoB ⁇ 3 T ⁇ 3 0 12 , and LaB ⁇ 3 T ⁇ 3 0 ⁇ 2 after the reaction with the Bi-contaimng excess mobile specie.
• Transitional metal nitrides include, for example, T ⁇ N x , ZrN x , and HfN x with 0 ⁇ x ⁇ l; TaN x and NbN x with 0 ⁇ x ⁇ 1.5; WN X and MoN x with 0 ⁇ x ⁇ 2.
• the nitride is oxidized to form a non-conducting barrier layer.
• the barrier comprises a dense material that reduces the migration of the excess mobile specie from the metal oxide ceramic into the substrate.
• Materials that are sufficiently dense, m the case of Bi- based metal ox- ⁇ e ceramics, to reduce the diffusion of Bi mobile specie include oxides such as A1 2 0 3 , Sc 2 0 3 , Y 2 0 3 , MgO, BeO, T ⁇ 0 2 , and Ta 2 0 5 .
• the barrier layer can be formed by various deposition techniques, such as sputtering, CVD, or physical vapor deposition (PVD) . Other deposition techniques can also be useful.
• the barrier layer is deposited on the substrate by sputtering using, for example, an oxide target or a metal target m the presence of oxygen.
• the temperature at which the barrier layer is sputtered is about 200-400°C.
• Lower sputtering temperatures such as, for example, of about 20-200°C and preferably about 200°C results in finer grains, which can be advantageous because the they extend the diffusion pathways of the mobile specie. Higher temperatures, s ⁇ ch as greater than 400°C can also be useful.
• tne barrier layer is deposited metallic form by sputtering or CVD. After deposition, the barrier layer is annealed oxygen to transform the as-deposited layer into an oxide barrier layer. The anneal, due to oxidation, leads to expansion of the as-deposited layer, thereby increasing ts density.
• the expansion can create an excessive amount of compressive stress.
• the barrier layer can be deposited under tensile stress. Tensile stress can be induced by depositing the barrier layer at elevated temperatures of about, for example, 200-400°C.
• the barrier layer can be deposited with a deficient oxygen content to form a mixture of oxide and metal or suboxide. An anneal is then performed oxygen to oxidized the barrier layer. Since the as-deposited film comprises a suboxide (a metal having an oxidation state that s less than its highest oxidation state) or a mixture or oxide and metal, the amount of volume expansion is less, t erec decreasing the compressive stress.
• the barrier layer comprises a Ti- suboxide.
• the stoichiometry of the Ti-suboxide is, for
• T ⁇ O x where x is 0.5 ⁇ x ⁇ 1.5.
• a barrier layer comprising Ta-suboxide is also useful.
• the Ta-suboxide can be expressed as TaO and where x is about
• the barrier layer comprises a barrier stack having first and second barrier layers .
• the first barrier layer comprises a material having a small diffusion constant for the mobile specie
• the second barrier layer comprises a material having high reactivity with the mobile specie.
• the second barrier layer tends to attract the mobile specie with which it reacts to form a stable compound.
• the first barrier layer prevents the passage of the mobile specie due to its denseness .
• the second barrier layer is formed above the first barrier layer.
• the excess mobile specie reacts with the second barrier layer and becomes trapped therein.
• the first barrier layer below prevents the passage of excess mobile specie due to its denseness.
• the barrier and ILD layers are patterned to form an opening to diffusion region 212.
• a conductive material is deposited, filling the opening.
• the excess conductive material can be removed by, for example, a chemical mechanical polish (CMP) to form a contact plug 240.
• CMP chemical mechanical polish
• a conductive layer 253 serving as a bottom electrode is deposited on the substrate, covering the barrier layer and contact plug 240.
• a conductive electrode barrier layer 251 can be formed on the substrate prior to the formation of the conductive layer to prevent the passage of oxygen into the plug 240.
• the electrode barrier layer can also serve to reduce migration of atoms between the contact plug and the electrode.
• the electrode barrier and conductive layers are patterned to form a bottom electrode stack 280.
• the bottom electrode is coupled to the diffusion region 212 by contact plug 240.
• a metal oxide ceramic layer 255 is formed over the bottom electrode and ILD layer.
• the metal oxide ceramic one embodiment, comprises a ferroelectric phase or is capable of transformation into a ferroelectric. As previously described, the composition of the metal oxide ceramic can be tailored to reduce diffusion of the excess mobile specie.
• An anneal is performed to transform the metal oxide ceramic into the desired phase with good electrical properties.
• a conductive layer 257 is deposited over the metal oxide ceramic to form the top electrode. Performing the anneal after the formation of the top electrode 257 can also be useful. Alternatively, a pre-anneal is performed after the deposition of the metal oxide ceramic to form the ferroelectric phase, and then an anneal is performed after the formation of the top electrode to achieve the desired electrical properties.
• the top electrode typically serves as a common electrode, connecting other capacitors in the memory array.
• the top electrode along with the other layers underneath, can be patterned as necessary to provide contact openings to the bitlines and wordlines. Additional processing is performed to complete the ferroelectric memory IC.
• an electrode barrier layer is deposited over the ILD layer and patterned to form the electrode barrier 251 on top of the plug 240.
• a conductive material is deposited and patterned to form the bottom electrode 253.
• the bottom electrode covers the electrode barrier 251 and a portion of the barrier layer 275. The process continues as described in Fig. 4c.
• Figs. 5a-c shows another embodiment of the invention.
• a substrate 201 comprises a partially formed memory cell as previously described.
• a barrier layer 275 in accordance with the invention is formed over the substrate surface.
• the barrier layer is patterned using conventional masking and etching processes to form an opening 241, exposing the surface of the contact plug.
• the opening 241 exposes only the surface of the plug 240.
• Providing an opening 241 that also exposes a portion of the ILD layer, as depicted by the dotted lines 242, is also useful.
• the opening can be the size of the subsequently formed bottom electrode. Other techniques for removing excess electrode barrier material can also be used.
• an electrode barrier layer is deposited over substrate, covering the barrier 275 and electrode.
• the substrate surface can be planarized by CMP to remove excess electrode barrier material from the surface of the barrier layer 275.
• the CMP produces a planar top surface 276.
• a conductive layer 253 is deposited over substrate surface and patterned to form a bottom electrode.
• a metal oxide ceramic layer 255 is deposited over substrate, covering the electrode and barrier layer 275.
• the composition can be tailored to reduce the amount of excess mobile specie that diffuses out.
• An anneal is performed to transform the metal oxide ceramic into the desired phase with good electrical properties.
• a conductive layer 257 is deposited over the metal oxide ceramic to form the top electrode.
• a pre-anneal is performed after the deposition of the metal oxide ceramic to partially or fully form the ferroelectric phase, and then an anneal is performed after the formation of the top electrode to, if necessary, fully transform the metal oxide ceramic into the ferroelectric phase, to promote gram growth to achieve the desired electrical properties, and to ensure a well-defined metal oxide ceramic/electrode interface. Additional processing is performed to complete the ferroelectric memory IC.
• Figs. 6a-b snows another embodiment of the invention.
• a substrate 201 comprises a partially formed memory cell as previously described.
• a barrier layer 275 m accordance with the invention is deposited over the ILD 260.
• an additional ILD layer 261 is formed over the barrier layer 275.
• the additional ILD layer although not necessarily, can be formed from the same material as the ILD layer 260.
• the contact plug 240 is formed by pattering the ILD layer 261 and layers thereunder to expose the diffusion region 212.
• a conductive material is deposited, filling the opening. Excess conductive material can be removed by, for example, a chemical mechanical polish (CMP) to form a contact plug 240.
• CMP chemical mechanical polish
• An electrode barrier layer 251 and conductive layer 253 are deposited on the substrate and patterned to form a bottom electrode stack 280.
• the bottom electrode stack is coupled to the diffusion region 212 by contact plug 240.
• a conductive layer 253 is formed over the ILD layer 260.
• the conductive layer comprises a conductive material which blocks the diffusion of the excess mobile specie through it.
• the conductive material preferably does not react with the subsequently formed metal oxide ceramic 255.
• the conductive layer can be formed by, for example, sputtering, physical vapor deposition, or CVD. Other deposition processes for the conductive layer are also useful .
• the conductive material oxidizes during an anneal.
• the formed oxide can segregate from the base electrode material and fill the gaps between gram boundaries, thereby blocking the diffusion of the mobile specie.
• the oxide can be integrated into the base electrode material, forming fully or highly miscible material which reacts to trap the excess mobile specie.
• the conductive layer comprises a base conductive material such as a noble metal.
• the noble metal includes, for example, Pt, Pd, Au, Ir, or Rh.
• the noble metal is combined with a metal that oxidizes during a thermal treatment (anneal) to form a conductive layer that suppresses the diffusion of the mobile specie.
• the noble metal is combined with a metal selected from the group comprising Ti, Ta, Nb, W, Mo, Mg,
• a metal oxide ceramic layer 255 is deposited over substrate, covering the electrode and barrier layer 275. The composition of the metal oxide ceramic can be tailored to reduce the amount of excess mobile specie that diffuses out .
• a substrate 201 comprises a partially formed memory cell as previously described.
• the surface of the plug 240 is recessed below the surface of the ILD layer 260.
• An electrode barrier layer is formed over the substrate, covering the substrate and filling the recess. Excess material is removed by, for example, CMP, leaving the electrode barrier 251 above the plug. Other techniques for removing the excess material are also useful.
• a barrier layer 275 accordance with the invention is deposited over the substrate, covering the ILD and electrode barrier.
• the barrier layer is patterned, exposing the electrode barrier.
• a conductive layer 253 is deposited on the substrate and patterned to form the bottom electrode.
• a metal oxide ceramic layer 255 is deposited over substrate, covering the electrode and barrier layer 275.
• the composition of the metal oxide ceramic can be tailored to reduce the amount of excess mobile specie that diffuses out.
• An anneal is performed to transform the metal oxide ceramic into the desired phase with good electrical properties.
• a conductive layer 257 is deposited over the metal oxide ceramic to form the top electrode.
• a anneal is then performed to ensure a well defined metal oxide ceramic/electrode interface.
• a pre-anneal is performed after the deposition of the metal oxide ceramic to partially or fully form the ferroelectric phase, and then an anneal is performed after the formation of the top electrode to, if necessary, fully transform the metal oxide ceramic into the ferroelectric phase, to promote gram growth to achieve the desired electrical properties, and to ensure a well-defined metal oxide ceramic/electrode interface. Additional processing is performed to complete the ferroelectric memory IC.

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• Condensed Matter Physics & Semiconductors (AREA)
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• Semiconductor Memories (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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• 1999
  • 1999-12-08 KR KR1020017007678A patent/KR20010086116A/ko not_active Application Discontinuation
  • 1999-12-08 WO PCT/IB1999/002028 patent/WO2000038247A1/en not_active Application Discontinuation
  • 1999-12-08 CN CNB998146153A patent/CN1199287C/zh not_active Expired - Fee Related
  • 1999-12-08 JP JP2000590226A patent/JP2003536239A/ja not_active Withdrawn
  • 1999-12-08 EP EP99958444A patent/EP1142027A1/en not_active Withdrawn
  • 1999-12-15 TW TW088122022A patent/TW478176B/zh not_active IP Right Cessation

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