EP1135797A1 - Textured bi-based oxide ceramic films - Google Patents

Textured bi-based oxide ceramic films

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Publication number
EP1135797A1
EP1135797A1 EP99963947A EP99963947A EP1135797A1 EP 1135797 A1 EP1135797 A1 EP 1135797A1 EP 99963947 A EP99963947 A EP 99963947A EP 99963947 A EP99963947 A EP 99963947A EP 1135797 A1 EP1135797 A1 EP 1135797A1
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EP
European Patent Office
Prior art keywords
composition
metal oxide
ferroelectric
ratio
based metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP99963947A
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German (de)
French (fr)
Inventor
Debra A. Desrochers
Bryan C. Hendrix
Jeffrey F. Roeder
Frank S. Hintermaier
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Infineon Technologies AG
Advanced Technology Materials Inc
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Infineon Technologies AG
Advanced Technology Materials Inc
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Priority claimed from US09/197,984 external-priority patent/US6713797B1/en
Application filed by Infineon Technologies AG, Advanced Technology Materials Inc filed Critical Infineon Technologies AG
Publication of EP1135797A1 publication Critical patent/EP1135797A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material

Abstract

A non-volatile memory cell wherein the capacitor comprises a Bi-based metal oxide having a crystallographic texture to produce high switchable polarization.

Description

TEXTURED BI-BASED OXIDE CERAMIC FILMS
Cross-Reference to Related Application
This is a continuation-in-part of US Patent Application USSN 09/107,861 filed on June 30, 1998.
Field of the Invention
The invention relates generally to Bi-based metal oxide ceramic films used in integrated circuits (ICs) . More particularly, the invention relates to textured Bi- based metal oxide ceramic films with high switchable electrical polarization.
Background of the Invention
Metal oxide films have been investigated for their use in integrated circuits (ICs) . In particular, metal oxide films comprising strontium, bismuth, and tantalum, such as SrBi2Ta209 (SBT) , have attracted considerable attention because of their excellent ferroelectric properties. The ferroelectric properties of SBT make them a promising material for memory capacitors in nonvolatile ferroelectric random access memory ICs. Various techniques, such as sol -gel, chemical vapor deposition (CVD) , sputtering, pulsed laser deposition (PLD) , and evaporation, have been developed for depositing such films on a substrate.
Fatigue in the ferroelectric material causes degradation in polarization (2Pr) . Degradation in polarization is undesirable as it creates reliability issues in the memory IC. For example, degradation in polarization can result in the signal from the stored charge being too small to be unequivocally defined as a logical "0" or "1." To compensate for polarization fatigue, a ferroelectric material with high switchable polarization is needed to increase the reliability of the memory cells.
Other factors also contribute to a need for providing ferroelectric materials with high 2Pr. For example, higher integration densities of devices result in smaller capacitors, necessitating a higher 2Pr value to store the same charge on a smaller capacitor. Also, material degradation due to post-processing can decrease the material's 2Pr value.
From the above discussion, it is desirable to produce a Bi-based metal oxide with high switchable polarization.
Summary of the Invention The invention relates to Bi-based metal oxide ceramic layer. In accordance with the invention, the Bi- based metal oxide ceramic layer comprises a crystallographic texture with the correct orientation to result in an increase in the switchable electrical polarization.
In one embodiment, the Bi-based metal oxide ceramic is expressed by YaBibX2Oc, where Y comprises a 2-valent cation and X comprises a 5-valent cation. In one embodiment, Y is equal to one or more elements selected from Sr, Ba, Pb, and Ca . X, in one embodiment, is equal to one or more elements selected from Ta and Nb . Various techniques, such as sol-gel, chemical vapor deposition (CVD) , sputtering, pulsed laser deposition (PLD) , and evaporation, can be used to form the Bi-based metal oxide. In one embodiment, the Bi-based metal oxide is deposited amorphously by CVD. The amorphous CVD material is post-deposition processed to transform it into a material with the desired electrical properties.
Appropriate control of the composition of the Bi- based oxide can result in a highly textured material . In one embodiment, the composition of the Bi-based oxide is controlled to result in a crystallographic texture of the material having an orientation that produces an increase in the average of the components in the polarization direction perpendicular to a conductive layer.
In one embodiment of the invention, the composition of Bi-based metal oxide comprises a Y/2X ratio of about 0.5-0.9, preferably about 0.6-0.8, and more preferably 0.7-0.8. The ratio of Bi/2X, in one embodiment, is about 2.0-2.6, preferably about 2.1-2.5, and more preferably 2.1-2.3.
Brief Description of the Drawings
Fig. 1 shows a ferroelectric memory cell in accordance with one embodiment of the invention;
Fig. 2 shows a metal oxide field effect transistor comprising a ferroelectric layer in accordance with one embodiment of the invention;
Fig. 3 shows a layered perovskite structure of the ferroelectric SBT;
Figs. 4-6 show the texture of the Bi-based oxide as a function of composition; and
Fig. 7 shows the correlation between switchable polarization (2Pr) with respect to composition.
Detailed Description Of The Invention
The invention relates to Bi-based metal oxide ceramic films and their applications in ICs. More particularly, the invention relates to Bi-based metal oxide ceramics comprising a crystallographic texture controlled by its composition.
In accordance with one embodiment of the invention, a Bi-based metal oxide film is deposited on a substrate. Various techniques, such as sol -gel, chemical vapor deposition (CVD) , sputtering, pulsed laser deposition (PLD) , and evaporation can be used to deposit the Bi- based metal oxide film. Preferably, the Bi-based metal oxide is deposited by CVD. More preferably, the Bi-based metal oxide is deposited amorphously by CVD. Typically, a post -deposition heat treatment such as an anneal is performed to transform the Bi-based oxide into a ferroelectric material. The post-deposition heat treatment produces a highly textured Bi-based oxide ceramic .
For purposes of illustration, the invention is described in the context of a ferroelectric memory cell and a ferroelectric transistor. However, the invention is applicable to the formation of Bi-based metal oxide ceramics with high switchable polarization in general . Other applications such as a transistor comprising a Bi- based metal oxide layer are also useful . Ferroelectric transistors are described in, for example, Miller and McWhorter, "Physics of ferroelectric nonvolatile memory field effect transistor," J. Appl . Physics, 73(12), p 5999-6010 (1992); and co-pending US patent application USSN 09/107,861, titled "Amorphously Deposited Metal Oxide Ceramic Films," which are herein incorporated by reference for all purposes.
Referring to Fig. 1, a schematic diagram of a ferroelectric memory cell 100 in accordance with one embodiment of the invention is shown. As shown, the memory cell comprises a transistor 110 and a ferroelectric capacitor 150. A first electrode 111 of the transistor is coupled to the bitline 125 and a second electrode 112 is coupled to the capacitor. A gate electrode of the transistor is coupled to the wordline 126.
The ferroelectric capacitor comprises first and second plates 153 and 157 separated by a Bi-based ferroelectric layer. The first plate 153 is coupled to the second electrode of the transistor. The second plate typically serves as a common plate in the memory array.
In accordance with the invention, the Bi-based ferroelectric layer comprises a crystallographic texture controlled by its composition. Providing a correctly oriented crystallographic texture in Bi-based metal oxide ferroelectric layer results in a high switchable polarization.
Typically a plurality of memory cells is interconnected with wordlines and bitlines to form an array in a memory IC. Access to the memory cell is achieved by providing the appropriate voltages to the wordline and bitline, enabling data to be written or read from the capacitor.
Referring to Fig. 2, a cross-section of an illustrative ferroelectric memory cell 100 in accordance with one embodiment of the invention is shown. The memory cell comprises a transistor 110 formed on a substrate 101 such as a semiconductor wafer. The transistor includes diffusion regions 111 and 112 separated by a channel 113, above which is located a gate 114. A gate oxide (not shown) separates the gate from the channel . The diffusion regions comprise dopants which are p-type or n-type. The type of dopants chosen is dependent upon the type of transistor desired. For example, n-type dopants such as arsenic (As) or phosphorus (P) are used for n-channel devices, and p-type dopants such as boron (B) are used for p-channel devices. Depending on the direction of current flow between the diffusion regions, one is referred to as the "drain" and the other the "source." The terms "drain" and "source" are herein used interchangeably to refer to the diffusion regions. Typically, the current flows from the source to drain. The gate represents a wordline, and one of the diffusion regions 111 is coupled to a bitline by a contact plug (not shown) .
A capacitor 150 is coupled to diffusion region 112 via a contact plug 140. The capacitor comprises bottom and top electrodes 153 and 157 separated by a ferroelectric layer 155. A highly textured erroelectric layer is provided. The crystallographic texture is controlled by the composition of the ferroelectric layer. The electrodes are typically formed from noble metal such as, for example, Pt . A conductive barrier layer 151 can be provided between the bottom electrode and contact plug. The barrier layer inhibits the diffusion of oxygen into the contact plug 140. The barrier layer also inhibits 1) the diffusion of atoms from the plug into the ferroelectric layer, and 2) the migration of atoms from the bottom electrode or ferroelectric layer into the plug.
An interlevel dielectric (ILD) layer 160 is provided to isolate the different components of the memory cell. The ILD layer comprises, for example, silicate glass such as silicon dioxide (Si02) or silicon nitride (Si3N4) . Doped silicate glass such as borophosphosilicate glass (BPSG) , borosilicate glass (BSG) , or phosphosilicate glass (PSG) are also useful. Other types of dielectric materials can also be used.
The memory cell 100 is formed by a process sequence that includes forming the transistor 110 on the substrate. The substrate, for example, is a semiconductor wafer comprising silicon. Other types of substrates such as germanium (Ge) , gallium arsenide (GaAs) , or other semiconductor compounds can also be used. Typically, the substrate is lightly doped with p- type dopants such as B. More heavily doped substrates are also useful. A heavily doped substrate with a lightly doped epitaxial (epi) layer such as a p-/p+ substrate can also be used. N-type doped substrates, including lightly doped, heavily doped, or heavily doped substrates with a lightly doped epi layer, are also useful .
A doped well comprising dopants, if necessary, is provided to prevent punchthrough. The doped well is formed by selectively implanting dopants into the substrate in the region where the transistor is formed. A photoresist mask layer can be used for selectively implanting the dopants. In one embodiment, the doped well is formed by implanting p-type dopants such as B into the substrate. The p-type doped well (p-well) serves as a doped well for n-channel devices. The use of an n-type doped well (n-well) comprising, for example, As or P dopants is also useful for p-channel devices.
Diffusion regions 111 and 112 are formed by selectively implanting dopants having a second electrical type into the desired portions of the substrate. In one embodiment, n-type dopants are implanted into the p-type well used for n-channel devices and p-type dopants are used for p-channel devices. An implant may also be performed to implant dopants into the channel region between the diffusion regions to adjust the gate threshold voltage (Vτ) of the transistor. Forming the diffusion regions after gate formation is also useful . Various layers are deposited on the substrate and patterned to form the gate. The gate, for example, include gate oxide and polycrystalline silicon (poly) layers. The poly is, for example, doped. In some cases, a metal suicide layer is formed over the doped poly, producing a polysilicon-silicide (polycide) layer to reduce sheet resistance. Various metal suicides, including molybdenum (MoSix) , tantalum (TaSix) , tungsten (WSix) , titanium suicide (TiSix) or cobalt suicide (CoSix) , are useful. Aluminum or refractory metals, such as tungsten and molybdenum, can be used alone or in combination with suicides or poly. Contact plugs and bitline can be formed after completion of the transistor using various known techniques such as, for example single or dual damascene techniques. Reactive ion etch (RIE) techniques are also useful . A combination of damascene and etch techniques can also be used. The contact plugs comprise a conductive material such as doped poly or tungsten ( ) . Other conductive materials are also useful. The bitline, for example, comprises aluminum (Al) or other types of conductive materials. An ILD layer 160 isolates the different components of the memory cell .
To prevent or reduce migration of atoms between the contact plug 140 and the subsequently formed ferroelectric layer, a conductive barrier layer 151 over the ILD layer. The barrier layer comprises, for example, titanium nitride (TiN) . Other materials such as IrSixOy, Ce02/TiSi2, or TaSiNx are also useful.
The process continues by forming the ferroelectric capacitor 150. A conductive layer 153 is deposited over the barrier layer. The conductive layer 153 serves as the bottom electrode. The bottom electrode comprises a conductive material. Preferably, the conductive material does not react with the subsequently deposited metal oxide ceramic film. In one embodiment, the bottom electrode comprises a noble metal such as Pt , Pd, Au, Ir, or Rh. Other materials such as conducting metal oxides, conducting metal nitrides, or super conducting oxides are also useful. Preferably, the conducting metal oxides, conducting metal nitrides, or super conducting oxides do not react with the ferroelectric layer. Conducting oxides include, for example, IrOx, RhOx, RuOx, OsOx, ReOx, or Ox (where x is greater than about 0 and less than about 2). Conducting metal nitrides include, for example, TiNx, ZrNx (where x is greater than about 0 and less than about 1.1) , NX, or TaNx (where x is greater than about 0 and less than about 1.7) . Super conducting oxides can include, for example, YBa2Cu207-x or
The conductive and barrier layers are patterned to form a bottom electrode.
A Bi-based metal oxide layer 155 is formed over the conductive layer 153. In accordance with the invention, the resulting Bi-based oxide layer comprises a crystallographic texture which produces a high switchable polarization. Various techniques, such as such as sol- gel, chemical vapor deposition (CVD), sputtering, pulsed laser deposition (PLD) , and evaporation, are used to form the Bi-based metal oxide. Preferably, the Bi-based metal oxide is formed by CVD. In one embodiment, The Bi-based oxide is deposited by low temperature CVD techniques. Low temperature techniques are described in co-pending United States Patent Application USSN 08/975,087, titled "Low Temperature CVD Process using B-Diketonate Bismuth Precursor for the Preparation of Bismuth Ceramic Thin Films for Integration into Ferroelectric Memory Devices," which is herein incorporated by reference for all purposes. Depositing the Bi-based oxide amorphously by CVD is also useful. CVD Amorphously deposited Bi-based oxide layers are described in co-pending United States Patent Application USSN 09/107,861, titled " Amorphously Deposited Metal Oxide Ceramic Films" (attorney docket number 98P7422) , which is herein incorporated by reference for all purposes.
In one embodiment, the Bi-based metal oxide layer is generally expressed by YaBibX2Oc, where Y comprises a 2- valent cation and X comprises a 5-valent cation. In one embodiment, Y is equal to one or more elements selected from Sr, Ba, Pb, and Ca . X, in one embodiment, is equal to one or more elements selected from Ta and Nb . The subscript "a" refers to the number of Y atoms for every 2X atoms; subscript "b" refers to the number of Bi atoms for every 2X atoms; and subscript " c" refers to the number of oxygen atoms for every 2X atoms .
In one embodiment, the Bi-based oxide ceramic comprises Sr. A Bi-based oxide comprising Sr and Ta is also useful. Preferably, the Bi-oxide comprises SraBibTa2Oc. Derivatives of SBT are also useful. SBT derivatives include SraBibTa2-xNbxOc ( 0<x<2 ) , SraBibNb2Oc, Sra_ xBaxBibTa2_yNbyOc (O≤x≤l, 0≤y≤2), Sra_xCaxBi2Ta2-yNby09 (O≤x≤l,
0≤y≤2) , Sra_xPbxBi2Ta2-yNbyOc (O≤x≤l, 0≤y<2), or
Sra-x-y-2BaxCayPbzBibTa2_pNbpOc (O≤x≤a, O≤y≤a, O≤z≤a, 0≤p≤2) . Substituting or doping the Bi-based oxides or SBT derivatives with a metal of the lanthanide series is also useful .
Precursors and reactive gases employed to form the Bi-based oxide ceramic are described in co-pending United States Patent Application USSN 08/975,087, titled "Low Temperature CVD Process using B-Diketonate Bismuth Precursor for the Preparation of Bismuth Ceramic Thin Films for Integration into Ferroelectric Memory Devices," which was filed on November 20, 1997; and co-pending United States Patent Application USSN 08/960,915, titled "Anhydrous Mononuclear Tris (Beta-Diketonate) Bismuth Compositions and Method of Making the Same," which was filed on October 30, 1997, and which are all herein incorporated by reference for all purposes.
In one embodiment, the Bi precursor of the Bi-based
oxide ceramic comprises Bi (β-diketonate) . Preferably, the Bi precursor comprises Bi(thd)3. Bi alcoxides, Bi carboxylates, Bi amides, and Bi aryls are also useful Bi precursors. In one embodiment, the Bi aryl precursor comprises BiPh3.
The Sr precursor of the Bi-based oxide ceramic
comprises, for example, Sr (β-diketonate) . In one embodiment, the Sr precursor comprises Sr(thd)2.
Sr (thd) 2 (adduct) such as
Sr (thd) 2 (pentamethyldiethylenetriamine) or
Sr (thd) 2 (tetraglyme) is especially useful.
The Ta precursor of the Bi-based oxide ceramic
comprises, for example, Ta (β-diketonate) . Ta alcoxides are especially useful Ta precursors. In one embodiment, the Ta precursor comprises Ta (β-diketonate) alcoxides such as Ta (thd) x (OR) 5-x. A Ta precursor such as Ta(thd) (0- i-Pr)4 is also useful.
In another embodiment, the SBT or SBT-derived film is formed with Bi(thd)3, Sr(thd)2 pentamethyldiethylenetriamine adduct, and Ta (O-i-Pr) 4 (thd) precursors. Other precursors for the deposition of the Bi-based oxides are also useful.
The precursors can be individually dissolved in a solvent system and stored in a respective reservoir of the delivery subsystem. The precursors are mixed in the correct ratio prior to deposition. Mixing the precursors in a single reservoir is also useful . The precursors should be highly soluble in the solvent system. The solubility of the precursors in the solvent system is, for example, about 0.1 - 5M. Solubility of about 0.1 - 2M or about 0.1 - 1M is also useful.
The Bi-based metal oxide layer is annealed under appropriate conditions, transforming it into a ferroelectric material. Typically, the anneal is performed at a temperature of about 500-850°C. Annealing the metal oxide layer at a temperature of about 600-800°C, 650-750°C, 600-700°C, or 650-700°C is also useful. The temperature of the anneal can vary depending on the nature of the deposited film. For example, amorphously deposited films can be annealed at a relatively lower temperature. The anneal transforms the metal oxide layer into a highly textured ferroelectric material .
A conductive layer 157 is deposited over the ferroelectric layer to form the top electrode . The conductive layer comprises, for example, noble metal such as Pt , Pd, Au, Ir, or Rh. Other materials such as those used to form the bottom electrode are also useful . The top electrode typically serves as a common electrode, connecting other capacitors in the memory array. The top electrode is patterned as necessary to provide contact openings to the bitlines and wordlines. Another post- deposition heat treatment can be performed after the formation of the conductive layer.
Additional processing is performed to complete the ferroelectric memory IC. Such additional processing is known in the art. For example, the additional processing includes forming support circuitry, contact openings to the bitline, final passivation layer, contact openings in the passivation layer for testing and connecting to lead frame, and packaging.
In accordance with the invention, a Bi-based metal oxide comprising a crystallographic texture which produces a high switchable polarization is provided. The crystallographic texture of the Bi-based metal oxide layer affects the switchable polarization. By orienting the crystallographic texture of the Bi-based metal oxide in the correct direction can increase the switchable polarization.
The amount of polarization that can be switched is related to the cosine of the angle between the direction of the polarization vector in the ferroelectric crystal and the direction of the field applied by the device to switch the polarization. In the case of a parallel plate capacitor, the switching field is applied to the ferroelectric in the direction perpendicular to the conductive top and bottom electrodes . In the case of the ferroelectric transistor, the switching field is applied to the ferroelectric layer in a direction perpendicular to the conductive top or gate electrode. The maximum switchable polarization is obtained when the polarization vector of the ferroelectric crystal is aligned with the applied field as the cosine of 0° gives the maximum value of the cosine, namely, 1.
Referring to Fig. 3, a layered perovskite structure 300 of the ferroelectric SBT is shown. The SBT is expressed by, for example, the formula SrBi2Ta209. The Aurivillius phase of the SBT film comprises negatively charged perovskite layers of Sr and Ta oxide 305 separated by positively charged Bi oxide layers 310. The stoichiometry of the Sr and Ta oxide is for example [SrTa207] 2n"n, and the stoichiometry of the Bi oxide layers is for example [Bi202]2n+ n, creating a structure of alternating [SrTa207] 2π" n and [Bi202] 2n+ n layers.
As shown in Fig. 3, the polarization direction of the SBT is along the a-axis. The b-axis represents a potential polarization direction. The a-axis and b-axis can be interchanged by, for example, a diffusionless transformation between 90° domains of the ferroelectric material. The transformation (poling) occurs with the application of an electric field. The c-axis, on the other hand, is perpendicular to the Bi-oxide layers of the structure. In this direction, little to no switchable polarization can be induced. Accordingly, only crystals of SBT that have a component of the a-axis and/or b-axis in the direction of the field applied by the device for switching will contribute to the switchable polarization.
In accordance with one embodiment of the invention, a Bi-based metal oxide layer comprising a crystallographic texture that produces an increase in the average of the components of the a-axis and/or b-axis of the crystal lattice (i.e., in the direction of the field applied by the device for switching) is provided. Increasing the average of the components of the a-axis and/or b-axis of the crystal lattice in the direction of the field applied by the device for switching increases the switchable polarization of the device incorporating the Bi-based metal oxide. Preferably, the Bi-based metal oxide ceramic comprises a crystallographic texture that maximizes the average of the components of the polarization direction in the direction of the field applied by the device for switching.
We have discovered that the stoichiometry or composition of the Bi-based metal oxide layer affects the crystallographic texture of the layer. In one embodiment of the invention, the composition of the Bi-based metal oxide layer is controlled to produce a crystallographic texture that increases the average of the components of the polarization directions in the direction of the field applied by the device for switching. Preferably, the crystallographic texture of the Bi-based metal oxide comprises an orientation that maximizes the average of the components of the polarization directions in the direction of the field applied by the device for switching. In one embodiment, the crystallographic texture results in an increase in the average of the a-axis and/or b-axis direction in the direction of the field applied by the device for switching.
In one embodiment of the invention, the Bi-based metal oxide layer expressed by YaBibX2Oc. The composition of the YaBibX20c layer is controlled to produce a crystallographic texture that increases the average of the polarization components (which is in the a-axis and/or b-axis direction) in the direction of the field applied by the device for switching. Preferably, the composition of the YaBibX2Oc layer is controlled to produce a crystallographic texture that maximizes the average of the polarization components (which is in the a-axis and/or b-axis direction) in the direction of the field applied by the device for switching.
In one embodiment, the composition of YaBibX2Oc comprises a Y/2X ratio of about 0.5-0.9, preferably about 0.6-0.8, and more preferably 0.7-0.8. The Bi/2X ratio of the Bi-based metal oxide, in one embodiment, is about 2.0-2.6, preferably about 2.1-2.5, and more preferably 2.1-2.3.
In a preferred embodiment, the composition of the Bi-based metal oxide comprising SBT comprises a Sr/2Ta ratio of about 0.5-0.9, preferably about 0.6-0.8, and more preferably 0.7-0.8. The Bi/2Ta ratio of the SBT, in one embodiment, is about 2.0-2.6, preferably about 2.1- 2.5, and more preferably 2.1-2.3.
Decreasing the Sr or Y content of the Bi-based metal oxide produces an increase in the average of the a-axis and/or b-axis in the direction perpendicular to the conductive layer or plates of the capacitor. This result is contrary to conventional teachings. Conventional teachings suggest that decreasing the Sr content of SBT causes an increase in the unpolarizable c-axis orientation. See Hase et al . , Sr Content Dependence of Ferroelectric Properties in SrBi2Ta209 Thin Films," Integrated Ferroelectrics, vol 15, pl27-135 (1997) . Experiments
Numerous SBT films with different compositions were formed on prepared substrates . The substrates included a 625 nm thick layer of thermal silicon oxide with a 10 nm thick Ti layer deposited on the oxide by sputtering at about 450°C. A bottom electrode comprising about 100 nm thick of Pt was formed over the Ti by sputtering at about 190°C.
The SBT films were deposited over the Pt electrode. The precursors employed to form the SBT films were Sr(thd)2, Bi(thd)3, and Ta (thd) (O-I-Pr) 4. The SBT films were deposited amorphously at a temperature of about 380°C and a pressure of about 9torr in an ambient of 60%O2:40%Ar. The gas flow rate was either 1.6 slm or 10 slm for different films. Films were grown to thickness from 150 nm to 200 nm. The deposited SBT films were annealed for about 1 hour in flowing 02 at about 800°C. Pt was e-beam evaporated through a shadow mask to form top electrodes . A second anneal was performed for about 15 minutes in flowing 02 at 800°C.
The SBT films were analyzed to determine the relationship among orientation, composition, and electrical characteristics. Electrical testing was performed in a Radiant RT6000 ferroelectric tester. Composition was measured over 8 mm diameter areas in a Rigaku 3613 X-ray fluorescence spectrometer using Rigaku' s "fundamental parameters" method and standards of MOD films. Texture was estimated from the intensity of different peaks in a symmetric theta-2theta (Bragg- Brantano) geometry in a Rigaku D/maxB goniometer with a curved monochrometer and a Cu X-ray target. The divergent slit was 1°, the receiving slit was 0.3°, and the receiving slit for the monochrometer was 0.6°.
Fig. 4 shows the intensity of the (200)/ (020) peak as a function of composition. The dots indicate the composition of the films that were measured and the contour lines indicate the interpolated intensity as a function of composition. The (200) peak corresponds to the a-axis and the (020) peak corresponds to the b-axis. The (200) and (020) orientations cannot be distinguished in this measurement because their lattice parameters are very close. As the ratio of Sr/2Ta decreases and the Bi/2Ta ratio increases, a (200) orientation is preferred.
Fig. 5 shows the intensity of the (115) peak as a function of composition. The dots indicate the composition of the films that were measured and the contour lines indicate the interpolated intensity as a function of composition. The (115) peak corresponds to components from the a-axis and b-axis. Lower ratios of Sr/2Ta and intermediate Bi/2Ta enhance the preference for (115) orientation.
Fig. 6 shows the intensity of the (00' 10) peak as a function of composition. The dots indicate the composition of the films that were measured and the contour lines indicate the interpolated intensity as a function of composition. The (00' 10) peak corresponds to the c-axis. As can be seen, a lower Sr/2Ta ratio decreases the preference for the (00' 10) orientation.
From Figs. 4-6, it can be seen that the amount of a- axis texture and b-axis texture can be increased almost to the exclusion of measurable c-axis material. As the (00' 10) texture is reduced and the a-axis and b-axis increased, the switchable polarization increases. This demonstrates the relationship between the polarization direction of the crystals and the plates of the capacitor. Furthermore, Figs. 4-6 show that the texture of the film is affected by the composition of the film. As Sr is decreased from the stoichiometric composition of 1.00 to 0.75-0.80, the (OO'IO) peak decreases and the (115) and (200) peaks increase relative to one another. With the Sr/2Ta ratio in the range of about 0.65-0.80 and increasing the Bi/2Ta ratio from about 2.0 to 2.3, the intensity of the (200) peak increases with the (OO'IO) remaining minimal . Fig. 7 shows the correlation between switchable polarization (2Pr) with respect to composition. It can be seen that switchable polarization increases as the ratio of Sr/2Ta decreases to below 0.75 at a Bi/2Ta from about 2.0 to 2.5.
While the invention has been particularly shown and described with reference to various embodiments, it will be recognized by those skilled in the art that modifications and changes may be made to the present invention without departing from the spirit and scope thereof. The scope of the invention should therefore be determined not with reference to the above description but with reference to the appended claims along with their full scope of equivalents.

Claims

What is claimed is:
1. A ferroelectric device comprising: a conductive layer; a Bi-based ferroelectric layer electrically contacting the conductive layer, wherein the Bi-based ferroelectric layer comprises a crystallographic texture which is controlled by the composition of the Bi-based ferroelectric layer.
2. The ferroelectric device of claim 1 wherein the crystallographic texture comprises an orientation that produces high switchable polarization.
3. The ferroelectric device of claim 2 wherein the crystallographic texture of the Bi-based ferroelectric layer is oriented to produce an increase in the average of the components of a polarization direction perpendicular to the conductive layer.
4. The ferroelectric device of claim 2 wherein the crystallographic texture of the Bi-based ferroelectric layer is oriented to maximize the average of the components of a polarization direction perpendicular to the conductive layer.
5. The ferroelectric device of claim 2, 3, or 4 wherein the Bi-based ferroelectric layer is expressed by YaBibX2Oc, where Y comprises a 2-valent cation and X comprises a 5- valent cation.
6. The ferroelectric device of claim 5 wherein:
Y is equal to one or more elements selected from the group comprising Sr, Ba, Pb, and Ca; and
X is equal to one or more elements selected from the group comprising Ta and Nb.
7. The ferroelectric device of claim 6 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.5-0.9.
8. The ferroelectric device of claim 7 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.0-2.6.
9. The ferroelectric device of claim 6 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.6-0.8.
10. The ferroelectric device of claim 9 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.1-2.5.
11. The ferroelectric device of claim 6 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.7-0.8.
12. The ferroelectric device of claim 11 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.1-2.3.
13. The ferroelectric device of claim 5 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.5-0.9.
14. The ferroelectric device of claim 13 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.0-2.6.
15. The ferroelectric device of claim 5 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.6-0.8.
16. The ferroelectric device of claim 15 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.1-2.5.
17. The ferroelectric device of claim 5 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.7-0.8.
18. The ferroelectric device of claim 17 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.1-2.3.
19. The ferroelectric device of claim 5 wherein the Bi- based ferroelectric layer comprises Sr and Ta .
20. The ferroelectric device of claim 19 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.5-0.9.
21. The ferroelectric device of claim 20 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.0-2.6.
22. The ferroelectric device of claim 19 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.6-0.8.
23. The ferroelectric device of claim 22 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.1-2.5.
24. The ferroelectric device of claim 19 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.7-0.8.
25. The ferroelectric device of claim 24 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.1-2.3.
26. The ferroelectric device of claim 19 wherein the Bi- based ferroelectric layer comprises SraBibTa2Oc (SBT) .
27. The ferroelectric device of claim 26 wherein the composition of the Bi-based metal oxide comprises a Sr/2Ta ratio of about 0.5-0.9.
28. The ferroelectric device of claim 27 wherein the composition of the Bi-based metal oxide comprises a Bi/2Ta ratio of about 2.0-2.6.
29. The ferroelectric device of claim 26 wherein the composition of the Bi-based metal oxide comprises a Sr/2Ta ratio of about 0.6-0.8.
30. The ferroelectric device of claim 29 wherein the composition of the Bi-based metal oxide comprises a Bi/2Ta ratio of about 2.1-2.5.
31. The ferroelectric device of claim 26 wherein the composition of the Bi-based metal oxide comprises a Sr/2Ta ratio of about 0.7-0.8.
32. The ferroelectric device of claim 31 wherein the composition of the Bi-based metal oxide comprises a Bi/2Ta ratio of about 2.1-2.3.
33. The ferroelectric device of claim 5 wherein the Bi- based ferroelectric layer comprises an SBT derivative.
34. The ferroelectric device of claim 33 wherein the SBT derivative comprises a Bi-based oxide selected from the group comprising SraBibTa2-xNbxOc (0<x<2) , SraBibNb2Oc,
Sra-xBaxBibTa2-yNbyOc (O≤x≤a, 0≤y≤2) , Sra-xCaxBibTa2-yNbyOc
(O≤x≤a, 0<y≤2) , Sra_xPbxBibTa2-yNbyOc (O≤x≤a, 0≤y≤2) , or
Sra-x-y-zBaxCayPb2BibTa2_pNbpOc (O≤x≤a, O≤y≤a, O≤z≤a, 0≤p≤2 ) .
35. The ferroelectric device of claim 34 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.5-0.9.
36. The ferroelectric device of claim 35 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.0-2.6.
37. The ferroelectric device of claim 34 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.6-0.8.
38. The ferroelectric device of claim 37 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.1-2.5.
39. The ferroelectric device of claim 34 wherein the composition of the Bi-based metal oxide comprises a Y/2X ratio of about 0.7-0.8.
40. The ferroelectric device of claim 39 wherein the composition of the Bi-based metal oxide comprises a Bi/2X ratio of about 2.1-2.3.
41. A process for fabricating a ferroelectric device comprising: depositing a Bi-based ferroelectric layer on a substrate, wherein the crystallographic texture of the Bi-based ferroelectric layer is controlled by its composition.
42. A process for fabricating a ferroelectric capacitor comprising: depositing a first conductive layer; depositing a Bi-based ferroelectric layer on the first conductive layer, wherein the crystallographic texture of the Bi-based ferroelectric layer is controlled by its composition; and depositing a second conductive layer, wherein the first and second conductive layers serve as electrodes for the ferroelectric capacitor.
EP99963947A 1998-11-23 1999-11-22 Textured bi-based oxide ceramic films Withdrawn EP1135797A1 (en)

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