Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B7/00—Radio transmission systems, i.e. using radiation field
  • H04B7/24—Radio transmission systems, i.e. using radiation field for communication between two or more posts
  • H04B7/26—Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile
  • H04B7/2643—Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile using time-division multiple access [TDMA]
  • H04B7/2656—Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile using time-division multiple access [TDMA] for structure of frame, burst
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B7/00—Radio transmission systems, i.e. using radiation field
  • H04B7/24—Radio transmission systems, i.e. using radiation field for communication between two or more posts
  • H04B7/26—Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile
  • H04B7/2615—Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile using hybrid frequency-time division multiple access [FDMA-TDMA]
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
  • H04W88/02—Terminal devices

Definitions

• the field of the present invention relates to methods and apparatus for managing and controlling time slot operations within a system for multiple access communication.
• a variety of techniques are known for allowing multiple users to communicate with one or more fixed stations (i.e., base stations) by making use of shared communication resources.
• multiple access communication systems include various types of cellular telephone networks and local wireless communication systems, such as wireless private branch exchange (PBX) networks.
• PBX wireless private branch exchange
• transmissions from different sources may be distinguished in a variety of manners, such as on the basis of different frequencies, time slots, and/or codes, for example.
• a communication system in which transmissions are distinguished according to the transmission frequency may be referred to as a frequency division multiple access (FDMA) communication system.
• FDMA frequency division multiple access
• FDD frequency division duplex
• a communication system in which transmissions are distinguished according to the relative timing of the transmission may be referred to as a time division multiple access (TDMA) communication system.
• TDMA time division multiple access
• a communication system in which a forward link transmission during one time slot (or time segment) is paired with a reverse link transmission occurring during a different time slot (or time segment) may be referred to as a time division duplex (TDD) communication system.
• a communication system in which transmissions are distinguished according to which code is used to encode the transmission may be referred to as a code division multiple access (CDMA) communication system.
• CDMA code division multiple access
• the data to be transmitted is generally encoded in some fashion, in a manner which causes the signal to be "spread” over a broader frequency range and also typically causes the signal power to decrease as the frequency bandwidth is spread.
• the signal is decoded, which causes it to be "despread” and allows the original data to be recovered.
• Distinct codes can be used to distinguish transmissions, thereby allowing multiple simultaneous communication, albeit over a broader frequency band and generally at a lower power level than "narrowband" FDMA or TDMA systems. Different users may thereby transmit simultaneously over the same frequency without necessarily interfering with one another.
• a GSM system may be viewed as a “hybrid” communication system utilizing aspects of both FDD and TDMA.
• TDMA or TDD In communication systems employing aspects of TDMA or TDD, including "hybrid" type systems, management of slot-related operations and forward and reverse links by a user station can be challenging, due in part to timing and synchronization constraints.
• the user station may need to precisely control its reception frame window and its transmission frame window in relation to the time frame established by the base station.
• the user station may also need to process received data (for, e.g., decoding or correcting/processing) while at the same time, or immediately thereafter, having to transmit data in return to the base station.
• the bursty nature of packetized TDMA or TDD communications may lead to particular difficulties at the user station in handling data.
• bearer or voice data may need to be broken into a number of data packets to be transmitted over several or possibly many time frames, depending on the amount of data to be transmitted, and similarly may need to be reconstructed from data packets received from the base station over several or possibly many time frames.
• the data may also need to be processed by encoding or decoding algorithms (e.g., vocoding) after being received or before being transmitted, as well as processed for errors, therefore adding to the complexity of control operations at the user station.
• a user station may need to have provision for handling different message types, such as signalling (i.e., control) traffic messages as well as normal bearer traffic messages.
• the user station may need the ability to exchange signalling traffic messages in order to establish communication or handoff to another base station.
• the user station hardware interface may need to respond rapidly and efficiently to instructions revealed through signalling messages from the base station
• it may be desirable to support advanced protocol features, such as super-rate or sub-rate communication, at the user station.
• advanced protocol features such as super-rate or sub-rate communication, at the user station.
• the radio at the user station may need to be reconfigured periodically to switch between receive and transmit frequencies. The radio reconfiguration may need to occur simultaneous with processing of data just received or about to be transmitted.
• the user station may also need to control the radio as to allow monitoring of neighboring base stations and handover when needed.
• a user station having advanced protocol capabilities, and having, for example, the ability to transmit and/or receive at super-rates or sub-rates. It would also be advantageous to provide a user station control system capable of managing time slots and peripheral activities associated with communication in a TDMA or TDD environment, in addition to dynamic radio reconfiguration to support different communication environments and protocols (e.g., FDD or FDMA) and to support handover between base stations.
• a user station control system comprises an event-driven architecture utilizing interrupts to communicate with and/or to initiate action by a microcontroller.
• the microcontroller responds to such interrupts by transferring data to or from various hardware components, such as transmit and receive frame memory buffers, a digital signal processor (DSP) and vocoder, and a radio channel.
• DSP digital signal processor
• the microcontroller responds to a variety of interrupts, each of which requests the transfer of a discrete amount (e.g., a single byte) of data.
• a user station control system comprises a variety of software components for managing and controlling time slot operations.
• the user station control system may comprise a slot manager for setting up time slots, and for maintaining active time slots in a list or queue format.
• the user station control system may further comprise an over-the-air (OTA) driver for interfacing with various hardware components (e.g., a DSP/vocoder) and also for instructing the slot manager when to add, update or delete active time slots from the time slot list or queue.
• OTA over-the-air
• the slot manager and OTA driver may communicate via slot message queues.
• the user station control system also preferably comprises a variety of direct memory access data transfer tasks, which allow access to hardware registers and transference of data between various hardware sources and destinations.
• the user station control system may comprise components for radio reconfiguration, ARQ processing and power control processing.
• a microcontroller is programmed in accordance with algorithms for controlling and managing time slot operations in a user station.
• a control ASIC interfaces with the microcontroller, and provides an interface to various hardware components including, for example, a program memory, random-access memory, DSP/vocoder, linearizer and radio.
• the microcontroller may comprise a peripheral event controller which responds to interrupts received from the control ASIC.
• the microcontroller may instruct the control ASIC as to a predefined amount of data (e.g., number of bytes) to be transferred between hardware components, and the control ASIC may then, for each byte to be transferred, interrupt the peripheral event controller of the microcontroller to initiate a direct transfer of the data.
• a user station control system to manage time slot operations, wherein a user station is capable of communicating with more than one base station at the same time.
• the user station control system preferably maintains, in the form of a slot object, a discrete data profile for each time slot or related group of time slots, and dynamically re-configures the user station radio (including its operative frequency, if applicable) to transmit or receive according to the data profile for the current time slot.
• the control and/or configuration parameters for the next time slot are loaded.
• Each time slot preferably includes within its data profile an indicator (i.e., pointer) identifying the next active time slot.
• a slot object may be added for each active communication channel (whether signalling, voice or other data), and may be deleted when the communication channel is closed down.
• the user station control system provides a capability for the user station to handoff from one base station to another, or monitor nearby base stations, by providing the ability for the user station to communicate contemporaneously (in different time slots of the same time frame) with different base stations.
• a user station control system for managing time slot operations within a TDMA or TDD communication system (and/or FDD or FDMA communication system) provides GSM functionality by interfacing with a subscriber identity module (SIM) card located within the user station.
• SIM subscriber identity module
• the user station control system may comprise a control ASIC which provides an interface between a microcontroller and the SIM card.
• FIG. 1 is a diagram of a cellular system.
• Fig. 2 is an abstract diagram of components of a preferred software system and their associated interfaces, in accordance with various aspects of the present invention.
• Fig. 3 is a block diagram of a user station or handset in which the invention may be employed.
• Fig. 4 is a diagram of a frame structure for FDD communication between a base station and multiple user stations.
• Figs. 5 and 6 are diagrams of alternative frame structures for FDD communication between a base station and multiple user stations.
• Fig. 7 is a diagram of a process flow for controlling a user station.
• Fig. 8 is a data path diagram illustrating the flow of signalling traffic in accordance with a preferred embodiment of a user station.
• Fig. 9 is a timing diagram illustrating timing and sequencing for signalling traffic.
• Fig. 10 is a data path diagram illustrating the flow of voice or bearer traffic in accordance with a preferred embodiment of a user station.
• Fig. 11 is a timing diagram illustrating timing and sequencing for voice or bearer traffic.
• Fig. 12 is a timing diagram illustrating slot object access control.
• Fig. 13 is a timing diagram depicting a slot interrupt sequence.
• Fig. 14 is a table diagram for automatic repeat request (ARQ) states.
• Fig. 15 is a top-level system diagram of a preferred control section for a user station in accordance with certain aspects of the invention as described herein.
• Fig. 16 is a diagram of a preferred system memory map.
• Fig. 17 is a diagram of a memory map for volatile memory space.
• Fig. 18 is a diagram of a transmit/receive frame memory structure.
• Fig. 19 is an example illustrating a relationship between slot objects and time slots.
• FIG. 1 is a diagram of a cellular communication system 101 having base stations and user stations.
• a communication system 101 for communication among a plurality of user stations 102 includes a plurality of cells 103, each with a base station 104, typically located at or near the center of the cell 103.
• Each station (both the base stations 104 and the user stations 102) may generally comprise a receiver and a transmitter.
• the user stations 102 and base stations 104 preferably communicate using frequency division duplex (FDD) techniques as further described herein, in which base stations 104 communicate over one frequency band and user stations 102 communicate over another frequency band. Communication is also preferably conducted such that different user stations 102 transmit at different times (i.e., during different time slots), as further described herein.
• FDD frequency division duplex
• the communication system 101 may also comprise a base station controller 105 which connects to the base stations 104 in a particular geographic region.
• the base station controller 105 aggregates inputs from multiple base stations 104 and relays information from the base stations 104 to a mobile switching center (MSC) (not shown) and ultimately to a public switched telephone network (PSTN, or "network”) (not shown).
• the base station controller 105 also relays information from the network to the individual base stations 104.
• the base station controller 105 may, if necessary, perform conversion of signalling messages relating to, e.g., mobility management and call control, to make the signalling messages compatible with the communication protocol used by the base stations 104.
• a wireless communication system includes a frame structure according to which transmissions to and from user stations are distinguished based on time (i.e., TDMA or TDD), and according to which base station transmissions are transmitted on a different frequency band than user station transmissions (i.e., FDMA or FDD).
• TDMA time
• FDMA frequency band than user station transmissions
• An exemplary frame structure which may be utilized in such a wireless communication system is shown in Fig. 4, and described below. Examples of alternative frame structures are shown in Figs. 5 and 6, and are described hereinafter. However, other frame structures besides those shown in Figs. 4, 5 and 6 can be used in conjunction with the inventive features described herein.
• a repeating time frame 402 comprises a plurality of time slots 403, each of the time slots 403 having a first time segment 417 and a second time segment 418.
• the time slots 403 can be defined on multiple frequency bands 411, 412, in order to effectuate FDD or FDMA communication. Accordingly, the time slots 403 can be broken down into base transmit time slots 405 with respect to a base transmission frequency band 411, and user transmit time slots 406 with respect to a user transmission frequency band 412.
• Each of the base transmit time slots 405 is preferably paired with a corresponding one of the user transmit time slots 406, with such a pair defining a duplex channel for communication (up to N total duplex channels).
• the N duplex channels may be assigned, on demand, to user stations 102.
• the number of time slots 403 in a time frame 402 is sixteen, and the number of base transmit time slots 405 and user transmit time slots 406 is likewise sixteen. Also in a preferred embodiment, the pairing between base transmit time slots 405 and user transmit time slots 406 is made such that each user transmit time slot 406 is paired with a base transmit time slot 405 that occurs eight time slots later (i.e., one- half of time frame 402).
• the user stations 102 preferably transmit in the first time segment 417 of the user transmit time slots 406, while the base station 104 preferably transmits in the second time segment 418 of the base transmit time slots 405.
• a user station 102 to which the duplex channel is assigned transmits a user station message to the base station 104
• the base station 104 transmits a base station message to the user station 102 to which the duplex channel is assigned.
• the frame structure 401 is designed in one regard to allow relatively convenient adaptation of TDD equipment to perform FDD functionality. Consequently, the base station messages and user station messages are separated in time (i.e., user stations 102 transmit during the first time segments 417 of time slots 403 while the base station 104 transmits in the second time segments 418 of time slots 403) even though time separation would not be necessary to avoid interference because the base station messages and user station messages are also separated by frequency.
• the frame structure 401 is advantageous when converting a TDD base station using a single frequency band for both base and user transmissions to a base station employing FDD, because the adapted base station can maintain the same relative timing between user transmit time segments and base transmit time segments in each time slot while having only to switch frequencies between the first time segment 417 and the second time segment 418 in each time slot 403. Consequently, for the frame structure 401 of Fig. 4, the base station 104 need not have the capability of transmitting and receiving simultaneously over two different frequency bands, and does not need, for example, a diplexer.
• __ While preferred embodiments of the invention are described below in relation to the frame structure 401 shown in Fig. 4, alternative frame structures are introduced here which could also be used in conjunction with the inventive features and processes disclosed herein.
• a repeating time frame 502 comprises a plurality of time slots 503, which may be broken down, similar to Fig. 4, as base transmit time slots 505 with respect to a base transmission frequency band 511 and user transmit time slots 506 with respect to a user transmission frequency band 512.
• Each of the base transmit time slots 505 is preferably paired with a corresponding one of the user transmit time slots 506, with such a pair defining a duplex channel for communication (up to N total duplex channels).
• the time slots 503 are not divided into a first time segment and second time segment.
• the user station 102 to which the duplex channel is assigned transmits a user station message to the base station 104 over the user transmission frequency band 512
• the base station 104 transmits a base transmit message to the user station 102 to which the duplex channel is assigned over the base transmission frequency band 511.
• the base station 104 thereby carries out multiple access communication with a plurality of user stations 102.
• the base station 104 communicates with up to N user stations 102 in the N time slots 503 of time frame 502, unless more than one of the time slots (user time slots 506 or base time slots 505, or both) are aggregated to a single user station 102, or else more than one user station 102 is assigned to share a single time slot 503 by communicating during alternate time frames 502.
• the frame structure 501 is advantageous in that it can support twice as many user stations 102 as the frame structure 401, all other things being equal, but requires that the base station 104 be able to transmit and receive simultaneously over two different frequency bands 511, 512, unlike the frame structure 401 of Fig. 4.
• the alternative frame structure 602 shown in Fig. 6 is, like that of Fig. 4, one in which the base station 104 need not be able to transmit and receive simultaneously over two different frequency bands.
• a repeating time frame 602 comprises a plurality of base transmit time slots 605 and a plurality of user transmit time slots 606.
• Each of the base transmit time slots 605 is preferably paired with a corresponding one of the user transmit time slots 606, with such a pair defining a duplex channel for communication (up to N total duplex channels).
• the base station 104 transmits over a base transmission frequency band 611 in each of the base transmit time slot 605 in succession.
• the first half 602a of the time frame 602 is “dark” or unused.
• the user stations 102 transmit in succession over the user transmission frequency band 612.
• the second half 602b of the time frame 602 is "dark" or unused.
• the base transmit time slots 605 are paired with user transmit time slots 606 in the same relative sequential order, so that the first base transmit time slot 605 is paired with the first user transmit time slot 606, the second base transmit time slot 605 is paired with the second user transmit time slot 606, and so on.
• each base transmit time slot 605 is paired with a user transmit time slot 606 separated from it by one-half of the time frame 602.
• communication may be established between a base station 104 and a user station 102 by any suitable means, including the methods and techniques described in, for example, U.S. Patent Application Ser. No. 08/284,053 filed August 30, 1994, assigned to the assignee of the present invention, and hereby incorporated by reference as if set forth fully herein.
• a base station 104 transmits a "general poll" message in each time slot which is available for communication.
• a user station 102 desiring to establish communication with the base station 104 responds to one of the general poll messages by transmitting a general response message to the base station 104, preferably in the same time slot (or the user transmit time slot corresponding to the base transmit time slot) in which the general poll message was transmitted.
• the user station 102 transmits a user station identifier.
• the base station 104 Upon receipt of the general response message, the base station 104 transmits a specific poll message to the user station 102, preferably in the same time slot as the general poll message was transmitted.
• the user station 102 may transmit a specific response message, or else may commence communication in the appropriate time slot.
• a user station 102 may handoff communication to a base station 104 by first establishing communication with a new base station 104, requesting a circuit switch to the new base station 104, and then relinquishing the original link.
• the user station 102 may monitor the quality of signals received from other local base stations 104 and, when it appears that a handoff is desirable, establish a communication link with a new base station 104 by responding to a general poll message in an available time slot at the new base station 104.
• the user station 104 instructs the old base station 104 to switch over the circuits for the call, and then terminates the communication link with the old base station 104.
• the user station 102 maintains two separate links in two separate time slots, and potentially on different frequencies and/or with different code sets.
• the user station 301 includes a radio transceiver 305 (comprising a transmitter 315 and a receiver 316), an antenna 306 connected to the radio transceiver 305, and an over-the-air controller 310 also connected to the radio transceiver 305.
• the over-the-air controller 310 is connected to a memory buffer 311.
• the over-the-air controller 310 manages the retrieval of information from the memory buffer 311 by the radio transceiver 305 for transmission to the base station 104 with which the user station 301 communicates, and the storage of information into the memory buffer 311 by the radio transceiver 305 when such information is received from the base station 104.
• the memory buffer 311 is connected to an analog-to-digital (A/D) converter 331 and a digital-to-analog (D/A) converter 332. Both the A/D converter 331 and the D/A converter 332 are connected to a vocoder 335, which is connected to a speaker/microphone 336. Information received from the base station 104 and stored in the memory buffer 311 is converted from a digital format to an analog format by D/A converter 332. The vocoder 335 then processes the analog formatted information and sends a signal to speaker/microphone 336 to generate audible voice or other sounds to the user/listener.
• A/D analog-to-digital
• D/A converter 332 digital-to-analog converter 332
• the speaker/microphone 336 also picks up audible voice or other sounds from the user, and relays an analog data signal to the vocoder 335.
• the vocoder 335 processes the analog data signal, and sends the processed analog data signal to A/D converter 331 for conversion to a digital format.
• the digital formatted data is then stored in the memory buffer 311, and made available for transmission to the base station 104 in the appropriate time slot.
• FIG. 3 also shows further details of the over-the-air controller 310.
• the over-the-air controller 310 comprises a clock 320 connected to a time frame counter 321 and a time slot counter 322.
• the time frame counter 321 and time slot counter 322 are connected to control logic 323, which uses outputs from the time frame counter 321 and time slot counter 322 to format messages for over-the-air communication.
• the radio transceiver 305 Under control of the over-the-air controller 310, stores and removes information from the memory buffer 311.
• the radio transceiver 305 further comprises a transmit/receive (T/R) switch 317 to allow selection between a transmission mode and a reception mode.
• T/R transmit/receive
• the control logic 323 of the over-the-air controller 310 controls the T/R switch 317, and thereby selects between the transmission mode and reception mode based, for example, upon the current portion of a time frame (such as time frame 401 described elsewhere herein).
• the over-the-air controller 310 selects the user transmit frequency (e.g., user transmission frequency band 412), and when in a reception mode the over-the-air controller 310 selects the base transmit frequency (e.g., base transmission frequency band 411).
• control logic 323 comprises a microcontroller or microprocessor 327 (such as a Siemens C163/C165 processor) and a control ASIC 328 (referred to herein occasionally as the "MSCA").
• the MSCA 328 may provide an interface between the microprocessor 327 and many of the other hardware components in the user station 301, including the radio transceiver 305 and the speaker/microphone 336, as well as a coder/decoder (CODEC) and digital signal processing circuitry.
• CDODEC coder/decoder
• the MSCA 328 may comprise a variety of general and special purpose registers in order to facilitate performance of its various functions. Examples of such registers may include the following:
• the microcontroller comprises a peripheral event controller (PEC), which receives occasional interrupts from the MSCA 328 for data transfer or similar tasks.
• PEC peripheral event controller
• a radio transceiver control process preferably provides coordinated updates of all registers of the MSCA 328 and signals that are involved in over-the-air or slot-dependent operations.
• control section 1501 of a user station or handset in accordance with a preferred embodiment are shown in Fig. 15.
• the control section 1501 comprises an over-the-air line card assembly (OTA LCA) 1502 comprising controller logic 1503 and radio interface logic 1504.
• the controller logic 1503 may comprise a control ASIC 1591 (similar in general function to control ASIC 328 of Fig. 3).
• the OTA LCA 1502 is connected to a microcontroller 1505 (e.g., a Siemens SABC-165 microcontroller).
• the microcontroller 1505 comprises, among other things, a microprocessor and one or more serial ports (at least one of which is a high speed synchronous serial port).
• the OTA LCA 1502 and microcontroller 1505 are connected by a set of control lines 1561, including an interrupt link 1542, a control link 1543, a clock signal line 1544, and a set of chip select (CS) lines 1545.
• the OTA LCA 1502 provides a control interface between the radio transceiver 305 (see Fig. 3) and the microcontroller 1505.
• the microcontroller 1505 can move data to and from the OTA LCA 1502, read the status of the OCA LCA 1502, and/or issue commands to the OTA LCA 1502 instructing it to perform certain predefined actions.
• a system bus 1530 connects the OTA LCA
• the system bus is also connected to a static RAM (SRAM) 1524 and a flash memory 1525.
• SRAM static RAM
• the SRAM 1524 may, for example, be 128k in size (8-bit words), and the flash memory 1525 may, for example, be 256k in size (16-bit words).
• the controller logic 1503 of the OTA LCA 1502 is connected to a keypad 1523, a battery monitor 1522, a digital signal processor/vocoder (DSP/vocoder) 1510 and a linearizer ASIC 1513. Both the controller logic 1503 and the radio interface logic 1504 are connected to a radio interface ASIC 1514, and thereby to the radio transceiver (such as radio transceiver 305 shown in Fig. 3).
• the controller logic 1503 of the OTA LCA 1502 is connected to a keypad 1523, a battery monitor 1522, a digital signal processor/vocoder (DSP/vocoder) 1510 and a linearizer ASIC 1513.
• DSP/vocoder digital signal processor/vocoder
• Both the controller logic 1503 and the radio interface logic 1504 are connected to a radio interface ASIC 1514, and thereby to the radio transceiver (such as radio transceiver 305 shown in Fig. 3).
• SIM 1503 of the OTA LCA 1502 is also preferably connected via a SIM link 1533 to a SIM port 1520, which is coupled to a subscriber identity module (SIM) card (not shown).
• SIM subscriber identity module
• the SIM card is utilized to perform a number of GSM-related and user environment functions. Examples of such include provision of system security and storage of subscriber-specific information, including such things as subscriber authentication information and subscriber-specific data.
• the SIM port 1520 is also connected over a status signal line 1534 to the microcontroller 1505.
• the microcontroller 1505 is additionally connected to a liquid crystal display (LCD) controller 1512, which acts as the interface between the microcontroller 1505 and a visual display (not shown).
• the microcontroller 1505 is further connected to a data services port 1521, which can be used for downloading software, or testing and debugging.
• the data services port 1521 may comprise an asynchronous/synchronous serial interface port operable in two different modes, and which may be alternately connected to an RS232 port for code download, or directly to the asynchronous USART port of the microcontroller 1505.
• Figure 16 depicts a system memory map associated with the control section 1501 shown in Fig. 15.
• the system memory 1601 is divided into an imaged memory portion 1602 and a non-imaged memory portion 1603.
• the entirety of the imaged memory portion 1602 may be contained within the same segment of the system memory 1601 (e.g., segment 0).
• the imaged memory portion 1602 comprises one or more flash memory sections 1611, 1612 and 1613 (associated with the flash memory 1525 shown in Fig. 15), an SRAM section 1614 (associated with SRAM 1524 shown in Fig. 15), an internal RAM section 1627 (associated with a random-access memory or cache internal to the microcontroller 1505 shown in Fig.
• the "boot up" code for the microcontroller 1505 may be located in the first (i.e., lowest) flash memory section 1611.
• memory needed in certain direct memory access (DMA) operations is preferably imaged into segment 0 according to the above structure.
• the imaged memory portion 1603 in the embodiment shown in Fig. 16 comprises a flash memory section 1618, an SRAM section 1619, a prototype SRAM section 1620 and a prototype flash memory section 1621.
• the prototype SRAM section 1620 and prototype flash memory section 1621 are intended to assist in code development, and may require the use of additional chip select signal lines.
• Figure 17 is a diagram further detailing the SRAM memory map 1701. As shown in Fig. 17, the SRAM is divided into a plurality of general software regions 1702, 1709 and 1710, a base/frequency map 1703, and a plurality of various buffers including a command buffer 1704, SIM buffer 1705, receive buffer 1706, transmit buffer 1707, and linearizer buffer 1708.
• the transmit buffer 1707 and receive buffer 1706 are generally utilized by the radio transceiver 305 (see Fig. 3)
• the linearizer buffer 1708 is generally utilized by the linearizer ASIC 1513
• the SIM buffer is generally utilized by the SIM card (connected via SIM port 1520).
• a data message storage block 1801 comprises a header field 1808, a D-channel field 1807, a bearer data field 1806, and a vocoder control field 1805, and may also comprise a reserved portion 1804.
• the header field 1808 comprises 17 bits (for a message to be transmitted) or 23 bits (for a received message) of information
• the D-channel field 1807 comprises one byte of information
• the bearer data field 1806 comprises 24 bytes of information
• the vocoder control field 1805 comprises ten bytes of information.
• the control section 1501 provides an interrupt-driven architecture for controlling communication transactions. Events which occur external to the microcontroller 1505 are known as peripheral events, and may cause interrupts. These interrupts are typically generated by the OTA LCA 1502 and coupled to the microcontroller 1505 across the interrupt link 1542.
• the microcontroller 1505 preferably includes internal circuitry, specifically a peripheral event controller (PEC) for handling such interrupts.
• PEC peripheral event controller
• the interrupts caused by peripheral events may cause the peripheral event controller to initiate data moves.
• the peripheral event controller may respond to an interrupt by performing a DMA-type byte transfer over the system bus 1530. Different applications may require more than one byte of data.
• a separate interrupt is used for each byte of data to be transferred (e.g., 20 bytes of data requires 20 individual interrupt requests).
• the number of data transfers needed for a particular application (and hence the number of interrupts) is preferably known in advance by the software and is based on the type of interrupt. After the required number of bytes have been moved, the microcontroller 1505 vectors to the appropriate interrupt service routine.
• the OTA LCA 1502 may include an interrupt state machine for handling event signals and generating interrupts as necessary. If the microcontroller 1505 is asleep or in a power down mode when an interrupt occurs, the interrupt state machine may instruct the clock circuit (for a sleep or power down mode) and/or reset circuit (for a power down mode) to revive the microcontroller 1505. Once the interrupt state machine sees a response from the reset and/or clock circuit indicating that the microcontroller 1505 is fully operational, the interrupt state machine applies the interrupt to the microcontroller 1505.
• the interrupt state machine will present all the interrupts that have been thus far requested. For example, if an initial PEC interrupt request originates from a SIM receive process while the microcontroller 1505 was asleep or in power down, and during the time that the microcontroller 1505 is being revived another PEC interrupt request is received from a different source, both interrupt requests are presented to the microcontroller 1505 at the same time. As each interrupt request is serviced, the request is cleared. Only when all interrupt requests presented to the microcontroller 1505 have been serviced is the state machine able to process a new request.
• the types of peripheral event interrupts are given by Table 1-1 below.
• the peripheral event interrupts may be asserted by application of a high pulse to an assigned input pin of the microcontroller 1505 (e.g., pins EXOIN - EX7IN and pin T2IN of the Siemens SABC-165 microcontroller).
• an assigned input pin of the microcontroller 1505 e.g., pins EXOIN - EX7IN and pin T2IN of the Siemens SABC-165 microcontroller.
• peripheral event interrupts may be explained in more detail as follows.
• the OTA LCA 1502 When the OTA LCA 1502 is in need of data to transmit, it asserts a type 1 interrupt (according to Table 1-1), and the microcontroller 1505 responds with an operation including the steps of reading data from the SRAM transmit buffer 1707 (see Fig. 17) and writing the data to the OTA LCA transmit register (OEOIOH). The data is thereafter transferred to the radio transceiver 305 (see Fig. 3) at the appropriate time for transmission.
• the OTA LCA 1502 asserts a type 2 interrupt (according to Table 1-1) to request that data in the OTA LCA receive register (0E011H) be placed into the receive SRAM receive buffer 1706 (see Fig. 17).
• the microcontroller 1505 responds with an operation including the steps reading the data from the OTA LCA receive register and writing the data to the SRAM receive buffer 1706.
• a type 3 interrupt and type 7 interrupt are used in conjunction with various actions performed by or in relation to the DSP/vocoder 1510.
• the DSP/vocoder 1510 encodes data to be transmitted and decodes received data.
• encoded data is transferred from the DSP/vocoder 1510 to the OTA LCA 1502 at certain time intervals.
• the microcontroller 1510 transfers the data from the OTA LCA encoded data register (0E012H) to the SRAM transmit buffer 1707 for transmission at a later time.
• a type 7 interrupt is used in conjunction with the receipt of data and the transfer of that data to the DSP/vocoder 1510.
• the DSP/vocoder 1510 expects control information to follow the transmission of bearer information.
• the OTA LCA 1502 asserts a type 7 interrupt.
• the microcontroller 1505 writes a byte of DSP/vocoder data or control information from the SRAM receive buffer 1706 to the DSP data/control bytes register (0E013H). This process may be repeated as necessary until all the pertinent data has been transferred to the DSP/vocoder 1510.
• a type 4 interrupt is used in conjunction with activities performed by or in relation to the SIM card connected to the SIM port 1520.
• data is moved from the SIM buffer 1705 in the SRAM 1701 to the SIM transmit register (0E006H) within the OTA LCA 1502 in response to assertion of a type 4 interrupt.
• the OTA LCA 1502 asserts the type 4 interrupt to ensure a continuous flow of data to the SIM card.
• the SIM card receives all of its command and data information, it responds with output data for further processing by the microcontroller 1505.
• the SIM output data is moved from the SIM transmit register (0E006H) to the SIM buffer 1705 also through a type 4 interrupt.
• the microcontroller 1505 preferably takes account of the current state of the SIM card to determine the source and destination of data, as the type 4 interrupt can have more than one effect depending upon the state of the SIM card.
• a type 5 interrupt may be used to send commands to the linearizer ASIC 1513.
• the microcontroller 1505 sends a command to the linearizer ASIC 1513 by writing a command word to the linearizer command/data location (address 0E019H) in the peripheral address map.
• the linearizer state machine will begin to transfer data to the linearizer ASIC 1513.
• the linearizer state machine will make supplementary requests for data as each byte is sent out.
• the microcontroller 1505 may keep track of the number of bytes sent to the linearizer ASIC 1513.
• a type 6 interrupt is utilized during the course of receiving data, to pre-validate and/or pre-process the received data prior to the completion of an entire frame of data.
• the microcontroller 1505 constructs a set of command templates and masks, placed in the SRAM command buffer 1704, for the information it expects to see with each reception.
• a compare state machine within the OTA LCA 1502 asserts the type 6 interrupt twice for each comparison operation, a first time to retrieve a byte of the command template from the SRAM command buffer 1704 and a second time to retrieve a corresponding mask byte from the SRAM command buffer 1704.
• the compare state machine retrieves a command template byte and mask byte (i.e., a command/mask pair) from the SRAM command buffer 1704, and attempts to validate the incoming command. Further details of this process are described later herein.
• a type 8 interrupt allows the microcontroller 1505 to change operative radio frequencies.
• the radio configuration data (e.g., frequency and code set, if applicable) is stored in the flash memory 1525, and is transferred to the RIF ASIC 1514 by transfer of a special command code (referred to as RFLOAD) written by the microcontroller 1505 to the radio configuration/slot map data register (0E002H) of the OTA LCA 1502.
• RFLOAD command code governs what type of radio configuration data is to be transferred to the RIF ASIC 1514.
• the OTA LCA 1502 receives the RFLOAD command, it asserts a type 8 interrupt to initiate transfer of the radio configuration data to the RIF ASIC 1514.
• a type 9 interrupt is used by the OTA LCA 1502 to inform the microcontroller 1505 of an error of the end of the operation.
• the microcontroller 1505 responds to a type 9 interrupt by reading the general status register to determine the source of the error, if any.
• control section 1501 assists in the transmission and reception of data by a user station 102 or 301 within a multiple access communication system.
• the control section 1501 preferably operates according to a frame structure such as disclosed in Figs. 4, 5 or 6 herein, but may also be useful with a wide variety of alternative frame structures.
• Information is passed to and from the radio transceiver 305 (see Fig. 3) across the radio link 1590 shown in Fig. 15.
• the information is processed, as hereafter described, by the RIF ASIC 1514 and OTA LCA 1502, under control of the microcontroller 1505, and transferred to and from the DSP/vocoder 1510 and the CODEC 1511.
• the DSP/vocoder 1510 may incorporate vocoder functionality, and may provide voice data to and remove voice data from the CODEC 1511 according to an applicable sub-rate speech coder algorithm.
• Noice data may be formatted as 64K ⁇ -law pulse-coded modulated (PCM) data.
• the CODEC 1511 provides an interface between the digital circuitry of the control section 1501 and the analog circuitry of the end application (e.g., speaker/microphone 336, as shown in Fig. 3).
• the CODEC 1511 may operate at any suitable frequency, such as 2.048 MHz, and may be synchronized to the master radio clock at an 8 KHz rate.
• a frame sync clock may also be provided to the CODEC 1511.
• the frame sync clock may be any suitable frequency, such as 8 KHz, and may also be synchronized to the master radio clock.
• a presently preferred CODEC 1511 is commercially available from Texas Instruments, under the product name TLV320AC36IPT.
• a presently preferred DSP/vocoder 1510 is also commercially available from Texas Instruments, under the product name TMS320LC53SPZ57.
• the compressed data created by the DSP/vocoder 1510 is stored, via the OTA LCA 1502, in the SRAM transmit buffer 1707 prior to transmission to the base station 104.
• the OTA LCA 1502 begins requesting data from the DSP/vocoder 1510, which responds with a serial stream of data over the serial link 1540.
• the DSP/vocoder 1510 may provide a single byte per request from the OTA LCA 1502, and when the data is received by the OTA LCA 1502, a PEC interrupt (i.e., a type 3 interrupt as defined herein) is asserted by the OTA LCA 1502.
• the microcontroller 1505 writes the data to the SRAM transmit buffer 1707.
• an entire frame of data including bearer (e.g., voice) data and status bytes, will be moved from the DSP/vocoder 1510 into the SRAM transmit buffer 1707 before the transmit frame starts.
• the OTA LCA 1502 After the transmit frame starts, the OTA LCA 1502 asserts a type 1 interrupt (as defined later herein) to request a byte of encoded data from the SRAM transmit buffer 1707. In response, the microcontroller 1505 transfers the encoded (voice) data from the SRAM transmit buffer 1707 to the OTA LCA 1502. The OTA LCA 1502 continues to request encoded data in the same manner until the entire transmit frame is sent.
• a type 1 interrupt as defined later herein
• Received data in compressed form is sent, via the OTA LCA 1502, to the DSP/vocoder 1510 for decompression.
• the received data is first stored in the SRAM receive buffer 1706, then transferred out of the receive buffer 1706 by the OTA LCA 1502.
• the OTA LCA 1502 Prior to receiving the first byte of compressed bearer (e.g., voice) data, the OTA LCA 1502 writes the sync bytes to the DSP/vocoder 1510.
• the sync bytes may be stored within the OTA LCA 1502 and transferred to the DSP/vocoder 1510 without intervention by the microcontroller 1505.
• As data is received over the radio link 1590 from the radio transceiver 305 (see Fig. 3), it is stored temporarily in the OTA LCA 1502.
• a PEC interrupt i.e., type 2 interrupt as defined herein
• the microcontroller 1505 transfers the byte of data in the SRAM receive buffer 1706.
• bearer e.g., voice
• the OTA LCA 1502 After receipt of the bearer data is complete, the OTA LCA 1502 generates an interrupt to the microcontroller 1505 requesting the receipt of control bytes for the DSP/vocoder 1510.
• the microcontroller 1505 transfers the control data to the OTA LCA 1502, which transfers the control data serially to the DSP/vocoder 1510.
• the microcontroller 1505 constructs a set of command templates and masks for those commands that it expects to see with each receive frame.
• the set of command templates and masks are temporarily stored in the SRAM command buffer 1704. If the user station 301 is monitoring more than one time slot, then a separate area may be set up within the SRAM command buffer 1704 for each time slot that the user station 301 is monitoring.
• a single command template and mask together comprise a command/mask pair.
• the command template of the command/mask pair represents a command (or data) that the microcontroller 1505 expects to see in the next receive frame.
• the command template is compared against one or more command bytes after they are received as part of the receive frame.
• the number of command bytes to compare is controlled by a compare count command communicated to the OTA LCA 1502 from the microcontroller 1505.
• the mask of the command/mask pair provides the ability to ignore certain selected bits of the command template in the comparison operation. For example, in one embodiment, any mask bit of the mask that contains a logical "0" causes the corresponding bit of the command template to be excluded from the compare operation and not affect the outcome.
• the microcontroller 1505 then writes a compare count value to the Compare Count register within the OTA LCA 1502.
• the compare count value indicates how many control bytes are to be compared, including header bytes.
• the compare count value consequently will ordinarily be equal to at least the number of header bytes (e.g., three bytes, in a preferred embodiment).
• a compare state machine within the OTA LCA 1502 reads the compare count value and loads it into a decrementing register in preparation for the series of command compares.
• the compare state machine then asserts an interrupt (i.e., a type 6 interrupt as defined herein) twice for each comparison operation, once to retrieve a command template byte from the SRAM command buffer 1704 and a second time to retrieve a corresponding mask byte from the SRAM command buffer 1704.
• an interrupt i.e., a type 6 interrupt as defined herein
• the compare state machine uses two interrupts to retrieve a command template byte and mask byte (i.e., a command/mask pair) from the SRAM command buffer 1704.
• the decrementing register i.e., the Compare Counter
• the compare process terminates; however, the Compare Counter continues to decrement with each received byte.
• the interrupt control register is tested to determine if an interrupt should be issued; if so, a general interrupt may be issued and the compare complete bit will be set. Interrupts may be set to issue at the end of a receive frame and/or at the end of a compare operation.
• the OTA LCA 1502 will proceed with transferring data to the DSP/vocoder 1510 and SRAM 1524.
• RSSI information is preferably generated regardless of when an interrupt is issued and regardless of the outcome of the compare sequence, so as to allow the user station 301 to search for better time slots or a better base station 104 for communication based on signal strength measurements. If a bad comparison with the compare/mask pair occurs after the first byte but before the Compare Counter reaches zero, the PEC interrupts used for storing data in the SRAM command buffer 1704 are discontinued to save power. When the Compare Counter reaches zero, the entire receive frame is stored in the SRAM receive buffer 1706.
• a message from the base station 104 comprises a first header byte comprising a field indicating the packet type (e.g., general poll message, specific poll message, or other type of message). If it is determined that the packet type indicates receipt of a general poll message or a specific poll message, the compare state machine performs the compare/mask operation using the current command template to see whether a general poll message or specific poll message is a command type that is expected. If so, then the comparison process continues as described above.
• the packet type e.g., general poll message, specific poll message, or other type of message.
• the compare state machine will not decrement the Compare Counter, will not store the header byte in the SRAM receive buffer 1706, and will not indicate an error. Instead, the OTA LCA 1502 ignores the remainder of the incoming message (although it may continue to generate RSSI information).
• the OTA LCA 1502 makes a similar test for a general poll message or specific poll message, and responds in a similar way, and repeats this process until a general poll message or specific poll message is received or else a time-out occurs (which causes the microcontroller 1505 to reset the compare operation).
• the result of this special case is that, when the user station 301 is looking for a general poll message or specific poll message, the microcontroller 1505 is only interrupted/awakened on a valid general poll message or specific poll message, which results in a power savings.
• the OTA LCA 1502 preferably supports a SIM interface that is compliant with the ISA/IEC 7816-3 interface standard.
• the SIM interface may be managed by the microcontroller 1505 through various interface registers in the OTA LCA 1502.
• the microcontroller 1505 is responsible for managing the setup of the SIM port 1520 over the SIM interface.
• the SIM port 1520 may, if desired, include the capability of inverting or not inverting data, under instruction of the microcontroller 1505.
• the SIM port 1520 may also include the capability of rearranging data prior to transmission and after reception to conform to a most-significant-byte (MSB) first or least-significant-byte (LSB) first format, so that fewer operations for formatting data are required by the microcontroller 1505.
• MSB most-significant-byte
• LSB least-significant-byte
• the microcontroller 1505 To transmit data to the SIM card, the microcontroller 1505 writes the data to be transmitted in the SRAM SIM buffer 1705, prior to enabling the SIM interface. Once the data is in the SRAM SIM buffer 1705, the microcontroller 1505 writes the number of bytes of data to a SIM transmit counter, thereby enabling the SIM interface.
• the OTA LCA 1502 asserts a PEC interrupt (i.e., a type 4 interrupt as defined herein) to obtain the first byte of data from the SRAM SIM buffer 1705, and does so for each byte of data to be transmitted thereafter. With each byte of data retrieved, the SIM transmit counter is decremented until it reaches zero, at which point the transmit process is complete.
• a PEC interrupt i.e., a type 4 interrupt as defined herein
• the SIM interface preferably re-transmits the data autonomously, without the need for intervention by the microcontroller 1505.
• the SIM interface does not make another transmit request (via a PEC interrupt) until the previous byte has been transmitted successfully, or a reset from the microcontroller 1505 occurs. If an attempted transmission fails for a predefined number of times (e.g., 3 times), then the General Status register is set to indicate a SIM transmit error and the microcontroller 1505 may issue a reset to the SIM control circuitry via the General Purpose register.
• the SIM port 1520 is placed in a receive mode (to receive data from the SIM card) upon power-up, or after a successful transmission sequence to the SIM card has been completed, or when an external SIM reset is performed.
• the OTA LCA 1502 After each byte of data is received at the SIM port 1520 from the SIM card, the OTA LCA 1502 asserts an interrupt (i.e., a type 4 interrupt as defined herein) to move the data out of the OTA LCA 1502 and into the SRAM SIM buffer 1705.
• the microcontroller 1505 preferably keeps track of how many bytes have been transferred (as the hardware does not know how many bytes are to be received), and when the desired number of bytes have been received it resets the SIM state machine. During the receive operation, the microcontroller 1505 may perform a watchdog function to ensure that the SIM card is not disconnected or does not fail during the process.
• the OTA LCA 1502 also provides an interface between the microcontroller 1505 and the linearizer ASIC 1513.
• the linearizer ASIC 1513 is connected to the OTA LCA 1502 over a bi-directional, serial interface 1541 which is used for transporting both commands and data.
• the OTA LCA 1502 comprises a linearizer interface which may be instructed by the microcontroller 1505 to serialize and transmit data to the linearizer ASIC 1513, or to receive data from the linearizer ASIC 1513.
• the linearizer interface may also be placed in an autonomous special function mode whereby it periodically loads a temperature compensation instruction in a register accessible to the linearizer ASIC 1513 without requiring intervention by the microcontroller 1505.
• the user station 301 may include provisions for power reduction by selectively deactivating circuitry at times when the full processing potential of the device is not needed.
• the microcontroller 1505 determines that a power reduction mode is appropriate, it instructs the OTA LCA 1502 to enter the power reduction mode by writing a command to a Sleep Control register. If the microcontroller 1505 is to shut itself completely off, it first stores information in the Interrupt Control register (0E016H) to indicate which events will cause interrupts and return the microcontroller 1505 to full operation. If the microcontroller 1505 desires to save some power but will not be inactive for a long period of time, it may choose to place itself in standby mode with the microcontroller 1505 reduced to its minimum frequency.
• the microcontroller 1505 writes an appropriate command to the Sleep Control register of the OTA LCA 1502.
• the OTA LCA 1502 responds by reducing the frequency of the master clock to the minimum allowable frequency (e.g., 1 MHz).
• the microcontroller 1505 restores itself to full speed prior to performing an operation by requesting an interrupt which is handled by the OTA LCA 1502.
• the microcontroller 1505 may also selectively place any or all of the DSP/vocoder 1510, CODEC 1511, digital radio ASIC, and linearizer ASIC 1513 into a power reduction mode, and to selectively restore any device from a power reduction mode to full operation, by issuing commands to the OTA LCA 1502.
• a software control system 201 (sometimes referred to herein as the radio- transceiver component of the software, or RTRX) generally comprises the components shown in solid lines, while components to which the control system 201 interfaces are generally shown in dotted lines.
• the software control system 201 also comprises a real-time operating system (RTOS) not shown in Fig. 2, which provides a software platform that facilitates interaction or operation of the components shown in Fig. 2.
• RTOS real-time operating system
• the software control system 201 Two principal components of the software control system 201 include the over-the- air (OTA) driver 210 and the slot manager 211.
• the OTA driver 210 preferably controls transmit and receive operations for the user station 301, while the slot manager 211 preferably manages slot object-related operations.
• the OTA driver 210 and slot manager 211 communicate using message queues 212, 213, as further described herein.
• the software control system 201 also comprises a variety of interrupt service routines (ISRs), including an MSCA ISR 224, software trap ISR 225, a timer ISR 226, and an end-of-transmit ISR 227, to handle various conditions and events requiring service.
• ISRs interrupt service routines
• a peripheral event controller (PEC) ISR (not shown) is included in the software control system 201, to handle interrupts generated in conjunction with PEC related direct memory access (DMA) transfers.
• the software control system 201 comprises a radio services module 217, which can be accessed by both the OTA driver 210 and the slot manager 211 and provides a common interface to a digital ASIC (hereinafter digital radio ASIC, or DRA) in the radio transceiver 305.
• the software control system 201 further comprises a digital signal processor (DSP) object manager 215 which, like the radio services module 217, can be accessed by both the OTA driver 210 and the slot manager 211.
• DSP digital signal processor
• the general purpose of the DSP object manager 215 is to define and coordinate updates to the DSP/vocoder objects 216.
• Other parts of the software control system 201 include an automatic repeat request (ARQ) module 220 and a power control module 221, both of which are accessible to the slot manager 211.
• ARQ automatic repeat request
• the ARQ module 220 is involved in processing header information for automatic repeat requests, and the power control module 221 processes power control commands received from the base station 104.
• the software control system 201 communicates with other system components through a variety of mailboxes 241, 242, 243 and 244, each preferably having specific assigned functions, as further detailed herein.
• the OTA driver 210 may, for example, communicate with the OTA state machine 252 through a Slot Message (SM) mailbox 242 (designated SM Mbox in Fig. 2), or with a Digital Signal Processor (DSP) driver 251 through a DSP mailbox 244 (designated DSP Mbox in Fig. 2).
• the slot manager 211 of the software control system 201 can access various memory locations (including special - purpose registers) through a variety of direct memory access (DMA) interface components 235, 236, 237, 238 and 239, as further detailed herein.
• DMA direct memory access
• the slot manager 211 is, in one aspect, the heart of the software control system 201.
• the slot manager 211 may define slot objects 231 and perform slot object related operations. Such operations may include the ability to create, delete, update and query a slot object 231.
• the slot manager 211 may carry out all slot operations which must be executed in response to hardware slot synchronous events (e.g., interrupts).
• the slot manager 211 may utilize its inherent knowledge of interrupts to manage the operations of slot objects 231, to synchronize DSP control and status updates, and to synchronize radio configuration updates.
• the slot manager 211 also functions as a service module to the OTA driver 210 and the slot-related interrupt service routines (ISRs).
• ISRs slot-related interrupt service routines
• the slot manager 211 may be invoked by the OTA driver 210 to initialize, create, update, query or delete a slot object 231. If a request cannot be serviced due to potential interrupt conflicts, as determined by the slot manager 211, then the OTA driver 210 may queue the request in the slot message input queue 212 for subsequent interrupt-synchronous processing. As part of its interrupt- related processing, the slot manager 211 may process messages that are queued in the slot message input queue 212, and then queue corresponding responses in the slot message output queue 213. Slot event messages may also be queued in the slot message output queue 213. Slot event messages serve as "unsolicited" notification to the OTA driver 210 that a slot has complete a set of transmit and/or receive transactions. In one aspect, the slot event messages provide a snapshot of the most recent transaction status, including, for example, transmit status, RSSI values, and receive data.
• the slot manager 211 may use service functions to set up hardware, configure ISRs, set up PEC DMA paths, and to update slot objects 231.
• the slot manager 211 may, for example, invoke the DSP object manager 215 to create and initialize DSP objects 216, to commit DSP control updates, or to update DSP status.
• the slot manager 211 may invoke the radio services module 217 to commit configuration updates, synchronize the radio transceiver to time slots, switch between receive and transmit frequencies, read RSSI values, or set the transmit power level.
• the slot manager 211 may invoke the ARQ module 220 to control error detection and recovery processing on OTA packets.
• the slot manager 211 may invoke the power control module 221 to control the transmit power level of the radio transceiver 305 (see Fig. 3).
• the slot manager 211 also may use power-on/self-test functions to set up the various PEC DMA paths.
• the MSCA ISR 224 handles the general status interrupts that are from time to time generated by the MSCA 1591. Non-slot related interrupts are sensed, then signalled externally to the OTA driver 210 through the external event interface 261. Slot-related interrupts (e.g., interrupts occurring when the radio transceiver 305 receives data on an active slot) are handled by invoking the associated function(s) of the slot manager 211.
• the software trap ISR 225 handles software interrupts generated by the software control system 201.
• the software trap ISR 225 invokes the appropriate function(s) of the slot manager 211 based upon the source of the interrupt.
• the software trap ISR 225 may be invoked, for example, upon an end-of-transmit interrupt or a one-shot timer interrupt.
• the end-of-transmit (EOTX) ISR 227 handles an interrupt generated upon completion of the transmit portion of a slot.
• the EOTX ISR 227 sets a flag and generates a software trap (thus invoking the software trap ISR 225) to perform end-of-transmit processing.
• the peripheral event controller of the OTA LCA 1502 invokes the EOTX ISR 227 upon completion of a DMA transfer of transmit data from the SRAM 1524 to the radio transceiver 305.
• the timer ISR 226 handles an interrupt generated upon expiration of a local one- shot timer 229. To perform timer expiration processing, the timer ISR 226 may, for example, update a semaphore or set a flag.
• the peripheral event controller (PEC) ISRs (not shown in Fig. 2) handle interrupts generated upon completion of PEC-controlled DMA transfers. The PEC ISRs are triggered upon completion of DMA data transfers requested by the OTA LCA 1502 through the associated PEC channel.
• a variety of DMA data transfer tasks 223, 235, 236, 237, 238 and 239 are provided for moving data.
• a radio transceiver DMA data transfer task 235 moves transmit data from SRAM 1524 to the radio transceiver 305.
• a DSP input DMA data transfer task 236 moves DSP/vocoder control data from the SRAM 1524 to the DSP/vocoder 1510.
• a radio receive DMA data transfer task 238 moves receive data from the radio transceiver 305 to the SRAM 1524.
• a DSP output DMA data transfer task 239 moves DSP/vocoder status and transmit data from the DSP/vocoder 1510 to the SRAM 1524.
• a receiver compare DMA data transfer task 237 moves receive compare data from SRAM 1524 to the OTA LCA 1502.
• a radio configuration DMA data transfer task 223 moves radio configuration data between the SRAM 1524 and the radio transceiver 305.
• Each of the above DMA data transfer tasks 223, 235, 236, 237, 238 and 239 interface in some manner with the control ASIC or MSCA 205 (e.g., control ASIC 1591 in Fig. 15, or control ASIC 328 in Fig. 3).
• the radio services module 217 provides a common interface to the digital radio ASIC (DRA) in the radio transceiver 305.
• the radio services module 217 provides operations to configure receive and transmit frequencies, codes, and preambles, to control transmit power, to synchronize the radio to time slots, to read RSSI values, and to configure various thresholds.
• the radio services module 217 utilizes registers of the OTA LCA 1502 and DMA I/O operations triggered by the control ASIC 205 for communication with the digital radio ASIC (DRA) in the radio transceiver 305.
• the DSP object manager 215 defines and coordinates updates to DSP/vocoder objects 216.
• the DSP object manager 215 interacts with the DSP/vocoder 1510 at an "object" level, thus treating a DSP/vocoder object 216 as a block of data with an associated identifier, while the external DSP driver 251 actually updates the DSP/vocoder bit-level controls and interprets the DSP/vocoder bit-level statuses.
• the DSP object manager 215 invokes the DSP driver 251 to create, initialize or destroy DSP/vocoder objects 216. Additionally, the DSP object manager 215 accepts updates to the control and status blocks of DSP/vocoder objects 216.
• the slot manager 211 accesses an ARQ service module 220 and power control service module 221 as needed.
• the ARQ service module 220 if included, provides over-the-air error detection, error recovery, error notification and message sequencing based upon the particular ARQ mechanism implemented in over-the- air packets.
• the power control service module 22 if included, controls the transmit power level of the radio transceiver 305 of the user station 301 based upon the power control mechanism implemented in the over-the-air packets.
• a power-on/reset step 705 initiates a control process 701, and typically involves, for example, a user (i.e., a human being) pushing a power-on button on a handset.
• the control process 701 moves to a self-test step 706, wherein a power-on self test is commenced.
• a self-test step 706 a suite of processor and peripheral confidence tests are executed to verify the integrity of the electrical components of the system. If there are no errors as a result of the power-on self-test, control is passed to the real-time operating system (RTOS), and the control process 701 continues with an initialization step 707.
• RTOS real-time operating system
• the initialization step 707 comprises a series of sub-steps 721 through 729, as illustrated in Fig. 7.
• the OTA driver 210 is started, thereby ensuring the availability of RTRX services to other software components.
• the OTA driver 210 performs initialization of the software control system 201.
• the OTA driver 210 associates an event with the RTRX input mailbox 243, which later causes the operating system to automatically signal when one or more messages reside in the RTRX input mailbox 243.
• the peripheral event controller (PEC) ISRs are installed.
• the MSCA ISR 224 and the timer ISR 226 are installed.
• the slot message input queue 212 and slot message output queue 213 are initialized in a following sub-step 726.
• the radio configuration is initialized, followed by sub-step 728 wherein the transceiver-related hardware (i.e., radio transceiver 305 of Fig. 3) is configured to its idle state, and, finally, followed by sub-step 729 wherein the DSP objects 216 are initialized.
• the OTA driver 210 blocks further execution, and the control process 701 enters an idle mode (illustrated as a loop between steps 710 and 711) wherein the software control system 201 awaits either a message to be sent to its RTRX input mailbox 243, or a slot event to be signalled by the MSCA ISR 224.
• the software control system 201 can either execute a software loop where it continuously polls for the above two conditions, or preferably remains completely idle by halting execution and awaiting an interrupt to re-activate execution.
• the "loop" depicted by steps 710 and 711 in Fig. 7 is intended to encompass at least both those possible embodiments. Accordingly, as shown in Fig.
• the control process 701 in step 710 senses the occurrence of a slot event by receiving a signal from the MSCA ISR 244, resulting in a message relating to the slot event to be placed in the slot message output queue 213.
• the OTA driver 210 handles messages queued in the slot message output queue 213, as indicated by step 712, and processes these messages to completion.
• the slot event messages will lead to the sending of a message to the slot message (SM) mailbox 242 associated with the OTA state machine 252.
• the OTA driver 210 processes messages queued in the slot message input queue 212, as indicated in step 713 of the control process 701, until either no messages remain or a message is required to be re-queued. Once processing in step 713 is complete, the OTA driver 210 again blocks execution and returns to the idle mode.
• step 710 the control process 701 moves to step 711, wherein the control process 701 senses whether a message has been received in the RTRX input mailbox 243. If so, the OTA driver 210 then attempts to process the message to completion and, if appropriate, sends a corresponding response.
• operations involving data elements shared by the OTA driver 210 and the software modules invoked by the various ISRs 224, 225, 226 and 227 may require coordination to ensure exclusive access. This shared element access is arbitrated through simple, non-RTOS semaphores. Requests which the OTA driver 210 cannot completely process are preferably queued (i.e., placed in the slot message input queue 212) in first-in first-out (FIFO) order.
• the OTA driver 210 Upon receiving a message in its slot message input queue 212, the OTA driver 210 invokes the appropriate service module to perform all operations associated with the request which do not require exclusive access.
• the OTA driver 210 may, for example, invoke the radio services module 217 to initialize the radio configuration and to register updates to the radio configuration.
• the OTA driver 210 invokes the DSP object manager module 215 to register updates to DSP controls and to request DSP status.
• the OTA driver 210 invokes the slot manager 211 to initialize, create, update, query, or delete slot objects 231, as further described below. After invoking the service modules which do not require exclusive access, the OTA driver 210 then attempts to obtain the associated semaphore for those service modules or other software components requiring exclusive access.
• a slot object 231, as used herein, preferably comprises a data structure corresponding to a logical communication channel.
• the slot manager 211 is primarily responsible for organizing and maintaining slot objects 231 during communication between the user station 301 and a base station 104.
• a slot object 231 preferably comprises, among other things, command data and/or configuration information, including, for example, transmit power level information, ARQ information, state machine information, and data pointers (which identify the memory locations of data messages).
• a slot object 231 also preferably comprises a list of one or more time slot tags corresponding to the time slots which form the logical communication channel.
• a slot object 231 will comprise only a single time slot (and thus a single time slot tag); however, it may comprise a "super-slot” (i.e., multiple time slots) or a "sub-slot” (i.e., a time slot utilized once every N time frames).
• Each time slot tag preferably includes a next slot pointer indicating the next time slot, from among any of the active time slots within the slot objects 231, that is either a transmit or receive time slot for the user station 301.
• the slot object 231 preferably comprises information indicating whether its associated time slots are transmit or receive time slots, and whether they are to transmit signalling, voice or other data messages.
• a first slot object 231 is set up with a single transmit time slot (and hence a single time slot tag), and a second slot object 231 is set up with a single receive time slot (and hence a single time slot tag).
• the time slot tag of the first slot object 231 indicates in which slot position the user station 301 will transmit, and the first slot object 231 comprises information, as described above, utilized in the transmission process, including a pointer to the message to be transmitted.
• the time slot tag of the second slot object 231 indicates in which slot position the user station 301 will receive, and the second slot object 231 comprises information, as described above, utilized in the receive process, including a pointer to the appropriate receive message buffer.
• the time slot tag of the first slot object 231 comprises a next slot pointer which will (in the absence of any other slot objects 231) identify the receive time slot of the second slot object 231 as the next active time slot, while, similarly, the time slot tag of the second slot object 231 comprises a next slot pointer which will identify the transmit time slot of the first slot object 231 as the next active time slot.
• a slot object 231 may be added to define a logical signalling channel.
• the new slot object 231 will comprise one or more time slot tags indicating, among other things, which time slots are to be used to transmit, or receive, signalling information.
• any other time slot tags within the existing slot objects 231 are modified, as appropriate, to update their next time slot pointers so as to maintain proper sequencing.
• a slot object 231 exists until deleted by the slot manager 211.
• the user station 301 will communicate each time frame in each time slot defined by the time slot tags of the existing slot objects 231.
• a slot object 231 may be created simply to communicate in one time slot of one time frame, and then get deleted. This short lifespan may occur when the user station 301 transmits a brief signalling message, for example.
• a slot object 231 may last indefinitely.
• a slot object 231 may be modified dynamically by the slot manager 211.
• a slot object 231 may thereby not only define multiple time slots within a time frame, but these time slots can be changed from time frame to time frame, thus allowing, for example, the exercise of fast control traffic operations such as described in, e.g., U.S. Patent Application Ser. No. 09/122,565 filed August 24, 1998, assigned to the assignee of the present invention, and hereby incorporated by reference as if set forth fully herein.
• Slot objects 231 are generally created, modified or deleted at the request of upper layer protocol requests. These requests are received and queued by the OTA driver 210 for processing by the slot manager 211.
• the slot manager 211 ensures that slot objects 231 are only created, modified or deleted at times which do not interfere with crucial or ongoing hardware operations.
• the slot manager 211 also ensures that the slot object tags of the existing slot objects 231 are modified, if necessary, to reflect new time slots added from addition of a new slot object 231 or old time slots removed by deletion of an existing slot object 231.
• the slot manager 211 provides isolation between the OTA driver 210 and other components of the software control system 201, and the system hardware and/or physical layer of the user station 301.
• time slots defined by the existing slot objects 231 are processed sequentially according to their relative position within the time frame.
• the control and/or configuration parameters for the next time slot are loaded into the hardware by the slot manager 211.
• the loading of the new control and/or configuration parameters may, for example, cause the radio transceiver 305 to be switched from a receive mode to a transmit mode, or vice versa, and may also cause the radio transceiver 305 to load a new spread spectrum code set, if desired.
• At least one time slot separates each active time slot for the user station 301, unless adjacent active time slots employ the same control and configuration parameters such that the loading of new parameters is unnecessary.
• Each slot object 1902, 1903 and 1904 comprises a slot profile which includes command data and/or configuration information, such as the slot type (transmit or receive), message type (voice, signalling, data, etc.), and other information (such as transmit power level, ARQ information, etc.) as described above.
• Each slot object 1902, 1903 and 1904 has at least one time slot tag identifying an active time slot for the user station 301.
• the first slot object 1902 has one time slot tag 1911 corresponding to transmit time slot #1 of a time frame 1920, and indicating (via a next slot pointer) that the next active time slot for the user station 301 is time slot #5.
• the second slot object 1903 has one time slot tag 1912 corresponding to receive time slot #9, and indicating (via a next slot pointer) that the next active time slot for the user station 301 is time slot #12.
• the first and second slot objects 1902, 1903 are set up for voice traffic.
• the first and second slot objects 1902, 1903 may collectively comprise a duplex voice channel, according to the frame structures of Figs. 4, 5 or 6, for example.
• the third slot object 1904 has three time slot tags 1913, 1914 and 1915. Its first time slot tag 1913 corresponds, as shown, to receive time slot #5; the second time slot tag 1914 corresponds to receive time slot #12; and the third time slot tag 1915 corresponds to receive time slot #14.
• the three time slot tags 1913, 1914 and 1915 of the third slot object collectively define a receive communication channel for signalling data for the user station 301. If desired, a fourth slot object could be added to the collection of slot objects to define a transmit communication channel for signalling data.
• the OTA driver 210 assists in control of the operation of the software control system 201.
• the OTA driver 210 performs initialization of the software control system 201, monitors the RTRX input mailbox 243, routes requests to service modules, monitors the slot message input queue 212 and slot message output queue 213, processes slot events, and responds to the RTRX output mailbox 241.
• the OTA driver 210 When a slot event requires processing, the OTA driver 210 preferably processes the slot event to completion before the next slot event is signalled.
• the slot manager 211 may indirectly control this sequencing by ensuring that at least one inactive slot (e.g., 1.25 milliseconds, in one embodiment) occurs between active slots.
• Table 2-1 below lists some of the inputs to the OTA driver 210 and their sources, s well as comments regarding each.
• the OTA driver 210 responds to the following RTRX input mailbox messages: RTRX Configure Request, RTRX Reset Request, Link Request, Radio Configure Request, and DSP Update Request.
• RTRX Configure Request RTRX Configure Request
• RTRX Reset Request Link Request
• Radio Configure Request DSP Update Request
• RTRX input mailbox 261 it performs the following processing steps:
• the OTA driver 210 When the OTA driver 210 receives an RTRX Reset Request message in the RTRX input mailbox 261, it performs the following processing steps: 1. Shuts down the software control system 201.
• Link Create Request invokes the slot manager 211 to create the slot as specified.
• Link Delete Request invokes the slot manager 211 to delete the slot.
• Link Query Request invokes the slot manager 211 to obtain a snapshot of the slot's latest configuration and status.
• Link Update Request invokes the slot manager 211 to reconfigure the slot as specified by the request.
• the OTA driver 210 queues the request in the slot message input queue 212.
• the OTA driver 210 sends the associated Link Response to the return mailbox specified in the Link Request message.
• the OTA driver 210 When the OTA driver 210 receives a Radio Configure Request message in the RTRX input mailbox 261, it performs the following processing steps:
• the OTA driver 210 When the OTA driver 210 receives a DSP Update Request message in the RTRX input mailbox 261, it performs the following processing steps: 1. Invokes the DSP object manager 215 to update the DSP object 216 as specified by the DSP Update Request message. 2. Sends a DSP Register Update Confirmation message to the mailbox associated with the DSP object 216.
• the OTA driver 210 In addition to RTRX input mailbox messages, the OTA driver 210 also processes messages received in the slot message input queue 212. For example, when the OTA driver 210 receives a Slot Request message in the slot message input queue 212, it performs the following processing steps:
• the OTA driver 210 may re-queue the request in the slot message input queue 212.
• the OTA driver 210 sends the associated Link Response message to the return mailbox specified in the Slot Request message.
• the OTA driver 210 processes messages queued in the slot message output queue 213. For example, when the OTA driver 210 receives a Slot Response message in the slot message output queue 213, it performs the following processing steps: 1. Processes each Slot Response message, as follows: a. Slot Create Response - sends a Link Create Response message to the return mailbox specified in the request. b. Slot Delete Response - invokes the slot manager 211 to perform final delete operations on the slot, then sends a Link Delete Response message to the return mailbox specified in the request. c. Slot Query Response - invokes the slot manager 211 to obtain a snapshot of the slot's latest configuration and status, then sends a Link Query Response message to the return mailbox specified in the request. d. Slot Update Response - sends a Link Update Response message to the return mailbox specified in the request. When the OTA driver 210 receives a Slot Receive Complete message in the slot message output queue 213, it performs the following processing steps, depending on the conditions described below:
• the OTA driver 210 then: a. Invokes the slot manager 211 to obtain a snapshot of the slot's latest configuration and status. b. Sends a Link Event Indication message to the mailbox associated with the slot object 231. 2. If the DSP object manager 215 indicates that the status of the associated
• the OTA driver 210 then: a. Sends a DSP Register Update Indication message to the mailbox associated with the DSP object 216.
• the OTA driver 210 Upon detecting a slot event, the OTA driver 210 processes all messages queued in the slot message output queue 213 to completion, as specified in the process steps above, and then processes all messages queued in the slot message input queue 212 to completion, as specified in the process steps above, or until forced to re-queue a message due to an access conflict or for some other reason.
• the OTA driver 210 sends an Error Indication message to the RTRX output mailbox 241.
• error conditions include an unrecognized external message received from the RTRX input mailbox 243, or an unrecognized message received from the slot message input queue 212 or slot message output queue 213.
• Table 2-2 lists some of the outputs from the OTA driver 210 and their destinations, as well as comments regarding some of the OTA driver outputs.
• the slot manager 211 preferably defines all slot objects 231 and performs all operations related to the slot objects 231. For example, the slot manager 211 may create, delete, update or query slot objects 231. In addition, the slot manager 211 handles those slot operations which are executed in response to hardware slot-synchronous events (e.g., interrupts), and can use its inherent knowledge of interrupts to manage the operations on slot objects 231 and perform other functions.
• hardware slot-synchronous events e.g., interrupts
• Table 3-1 lists major inputs to the slot manager 211 and their sources, along with comments.
• Table 3-2 illustrates data elements used by the slot manager 211 in a preferred embodiment, along with a brief description of each.
• Table 3-3 below describes a structure which is used in one embodiment comprising the slot manager 211 containing the configuration and status of a slot.
• the slot manager 211 comprises a service module for the OTA driver 210 and slot-related ISRs that can be called upon demand as needed.
• the slot manager 211 may in some cases be subject to specific timing requirements imposed, for example, by the interrupt processing functions (e.g., the ISRs 224, 225, etc.). Timing and sequencing of various operations may, in particular, require consideration in relation to signalling traffic processing and voice traffic processing. Such timing and sequencing considerations may be explained with reference to Figs. 8, 9, 10 and 11, of which Figs. 8 and 9 relate to signalling traffic processing, while Figs. 10 and 11 relate to voice traffic processing.
• FIG. 8 depicts a signalling traffic path in accordance with one embodiment disclosed herein, while Fig. 9 illustrates data paths and sequencing for an active signalling traffic slot.
• Fig. 8 depicts a microphone 827, speaker 828, CODEC 826 and DSP/vocoder 825, in a preferred embodiment these components are not utilized as part of the signalling traffic path.
• an SRAM transmit buffer 810, SRAM receive buffer 860, control ASIC 805, and digital radio ASIC (DRA) 820 shown in Fig. 8 are components utilized in the signalling traffic path.
• the SRAM transmit buffer 810 comprises storage area for a user station header 813, D channel information 812, bearer data 811, and DSP/vocoder status information 814.
• the SRAM receive buffer 860 comprises storage area for a base station header 863, D channel information 862, bearer data 861, and DSP/vocoder control information 864.
• a transmit sequence for signalling traffic from the user station 301 the following steps occur, as illustrated in the timing/sequence relationship shown in Fig. 9:
• a user transmit portion 902 of a time slot (for example, time slot 1 shown in Fig. 4 with respect to user station M9), the user station header 813, D channel information 812, and bearer data 811 are transferred from the SRAM transmit buffer 810 to the DRA 820 via a peripheral event controller (PEC) channel associated with the radio transmit DMA data transfer task 235, using a peripheral event controller counter to control the number of bytes transmitted.
• PEC peripheral event controller
• an end-of-transfer interrupt associated with the radio transmit DMA data transfer task 235 is generated.
• the radio transmit DMA ISR invokes the end-of-transmit (EOTX) ISR 227, which issues a software trap and thereby invokes the software trap ISR 225.
• EOTX end-of-transmit
• the software trap ISR 225 invokes the slot manager 211 for "transmit frame complete” processing. 5. Radio receive frequency data is transferred from the SRAM 821 to the
• an end-of-transfer interrupt occurs associated with the radio configuration DMA data transfer task 223.
• the radio transceiver 305 then re-adjusts its frequency synthesizer to a reception frequency.
• a base transmit portion 952 of a time slot (for example, time slot 9 shown in Fig. 4 with respect to the base station), the base station header 863, D channel information 862, and bearer data 861 are transferred from the DRA 820 to an SRAM receive buffer 860 via PEC channel associated with the radio receive DMA data transfer task 238, using a peripheral event controller counter to control the number of bytes transferred.
• Compare data for the receive frame i.e., the results of the command/mask comparison operations
• DMA data transfer task 237 is generated.
• the control ASIC 805 triggers a "receive compare complete" interrupt.
• the MSCA ISR 224 invokes the slot manager 211 to perform "receive compare complete" processing. 6. An end-of-transfer interrupt associated with the radio receive DMA data transfer task 238 is generated.
• the control ASIC 805 triggers a "receive frame complete" interrupt.
• the MSCA ISR 224 invokes the slot manager 211 to perform "receive frame complete" processing.
• Radio transmit frequency data is transferred from the SRAM 821 to the
• FIG. 10 depicts a voice traffic path in accordance with one embodiment disclosed herein, while Fig. 11 illustrates data paths and sequencing for an active voice traffic slot.
• Figure 10 depicts a microphone 1027 and speaker 1028 connected to a CODEC 1026, which is connected to a DSP/vocoder 1025.
• the DSP/vocoder 1025 is connected to a control ASIC 1005, which is connected to an SRAM 1021 (comprising an SRAM transmit buffer 1010 and an SRAM receive buffer 1060) and digital radio ASIC (DRA) 1020.
• SRAM 1021 comprising an SRAM transmit buffer 1010 and an SRAM receive buffer 1060
• DRA digital radio ASIC
• the SRAM transmit buffer 1010 comprises storage area for a user station header 1013, D channel information 1012, bearer data 1011, and DSP/vocoder status information 1014.
• the SRAM receive buffer 1060 comprises storage area for a base station header 1063, D channel information 1062, bearer data 1061, and DSP/vocoder control information 1064.
• the user station header 1013, D channel information 1012, and bearer data 1011 are transferred from the SRAM transmit buffer 1010 to the DRA 1020 via a PEC channel associated with the radio transmit DMA data transfer task 235, using a peripheral event controller counter to control the number of bytes transmitted.
• an end-of-transfer interrupt associated with the radio transmit DMA data transfer task 235 is generated.
• the radio transmit DMA ISR invokes the end-of-transmit (EOTX) ISR 227, which issues a software trap and thereby invokes the software trap ISR 225.
• EOTX end-of-transmit
• the software trap ISR 225 invokes the slot manager 211 for "transmit frame complete" processing.
• Radio receive frequency data is transferred from the SRAM 1021 to the DRA 1020 via a PEC channel associated with the radio configuration DMA data transfer task 223.
• the above steps for transmitting voice information are essentially the same steps previously described as carried out for transmitting signalling information from the user station 301.
• the DSP/vocoder status information 1014 and bearer data 1011 are transferred from the DSP/vocoder 1025 to the SRAM transmit buffer 1010 via a PEC channel associated with the DSP output DMA data transfer task 239.
• DSP control data 1064 is transferred from the SRAM receive buffer 1060 to the DSP/vocoder 1025 via a PEC channel associated with the DSP input DMA data transfer task 236. 3.
• an end-of-transfer interrupt associated with the DSP input DMA data transfer task 236 is generated.
• the base station header 1063, D channel information 1062, and bearer data 1061 are transferred from the DRA 1020 to an
• Compare data for the receive frame i.e., the results of the command/mask comparison operations
• ASIC 1005 via a PEC channel associated with the RX compare DMA data transfer task 237.
• the control ASIC 1005 triggers a "receive compare complete” interrupt.
• the MSCA ISR 224 invokes the slot manager 211 to perform "receive compare complete” processing.
• An end-of-transfer interrupt associated with the DSP output DMA data transfer task 239 is generated.
• An end-of-transfer interrupt associated with the radio receive DMA data transfer task 238 is generated.
• the control ASIC 1005 triggers a "receive frame complete” interrupt.
• the MSCA ISR 224 invokes the slot manager 211 to perform "receive frame complete" processing.
• Radio transmit frequency data is transferred from the SRAM 1021 to the DRA 1020 via a PEC channel associated with the radio configuration DMA data transfer task 223.
• Steps 4 through 14 above for receiving voice information are essentially the same steps as carried out for receiving signalling information from the user station 301.
• the slot manager 211 In addition to assisting with the transmission and reception of signalling information and voice/data information, the slot manager 211 also provides access control to slot objects 231. More specifically, in a preferred embodiment, the slot manager 211 implements a semaphore that controls exclusive access to the slot objects 231. In addition to providing exclusive access between the OTA driver 210 and ISR processing, the semaphore ensures that the configuration of a slot object 231 will not change after it has been committed (i.e., after the hardware has been configured).
• the semaphore is implemented through a timer 229 having a suitable resolution, such as, e.g., one microsecond resolution.
• the timer 229 is preferably implemented as a one-shot timer.
• the semaphore is cleared by the slot manager 211 at slot-synchronous times (i.e., at transitions between time slots 1202) to allow access to slot objects 231 for a time period defined by the value loaded in timer 229, and the semaphore is set upon timer expiration to disallow access to slot objects 231.
• This operation is illustrated in Fig. 12, which shows a time frame 1201 divided into a series of time slots 1202 (for simplicity, Fig. 12 does not show time slots on different base and user frequency bands).
• the semaphore starts out as set during a time period 1220.
• the slot manager 211 clears the semaphore at a point in time 1205, and the timer 229 (after being loaded with an appropriate count value reflecting the desired access time) is started. Access to the slot object 231 is then available for a time period 1221 indicated in Fig. 12, until the timer 229 times out at a later point in time 1206. The semaphore then remains set for a time period 1222, during which access to the slot object 231 is not allowed. At a next point in time 1210, the slot manager 211 clears the semaphore, thereby allowing access to the slot object 231. Access is allowed during the time period 1223, until a point in time 1211 when the timer 229 times out. The semaphore then returns to its set state. Preferably, as shown in Fig. 12, each setting or clearing of the semaphore is carried out on a transition between time slots 1202 (i.e., slot-synchronously).
• the slot manager 211 preferably functions as a service module to the OTA driver 210 and can be invoked to initialize, create, update, query, or delete a slot object.
• the slot manager 211 processes individually each slot request received from the OTA driver 210, and queues an associated response (e.g., success, fail, or incomplete) in the slot output message queue 213. Further details about these operations, as illustrated by a preferred embodiment, are explained below.
• the slot manager 211 performs several steps. First, the slot manager 211 installs the timer ISR 226. Next, the slot manager initializes the slot objects 231, the slot message input queue 212, the slot message output queue 213, and the DSP objects 216. Finally, the peripheral event controller (PEC) interrupts relating to slot object DMA functions are enabled by the slot manager 211.
• PEC peripheral event controller
• the slot manager 211 To create a slot object 231, the slot manager 211 first attempts to allocate a slot object 231. If the allocation attempt is unsuccessful, a failure status indicator is returned; otherwise the slot object is initialized and configured as specified by the request. Then, if access to slot objects 231 is not allowed (by reason of the semaphore), an incomplete status indicator is returned. Otherwise, the slot object 231 is inserted into a slot list. If there are no other active slots, then the radio services module 217 is invoked to commit any outstanding updates and to complete radio initialization. The slot manager 211 then performs "receive setup" processing, as described below. Finally, slot-related interrupts generated by or through the control ASIC 205 are enabled. Thereafter, the MSCA ISR 224 will be triggered by a general status interrupt upon the first successful receive. The slot manager 211 then returns a success status indicator.
• the slot manager 211 To delete a slot object 231, the slot manager 211 first determines whether access to the slot objects 231 is allowed (as dictated by the semaphore). If access is not allowed, an incomplete status indicator is returned. Otherwise, the slot object 231 is removed from the slot list. If there are no other active slots, then slot-related interrupts generated by or through the control ASIC 205 are disabled, and the radio services module 217 is invoked to reset the radio transceiver 305 to its idle state. The receive state machine in the control ASIC 205 is reset. The slot object 231 which has been removed from the slot list is then de-allocated, and a success status indicator is returned.
• the slot manager 211 To update a slot object 231, the slot manager 211 first saves the specified update configuration. If access to slot objects 231 is not allowed, an incomplete status indicator is returned. Otherwise, the configuration updates are "committed” by switching the active configuration for the slot object 231 to the saved update configuration. If the slot object 231 being updated is currently active, then the slot manager 211 performs "receive setup” or “transmit setup” processing as appropriate, and as described in more detail below. Finally, a success status indicator is returned.
• the slot manager 211 To query a slot object 231, the slot manager 211 first determines whether access to the slot objects 231 is allowed (as dictated by the semaphore). If access is not allowed, an incomplete status indicator is returned. Otherwise, the slot manager 211 accesses the slot object's current configuration and current status. The slot manager 211 then returns a success status indicator.
• the slot manager 211 is also involved in interrupt processing. For example, the slot manager 211 performs processing when a receive compare complete interrupt, a receive frame complete interrupt, or a transmit frame complete interrupt occurs.
• the slot manager 211 stops the one-shot timer 229. It then checks the Head Check Field (HCF) Status from a Receive Status Register of the control ASIC 205. If the HCF status is "good”, then the slot manager extracts the OTA header fields, including Packet Type, Channel Utilization, Next Slot Pointer, ARQ, and Power. On the other hand, if the HCF status is "bad”, the OTA header fields are set to default values, as follows: Packet Type is set to unknown; Channel Utilization is set to unknown; Next Slot Pointer is set to indicate the "same slot next frame"; ARQ is set to indicate no change; and Power is set to indicate no change.
• HCF Head Check Field
• the slot manager 211 then updates the "receive status" for the current slot, including HCF status, Packet Type, Channel Utilization, and RX Compare Status (which is extracted from the General Status Register of the control ASIC 205). Finally, the slot manager 211 loads the Slot Map Pointer Register of the control ASIC 205 to select the next time slot in which to receive. When a transmit frame complete interrupt occurs, the slot manager 211 sets up to receive or transmit, as appropriate, for the next slot object 231 as further detailed herein.
• the slot manager 211 When a receive frame complete interrupt occurs, the slot manager 211 first examines the Packet Frame Check Word (FCW) Status from the Receive Status Register of the control ASIC 205. If the FCW Status is "good”, the slot manager 211 then determines whether an attempt is being made to synchronize to a time slot and, if so, whether synchronization has been achieved. If it has, the slot manager 211 clears radio synchronization control. The slot manager 211 then checks the receive Compare Status and, if "good”, resets the slot object compare control (i.e., the command mask templating operation) to compare only with the OTA Header field, with a "don't care" Packet type.
• FCW Packet Frame Check Word
• the slot manager 211 then invokes the ARQ service module 220 to perform ARQ processing, and sets the receive status of the message.
• the slot manager 211 determines the transmit status for the message. If the ARQ passed, the message transmit status is "good", and the slot manager 211 switches to a default transmit message. If, however, ARQ failed, and if a predefined number of retries have been exhausted, the message transmit status is changed to "bad”. The slot manager 211 then switches to a default transmit message. If ARQ failed but the predefined number of retries has not yet been exhausted, the message transmit status is changed to (or kept at) "unknown”. The current transmit message is kept for a subsequent re-transmission.
• the slot manager 211 continues interrupt processing for the receive compare complete interrupt, by invoking the power control module 221 to determine the transmit power level for the next transmission on the current time slot.
• the slot manager 211 then reads the RSSI values from the RSSI registers of the control ASIC 205. It allocates a new receive buffer in the SRAM 1524 for the next receive frame on the same time slot.
• the slot manager 211 processes messages in the slot input message queue 212, as further detailed herein. If the slot is in a voice traffic mode, the slot manager 211 copies the DSP/vocoder status data to the associated DSP object 216.
• the slot manager 211 sets up to receive or transmit, as appropriate, for the next slot object 231 as further detailed herein.
• the slot manager 211 For receive setup processing, the slot manager 211 first determines whether there are any pending radio configuration updates and, if so, invokes the radio services module 217 to commit the updates. The slot manager 211 also invokes the radio services module 217 to configure the radio receive frequency. Next, the slot manager 211 enables the radio receive DMA path, and disables the radio transmit functionality. The slot manager 211 then sets radio synchronization control as follows. If the user station 301 is in the process of acquiring a time slot (i.e., synchronizing), the slot manager 211 sets radio synchronization control to synchronize upon the first "good" (i.e., error-free) qualified receive slot.
• the slot manager 211 sets radio synchronization control to synchronize upon the first "good" (i.e., error-free) qualified receive slot.
• the slot manager 211 sets radio synchronization control to generate a DSP synchronization pulse for the current time slot, and then enables the DSP (e.g., DSP/vocoder 1510) through a General Purpose Register in the control ASIC 205 or 1591, for example. If neither of these synchronization activities are in process, the slot manager 211 clears radio synchronization control.
• DSP digital signal processor
• the slot manager 211 sets up the receive data paths for the time slot.
• the slot manager 211 sets up and enables a peripheral event controller (PEC) channel associated with the receive compare DMA data transfer task 237, thereby allowing direct memory access (DMA) operations for transfer of compare data from memory (e.g., from SRAM command buffer 1704 shown in Fig. 17) to a Command Compare Register in the control ASIC 205.
• PEC peripheral event controller
• the slot manager 211 sets up and enables a PEC channel associated with the radio receive DMA data transfer task 238, thereby enabling DMA operations for the transfer of data from a Receive Source Register in the control ASIC 205 to receive data memory (e.g., SRAM receive buffer 1706).
• the slot manager 211 copies DSP/vocoder control data from the associated DSP object 216 to DSP control memory (e.g., vocoder control field 1805 shown in Fig. 18).
• the slot manager 211 sets up and enables a PEC channel associated with the DSP input DMA data transfer task 236, thereby enabling DMA operations for the transfer of data from memory (e.g., SRAM receive buffer 1706) to a DSP Data/Control Register in the control ASIC 205.
• the slot manager 211 sets up a pre- transmit data path for the time slot.
• the slot manager 211 sets up and enables the PEC channel associated with the DSP output DMA data transfer task 239, thereby enabling DMA operations for transferring data from a DSP Source Register in the control ASIC 205 to memory (e.g., SRAM transmit buffer 1707).
• the slot manager 211 sets a Data Notice Select in the control ASIC 205 based upon the traffic mode (i.e., signalling or voice) of the time slot.
• the slot manager 211 starts the one-shot timer 229.
• the timer ISR 226 is configured to process queued messages upon expiration of the timer 229.
• the timer ISR 226 is configured by the slot manager 211 to set the slot object access semaphore upon expiration, thereby blocking access to slob objects 231 when the timer 226 times out.
• the slot manager 211 loads the Compare Count register in the control ASIC 205 to set up and initiate the command/mask templating operation upon reception of the receive frame.
• the slot manager 211 For transmit setup processing, the slot manager 211 first determines whether there are any pending radio configuration updates and, if so, invokes the radio services module 217 to commit the updates. The slot manager 211 invokes the radio services module 217 to configure the radio transmit frequency. Next, the slot manager 211 disables the radio receive DMA path, enables the radio transmit functionality, and clears radio synchronization control. The slot manager 211 then sets up the OTA header (e.g., user station header 813 in Fig. 8, or user station header 1013 in Fig. 10, or user station header 1808 in Fig. 18, depending on whether bearer traffic message(s) or signalling traffic message(s) will be sent).
• OTA header e.g., user station header 813 in Fig. 8, or user station header 1013 in Fig. 10, or user station header 1808 in Fig. 18, depending on whether bearer traffic message(s) or signalling traffic message(s) will be sent.
• the slot manager 211 may set up the Packet Type field as specified in the transmit configuration data, or the ARQ field as determined by the ARQ service module 220.
• the slot manager 211 sets up the transmit data path for the time slot.
• the slot manager 211 sets up and enables the PEC channel associated with the radio transmit DMA data transfer task 235, thereby enabling DMA operations to transfer data from transmit data memory (e.g., SRAM transmit buffer 1707) to a Transmit Destination Register in the control ASIC 205.
• the slot manager 211 starts the one-shot timer 229 and configures the timer ISR 226 to set the slot object access semaphore upon expiration, thereby blocking access to slot objects 231 when the one-shot timer 229 times out.
• the slot manager 211 invoke the radio services module 217 to load the desired transmit power level.
• the slot manager 211 Upon expiration of the one-shot timer 229, the slot manager 211 performs certain processing operations. The slot manager 211 processes messages queued in the slot message input queue 212, and then configures the timer ISR 226 to process queued messages upon time-out by the one-shot timer 229. Table 3-4 below summarizes the major outputs of the slot manager 211 and their destinations, along with comments. Table 3-4
• the MSCA ISR 224 handles the general status interrupts that are generated by the control ASIC 205.
• Non-slot related interrupts are sensed, then signalled externally through an external event interface.
• Non-slot related interrupts may include, for example, SIM TX error (i.e., SIM transmit port error), Mode Change (i.e., a port connector change has occurred or is sensed), and a Keypad Event (i.e., one or more keypad keys was pressed and released).
• SIM TX error i.e., SIM transmit port error
• Mode Change i.e., a port connector change has occurred or is sensed
• a Keypad Event i.e., one or more keypad keys was pressed and released.
• Slot-related interrupts are handled by invoking the associated function of the slot manager 211.
• Slot-related interrupts may include, for example, RX Compare Complete (i.e., the receive command/mask templating operation has been completed for a slot) and RX Frame Complete (i.e., the receive portion of a slot has been completed). Slot interrupts are generated when the user station 301 receives data on an active time slot.
• the MSCA ISR 224 is preferably capable of drawing upon ISR services of the real-time operating system, if needed for its functionality.
• the MSCA ISR 224 When invoked, the MSCA ISR 224 reads the MSCA General Status Register (GSR) to determine the cause of the interrupt. The MSCA ISR 224 then proceeds to service the interrupt, based upon its source. For example, for an RX Compare Complete interrupt, the MSCA ISR 224 may invoke the slot manager 211 to perform RX compare complete processing. For an RX Frame Complete interrupt, the MSCA ISR 224 may invoke the slot manager 211 to perform RX frame complete processing, and then signal a slot event.
• GSR MSCA General Status Register
• the MSCA ISR 224 executes upon each General Status interrupt received from the control ASIC 205.
• the control ASIC 205 is preferably given the highest possible interrupt priority that is lower than the priority of the RTOS system timer interrupt.
• the highest priorities are preferably reserved for the peripheral event controller (PEC) interrupts; therefore, it is possible for the MSCA ISR 224 to be interrupted by a PEC interrupt.
• PEC peripheral event controller
• non-slot related interrupts handled by the MSCA ISR 224 are asynchronous and aperiodic.
• slot- related interrupts are synchronous with the time slots, as may be explained by way of example with reference to Fig. 13.
• a time slot 1302 is divided into a user station transmit frame 1303 and a base station transmit frame 1304.
• the user station transmit frame 1303 and base station transmit frame 1305 are separated by a guard time and turn- around gap (collectively denoted by gap 1304 in Fig. 13).
• the user station transmit frame 1303 commences after a variable radio gap 1310 occurring at the starting point 1321 of the time slot 1302.
• a second turn-around gap 1311 occurs between the end of the base station transmit frame 1305 and the ending point 1322 of the time slot 1302 (i.e., the start of the next time slot 1352).
• the length of the first time period 1361 reflects processing of the header in the base station message and therefore depends in part upon the size of the header in the base station message.
• the RX Compare Complete interrupt during the period 1361 invokes the MSCA ISR 224.
• interrupt processing responsive to the RX Compare Complete interrupt occurs, and is preferably completed before the end of the base station transmit frame 1305.
• an RX Frame Complete interrupt occurs at point 1363 in Fig. 13.
• Processing in response to the RX Frame Complete interrupt occurs over time period 1364, and is preferably complete before the next time slot 1352. However, if the next time slot 1352 is not in use, processing may continue up until the end of the next time slot 1352.
• Table 4-1 summarizes the major outputs of the MSCA 224 and their destinations, along with comments. Table 4-1
• the software trap ISR 225 handles software interrupts (traps) generated by the software control system 201.
• the software trap ISR 225 invokes the appropriate functions of the slot manager 211 functions based upon the source of the interrupt.
• the software trap ISR 225 is preferably a "cooperative" ISR in the sense that it is free to use real-time operating system services for interrupt handling.
• One purpose of the software trap ISR 225 is to promote non-cooperative ISRs to cooperative ISRs.
• a software trap may be triggered by any of a variety of events, including TX frame complete or one shot timer expiration. It may be invoked, for example, by the end-of- transmit (EOTX) ISR 227 or the timer ISR 226.
• EOTX end-of- transmit
• the end-of-transmit (EOTX) ISR 227 handles the interrupt generated upon the completion of the user station transmit frame within a time slot.
• the EOTX ISR 227 may be invoked by a radio transmit DMA peripheral event controller ISR.
• the EOTX ISR 227 sets a flag and generates a software trap to perform end-of-transmit processing.
• the radio transmit DMA PEC ISR invokes the EOTX ISR 227 upon completion of DMA transfer of transmit data from memory to the radio.
• the EOTX ISR 227 may, in some embodiments, be non-cooperative ISR and therefore unable to use real-time operating system (RTOS) services. However, the EOTX ISR 227 may invoke the software trap ISR 225 to allow access to such services.
• RTOS real-time operating system
• the timer ISR 226 handles the interrupt generated upon expiration of the one-shot timer 229.
• the timer ISR 226 may update a semaphore or set a flag and then generates a software trap to transfer control over to the software trap ISR 225 to perform timer expiration processing.
• the timer ISR 226 may, in some embodiments, be a non- cooperative ISR and therefore unable to use real-time operating system services without the assistance of the software trap ISR 225.
• the peripheral event controller (PEC) ISRs handle interrupts generated upon completion of PEC-controUed DMA transfers.
• the PEC ISRs are triggered upon completion of DMA I/O requested by the control ASIC 205 through the associated PEC channel.
• a PEC ISR updates a counter or otherwise calls ⁇ function, as illustrated by examples explained earlier herein. Table 5-1 below summarizes the major inputs to the PEC ISRs and their sources, along with comments.
• the PEC ISRs are "non-cooperative" in the sense of not interfacing with the real-time operating system.
• the system processor e.g., micro- controller 1505 shown in Fig. 15
• the system processor preferably reserves the highest priorities and group numbers for the PEC interrupts. Simultaneous requests for PEC channels are prioritized according to the PEC channel number, where channel 0 has the lowest priority and channel 7 has the highest priority. Table 5-2 below shows PEC interrupt assignments in one embodiment.
• the associated PEC ISR is invoked to performs end-of-PEC transfer processing. If the interrupt action specifies an event counter to update, the PEC ISR increments the event counter. If the interrupt action specifies a function to call, the PEC ISR calls the specified function. In a presently preferred embodiment, only the PEC ISR associated with the radio transmit DMA transfer task 235 specifies a function to call.
• the PEC event counters may be monitored by external (i.e., non-PEC ISR) software processing components. These external software processing components may clear (i.e., zero) a given PEC event counter, or else let it increment until it rolls over.
• external software processing components may clear (i.e., zero) a given PEC event counter, or else let it increment until it rolls over.
• Table 5-3 summarizes the major outputs of the PEC ISRs and their destinations, along with comments.
• the radio services module 217 provides a common interface to the digital radio ASIC (DRA).
• the radio services module 217 preferably provides functions to configure receive and transmit frequencies, codes, and preambles, to control transmit power, to synchronize the radio to time slots, to read RSSI values, and to configure various thresholds.
• the radio services module 217 may utilize registers in the control ASIC 205, and DMA I/O operations triggered by the control ASIC 205 through, for example, the radio configuration DMA data transfer task 223.
• Table 6-1 summarizes the major data elements utilized by the radio services module 217, along with comments.
• the radio services module 217 preferably provides the following operations for configuring or otherwise manipulating radio functionality:
• Synchronization Control a. Acquire Slot (clears synchronization and searches for the next good receive slot by, e.g., finding the next receive preamble). b. Synchronize Slot (locks onto the next good receive slot) c. Synchronize DSP (issues DSP synchronization pulse on a slot)
• Timing Chain Control selects radio timing chain
• Load CDMA Configuration loads the DRA with the currently selected configuration set parameters, including receive frequency, receive code, receive preamble, transmit frequency, transmit code, and transmit preamble)
• Load Static Configuration loads the DRA with "static" parameters, including detect/track threshold, ratchet notch threshold, and synchronization offset
• the DSP object manager 215 defines and coordinates updates to the DSP objects 216.
• the DSP object manager 215 preferably treats the DSP/vocoder at an "object" level.
• a DSP object 216 comprises, in one aspect, a block of data with an associated identifier, while the "external" DSP driver 251 actually updates the bit-level controls and interprets the bit-level status flags of the DSP/vocoder.
• the DSP object manager 215 invokes the DSP driver 251 to create, initialize, and destroy DSP objects 216, and accepts updates to the control and status blocks of DSP objects 216.
• the DSP object manager 215 is executed upon demand and preferably has no knowledge of timing requirements.
• the DSP objects 216 which are managed serve as a central synchronization point for the DSP driver 251 (which updates DSP/vocoder control information asynchronously upon demand) and the slot manager 211 (which updates DSP/vocoder status information after the receive frame of an active bearer traffic slot).
• the ARQ service module 220 of the software control system 201 provides error detection, error recovery, error notification, and message sequencing based upon the ARQ mechanism implemented in the bearer packets.
• the ARQ service module 220 is invoked after the receive frame of a time slot but before the transmit frame of the associated time slot, so that a request to re-send the last received packet can be sent to the base station before the next packet is sent.
• the ARQ service module 220 may functionally separated into two state machines, one for receive ARQ and one for transmit ARQ.
• Figure 14 is a diagram of a state table 1401 illustrating the functional behavior of the ARQ service module 220. In Fig.
• Msg CRC Status represents the error status as derived from a cyclic redundancy check (CRC); "RX Msg#” indicates whether or not the base station message's "TX Msg#” matched the expected value (i.e., whether the received message both is and was expected to be either the "same” message or “next” message); “RX ACK” indicates whether an acknowledge (ACK) or non-acknowledge ("NAK”) message was received from the base station 104; “Special Msg?" indicates whether the message is of a type which will not cause the RX Msg# to be promoted; “TX ACK” indicates whether an ACK or NAK message will be returned to the base station 104; “TX Msg#” indicates whether the user station 301 will transmit the same data packet as previously sent or a new data packet; and "Next Expected RX Msg#” indicates whether the next received frame from the base station 104 should constitute the same data packet as previously received or a new data packet.
• the receive ARQ state machine in the ARQ service module 220 is generally responsible for filtering duplicate messages from the base station 104.
• the base station 104 may, for example, send duplicate messages when it has not received an ACK from the user station 301 to its previously transmitted message.
• Duplicate messages are filtered by the receive ARQ state machine by examining the "RX Msg#" bit of the message (i.e., data packet) received from the base station 104. If the "RX Msg#" bit matches the "Expected Msg#", then the message is considered valid and is processed; otherwise, the message is considered a duplicate message and is discarded.
• CT-HLD control traffic hold
• CT-SPO control traffic specific poll
• the "RX Msg#" is not promoted at the user station 301.
• the user station 301 processes these special messages even though the "RX Msg#” may not match the "Expected Msg#.”
• the user station 301 will accept any value for the "RX Msg#” when initially being paged.
• the user station 301 After initially responding to the general poll control traffic message (CT-GPO) from the base station 104, the user station 301 will begin keeping track of the "RX Msg#" from the base station 104 on an ongoing basis.
• CT-GPO general poll control traffic message
• the receive ARQ state machine of the ARQ service module 220 is also responsible for promoting the user station's "TX Msg#", based on the ACK/NAK value of the ARQ field in the data packet received from the base station 104.
• the base station 104 acknowledges receipt of a user station message by setting the "ACK" bit in the ARQ field of a message to the user station 301, the user station 301 promotes the "TX Msg#" (if it has new data to transmit) and then transmit the new data and promoted "TX Msg#" in the next message to the base station 104.
• the transmit ARQ state machine of the ARQ service module 220 is responsible for informing the base station 104 whether or not a particular message was received successfully at the user station 301, by sending an "ACK” or "NAK as appropriate in the next message transmitted by the user station 301.
• the transmit ARQ state machine is also responsible for indicating to the higher layers (in ISO terminology) that a message transmitted by the user station 301 was or was not successfully received at the base station 104, as indicated by the ACK/NAK value in the ARQ field of a received message.
• the user station 301 may perform a cyclic redundancy check (CRC) to determine whether the message was received with errors.
• CRC cyclic redundancy check
• the CRC status of the message received at the user station 301 generally impacts both the transmit ARQ state machine and the receive ARQ state machine of the ARQ service module 220, as indicated, for example, by the state table shown in Fig. 14.
• Messages received at the user station 301 have both "header CRC" and "frame CRC.” If the header CRC is good, then, regardless of the frame CRC, the header is deemed to contain valid information that may be processed by the user station 301. For example, if the user station 301 receives a message with good header CRC but with a bad frame CRC, and with the ACK bit set, the user station 301 may subsequently transmit a new message because it knows that its last transmitted message has been successfully received at the base station 104 (by virtue of the ACK bit being set). The D and B channels of the received message, however, are ignored because the bad frame CRC indicating that the packet contains errors. Therefore, the user station 301 will transmit a "NAK" with regard to the received message, and will discard the received message.
• the power control service module 221 of the software control system 201 controls the transmit power level of the radio transceiver 305 of the user station 301 based upon a power control mechanism implemented in the header of the data packets transmitted between the user station 301 and the base station 104.
• the power control service module 221 is preferably invoked after a receive frame of a time slot but before the next transmit frame of the associated time slot, so as to allow for closed loop power control of the user station 301 by the base station 104.
• the user station 301 adjusts its transmit power in response to a power control field (i.e., a set of bits) contained in the header of base station messages, as per the Table 7-1 below.
• Table 7-1 i.e., a set of bits
• the user station's transmit power level is "soft-limited" in that, when at the highest or lowest transmit power level, an increase or decrease request, respectively, will have no affect upon the transmit power level.
• control section 1501 depicted in Fig. 15.
• control section 1501 and specifically the control ASIC 1502 thereof, comprises registers having functions and access modes as given by the information appearing in Table 8-1 below.
• the Slot Map Pointer Register (0E01AH) provides a target address for sending the slot map pointer data to the radio interface circuitry.
• the microcontroller 1505 wants to indicate the next time slot for transmission by the radio, the microcontroller 1505 writes a new value to the Slot Map Pointer Register.
• the data is then read by the radio interface circuitry (including, e.g., the RIF ASIC 1514) to determine the next time slot to operate in.
• the Slot Map Pointer Register definition is as follows:
• the Linearizer Register (0E019H) acts as the control port to and from the linearizer ASIC 1513.
• the microcontroller 1505 desires to send control commands or data to the linearizer ASIC 1513, it writes a byte to the Linearizer Register.
• the linearizer interface circuitry in the OTA LCA 1502 transmits the command/data to the linearizer ASIC 1513. If the command issued is a read command, information stored in the Linearizer Register is read, but only bits 5-0 are considered valid.
• the register definition is as follows:
• the Test Register (0E018H) defines various test modes that the OTA LCA may be placed into by the controller.
• the register definition is as follows: ADDRESS: 0E018H
• the General Status Register (0E017H) contains bit specific status information relating to certain events that may cause the microcontroller 1505 to be interrupted.
• the microcontroller 1505 receives a general status interrupt, it responds by reading the General Status Register to determine the reason for the interrupt.
• the OTA LCA 1502 clears the status bit(s) to ensure that the data present in the register always indicates the true reason for an interrupt. Initial condition is set to '0' for all bits.
• the register definition is as follows:
• Bit 1 COMPARE ERROR - Indicates that the compare sequence did not match on all bytes that were compared.
• RXCMPLT Receive complete - Indicates that the reception of data in the receive portion of a slot has completed.
• Bit 7 KEY PRS-RLS - Keypad pressed or released- When an interrupt occurs and this bit is set, it indicates that the keypad has been pressed. When the controller is interrupted a second time with this bit active, it indicates that the keypad has been released.
• the Interrupt Control Register (0E016H) defines when and if the OTA LCA 1502 will generate interrupts to the microcontroller 1505 upon specified conditions. Initial conditions are set to '0' for all bits.
• the register definition is as follows:
• Bit 0 INTCMPC - Interrupt on compare complete - Indicates to the OTA LCA that a general status interrupt should be issued at end of compare sequence (error or no error).
• Bit 2 LNTRRCRL - Interrupt on RC circuit roll over - Indicates to the ⁇ C that the RC long timer counter had rolled over. This may be used for a long duration counter and allow the controller to be awakened periodically over long durations.
• the Command Compare Input Register (0E015H) causes a command template and mask pair to perform a compare operation. This register provides the target address for writing the command template and mask to the compare circuitry.
• the microcontroller 1505 in response to a PEC interrupt, will write the data byte first, then on the next PEC interrupt will write the mask for the data to this address.
• the compare circuitry of the OTA LCA 1502 stores the data appropriately.
• the register definition for the Command Compare Input Register is as follows:
• Bits 7-0 DATAx - The data or mask value for a single compare operation.
• the Compare Count Register (0E014H) defines a number of receive bytes to compare during a command template/mask compare sequence.
• the microcontroller 1505 writes to the Compare Count Register to control the number of receive bytes to compare
• the DSP Data/Control Bytes Register (0E013H) is used in conjunction with operations relating to the DSP/vocoder 1510.
• encoded data is sent to the DSP/vocoder 1510 for decoding.
• the data generally consists of bearer data and DSP control information.
• the OTA LCA 1502 utilizes PEC requests to retrieve the stored information, one byte at a time.
• the microcontroller 1505 writes the data and control bytes to the DSP Data/Control Bytes Register for transmission to the DSP/vocoder 1510.
• the register definition is as follows:
• the DSP Source Register (0E012H) provides the mechanism for moving DSP encoded data and status bytes into the SRAM transmit buffer 1707 (see Fig. 17). After the DSP/vocoder 1510 has encoded data for transmission, the encoded data is sent to the OTA LCA 1502, and PEC requests are then made to have the encoded data placed in the SRAM transmit buffer 1707. When the microcontroller 1505 places information in the DSP Source Register, the OTA LCA 1502 thereafter places the data on the system bus 1530 for writing into the SRAM 1524.
• the register definition is as follows: ADDRESS: 0E012H
• the Receive Source Register (0E011H) provides the address and data for read operations associated with data received over the link with the base station 104.
• the OTA LCA 1502 makes PEC requests to have data stored to the SRAM receive buffer 1706.
• the OTA LCA 1502 responds with the newly received data to be placed in the SRAM receive buffer 1706.
• the register definition is as follows:
• the Transmit Destination Register (OEOIOH) provides a target address for PECs associated with transmission of data over the communication link with the base station 104.
• OEOIOH The Transmit Destination Register
• the Sleep Control Register (0E00FH) defines the sleep control settings for the OTA LCA 1502 to the microcontroller 1505 and other hardware or peripherals.
• the OTA LCA 1502 clears (i.e., resets) the two controller power saving mode bits of the Sleep Control Register. If both modes are active, the mode with the greatest power savings will prevail.
• the microcontroller 1505 is in charge of turning off the CODEC 1511, DSP/vocoder 1510, linearizer ASIC 1513 and the digital radio ASIC (DRA) as needed.
• the register definition is as follows:
• Bit 0 ⁇ C PWRDWN - Indicates that the controller is going into power down mode and that the OTA LCA 1502 should reduce the controller clock to 0 Hz (set by microcontroller, cleared by OTA LCA).
• Bit 1 ⁇ C STNDBY - Indicates that the microcontroller is going into its standby mode and that the OTA LCA 1502 should reduce the clock to the minimum frequency (set by controller, cleared by OTA LCA).
• Bit 3 CODEC SLEEP - Instructs the OTA LCA 1502 to place the CODEC in sleep mode (cleared and set by controller).
• ASIC DAAin sleep mode (cleared and set by controller).
• Bit 5 LINEARIZER ASIC SLP Instructs the OTA LCA 1502 to place the linearizer ASIC 1513 in sleep mode (cleared and set by controller).
• the Reset Register (0E00EH) is a read and write register which provides the microcontroller 1505 with reset control for several circuit blocks and external devices.
• the register definition is as follows:
• the Receive Status Register (0E00DH) indicates the type of error condition when data is received from the radio transceiver 305 in error.
• the microcontroller 1505 may be informed of an error through a general status interrupt and, in response, may choose to read the Receive Status Register to determine the nature of the error.
• the register definition is as follows:
• the RSSI Byte 1 & 2 Register (0E00CH) stores RSSI information.
• the RSSI bytes are preferably stored for each receive frame along with the header type. This allows the microcontroller 1505 to determine the signal strength.
• the microcontroller performs two reads from the RSSI Byte 1 & 2 Register. The first read obtains the first received RSSI byte (average), and the second read obtains the second received byte (difference).
• the RSSI Byte 1 & 2 Register contains the value of the last RSSI byte received, except upon power up.
• the hardware within the OTA LCA 1502 performs multiplexing of the internal RSSI register to the RSSI Byte 1 & 2 Register in the appropriate manner. To ensure that the RSSI read function in the OTA LCA 1502 hardware does not get out of sequence, both bytes should be consecutively read.
• the register definition is as follows:
• the SYNC Byte 1 & 2 Register (0E00BH) provides access to synchronization information used in conjunction with the DSP/vocoder 1510.
• the OTA LCA 1502 writes two synchronization bytes to the DSP/vocoder 1510. These two bytes are "static" and, as they may present a problem to PEC flow, are stored within the OTA LCA 1502.
• the microcontroller 1505 writes the sync bytes in two successive writes to the SYNC Byte 1 & 2 Register.
• the first write transfers the first sync byte to be sent to the DSP/vocoder 1510, while the second write transfers the second sync byte to be sent to the DSP/vocoder 1510.
• the hardware within the OTA LCA 1502 performs appropriate multiplexing to the two SYNC registers internal to the OTA LCA 1502.
• the register definition is as follows: ADDRESS: 0E00BH
• Bits 7-0 SYNCx - May be synchronization byte 1 or 2 depending on which write. 'Value'- Sync byte.
• the SIM Transmit Count Register (0E008H) controls interactions with the SIM port 1520.
• the microcontroller 1505 writes to the SIM Transmit Count Register to define how many bytes will be transmitted to the SIM card through the SIM port 1520. After each successful transmission, the value stored in the SIM Transmit Count Register is decremented, until it eventually reaches zero. When that occurs, the SIM port 1520 changes to a receive mode.
• the register definition is as follows:
• the SIM Control Register (0E007H) provides a means of controlling the SIM port 1520 according to the ISO/IEC 7816-3 specification.
• the microcontroller 1505 provides the enable settings and the times at which the settings are to be made. When the microcontroller 1505 initiates a reset operation, some of the information that is returned by the SIM card provides values for the control settings of the SIM port 1520. These setting are written to the SIM Control Register to control communication over the SIM port 1520.
• the register definition is as follows:
• Bit 0 SIMINV - SIM invert data - This bit indicates to the SIM that the data should be inverted prior to transmission. In addition, it instructs the SIM that the data presented to a PEC will be inverted for the read sequence.
• the OTA LCA SIM port will perform the inversion of the data
• Bit 1 PE/O - Parity even or odd - Indicates to the SIM port that the parity generated and checked by the SIM transmitter should be odd or even.
• VCC VCC
• the SIM Transmit Register (0E006H) provides a destination for data writes by the microcontroller 1505 in response to a PEC request for SIM data.
• the OTA LCA 1502 makes a request of the microcontroller 1502, via the peripheral event controller, to retrieve more data to transmit to the SIM card.
• the PEC requests will continue until the SIM Transmit Count Register reaches zero, or a reset occurs.
• the register definition is as follows: __
• the SIM Receive Register (0E006H) provides the source address for data reads by the microcontroller 1505 in response to a PEC request. Data/control information is read in through the SIM port 1520, then placed in the SRAM 1524 through a PEC request in conjunction with the data move by the microcontroller 1505.
• the register definition is as follows:
• Bits 7-0 DATAx - The data value to be read by controller.
• the Linearizer Control Register (0E005H) provides a control mechanism for the Linearizer ASIC 1513.
• the microcontroller 1505 writes to the Linearizer Control Register to set the desired control settings.
• the microcontroller 1505 may also read from this register to determine if the Linearizer ASIC 1513 is busy, or to determine the status of the control settings.
• the register definition is as follows:
• Bit 6 RECMODE - This sets the Linearizer into receive mode. This bit is read and write.
• the Keyresp Register (0E003H) is a read only register which indicates the row of the key that is currently pressed by the user.
• the register definition is as follows:
• Bits 7-0 ROWx - Indicates if a key in that row is depressed.
• the Keypoll Register (0E003H) is a write-only register which allows the microcontroller 1505 to write values to the keypad matrix columns. The microcontroller 1505 is thereby able to detect the key that is currently pressed by the user. For key press identification, the microcontroller 1505 applies a '0' to one column at a time. The microcontroller 1505 reads the values of the rows in the key response register. The columns must be enabled for the values to be written to the keypad.
• the register definition is as follows: ADDRESS: 0E00 SH MSB LSB
• Bits 7-4 COLx - writing a 0 to any bit location will activate the corresponding column in the keypad matrix.
• the Radio Configuration/Slot Map Data Register (0E002H) provides a destination register for radio configuration data that is transferred from flash memory 1525 through PEC operations.
• the register definition is as follows:
• the Radio Configuration Code Register (0E001H) contains instructions to the radio interface line card assembly (RIF LCA) to reconfigure the radio transceiver 305. As the data is retrieved by the RIF LCA, the OTA LCA 1502 issues PEC requests to transfer further data to the RIF LCA.
• the register definition is as follows:
• the General Purpose Register (0E000H) is a write-only register which provides a variety of control functions to several areas of the OTA LCA 1502.
• the register definition is as follows:
• Bits 1-0 Presently unused Bit 2 RSTSIM - Reset SIM port - This signal provides the means to reset the SIM state machine. Generally a reset is attempted when the predefined number of bytes has been received, or a SIM error has occurred.
• the General Purpose Register (0E000H) is a read-only register, which is read by the microcontroller 1505 at any time to determine the current status and/or mode of operation. Generally the General Purpose Register will be read after the OTA LCA 1502 interrupts the microcontroller 1505 and indicates a change of mode.
• the register definition is as follows:
• Bit 0 HANDSFREE ' 1 ' - Handsfree not active '0' - Handsfree kit is attached Bits 2-1 CONFIGx
• the base station 104 and user stations 102 communicate using spread spectrum communication.
• Each of the embodiments previously described can be configured to operate using spread spectrum communication. Suitable spread spectrum transmission and reception techniques are described, for example, in U.S. Patent Nos. 5,016,255, 5,022047 or 5,659,574, each of which is assigned to the assignee of the present invention, and each of which is hereby incorporated as if fully set forth herein.
• Different cells 103 may be assigned different spread spectrum codes (or different sets of spread spectrum codes, from which individual codes may be temporarily assigned to individual user stations 102), thereby obtaining benefits of CDMA techniques.
• different frequencies may also be assigned to different cells 103, in the same or a different repeating pattern than CDMA codes are assigned.

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