Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/12—Mountings, e.g. non-detachable insulating substrates
  • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
  • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
  • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
  • H01L24/19—Manufacturing methods of high density interconnect preforms
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  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
  • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
  • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
  • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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  • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
  • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
  • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
  • H01L2224/241—Disposition
  • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• • H—ELECTRICITY
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  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
  • H01L2224/321—Disposition
  • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
  • H01L2224/732—Location after the connecting process
  • H01L2224/73251—Location after the connecting process on different surfaces
  • H01L2224/73267—Layer and HDI connectors
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  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01005—Boron [B]
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  • H01L2924/01—Chemical elements
  • H01L2924/01006—Carbon [C]
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  • H01L2924/01029—Copper [Cu]
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  • H01L2924/01033—Arsenic [As]
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  • H01L2924/01039—Yttrium [Y]
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  • H01L2924/01—Chemical elements
  • H01L2924/01078—Platinum [Pt]
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  • H01L2924/01—Chemical elements
  • H01L2924/01079—Gold [Au]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01087—Francium [Fr]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
  • H01L2924/097—Glass-ceramics, e.g. devitrified glass
  • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
  • H01L2924/1515—Shape
  • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
  • H01L2924/15165—Monolayer substrate
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
  • H01L2924/1901—Structure
  • H01L2924/1904—Component type
  • H01L2924/19043—Component type being a resistor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/30105—Capacitance
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  • H01L2924/3011—Impedance

Definitions

• the present invention relates to a method and device for buried electronic components, for example semi-conductor chips and passive networks such as resistor arrays or capacitance arrays, providing a simplified connection of the contacts of the component after installation of the electronic component in a substrate or carrier.
• semi-conductor chips and passive networks such as resistor arrays or capacitance arrays
• Most electronic constructions comprise electronic components which are installed on a carrier.
• the purpose of the carrier is among other things to provide mechanical support for the components.
• Common materials for the carrier include glass epoxy material or ceramic material. Examples of common materials are FR-4 or G-10.
• a known way of arranging an electronic component, for example a so-called "bare" chip on a carrier is that the chip is placed in a cavity in the carrier.
• US 5 353 498, US 5 497 033 describe a solution for fixing an electronic component in a cavity in a carrier.
• the device in this document secures the component in a cavity in the carrier by a dielectric surface layer being applied over the carrier and component, after which electrical connections are made from the contact points on the component to contact points on the surface layer.
• the electrical connections consist of metal plating in vias or holes drilled through the surface layer to the contact points on the component. As these vias are drilied after the component and the carrier have been covered by the surface layer, relatively high precision is required when drilling the holes with regard to finding the correct position to drill.
• Another obvious disadvantage of this device is the difficulty in plating inside the holes.
• the thickness of the plating at the bottom of the hole and on the sides of the hole is governed by the depth of the hole at the same time as the plating of circuit paths, etc., on the upper side of the surface layer will be about 20% thicker than the thickness of the plating in the hole.
• This means that the dimension of the circuit paths will be governed by the hole dimension, and it will thus be difficult to obtain a higher density of circuits as a fine pattern cannot be achieved at the same time as satisfactory plating in narrow holes.
• There are in addition certain absolute requirements concerning the hole dimension for which reason the width dimensions of the circuit paths cannot be varied arbitrarily.
• difficulties arise in locating components prior to cutting holes without using expensive and/or complicated methods such as X-rays or index positioning.
• UK Patent application GB 2 313 713 discloses another typical example of the backgrourfd art, which utilizes a chip located in an aperture in a carrier, the chip exhibiting a plurality of bumps.
• the chip, including the bumps, are covered in an insulating layer, and the bumps are subsequently exposed using a laser to drill holes in the covering insulating layer.
• a drawback of this design is the above- mentioned need for high precision in locating the correct positions for the laser.
• the abstract of Japanese patent document JP57-7147 discloses a method of placing a chip provided with connecting bumps in an aperture in a substrate, and subsequently covering the chip and the bumps in a mound of resin. The bumps are then exposed by lapping along with a smooth surface of the substrate, leaving resin only in the aperture.
• Drawbacks of this method are that due to the lapping along with the surface, the bumps cannot protrude out of the aperture above the surface of the substrate, thus degrading the degree of contact possible between the bumps and subsequent circuit patterns or other connections.
• the lapping of two or more materials at the same time may cause contamination between the different materials, thus causing short-circuits, and may also deform the bumps.
• a solid via as in the invention is also mechanically stronger than a via in the form of a hole and provides better cooling of the electronic component on account of its better heat conductivity. It is also possible to have dummy connecting means which only have a cooling function for the component. The contact between via and circuit path during the plating operation is also improved.
• connection of the component by means of connecting means takes place directly on the component by which a better contact is achieved between the connecting means and the contact surface of the component.
• Fig. 1 is a diagrammatic longitudinal section through a device according to
• Fig. 2a is a diagrammatic longitudinal section through a device according to the invention, where a chip is placed in an aperture in a carrier,
• Fig. 2b is a longitudinal section corresponding to Fig. 2a, where a dielectric layer is applied onto the device, and
• Fig. 2c is a longitudinal section corresponding to Figs 2a and 2b, where the circuit paths are applied onto the dielectric layer after exposure of the contact points of the component
• Figs 3a is a longitudinal section corresponding to fig 2b, of an alternative embodiment of the invention
• Fig 3b is a longitudinal section corresponding to fig 2b, of another alternative embodiment of an the invention.
• the method and the device according to the invention make possible the arranging of one or more electronic components 100 on a component carrier 200.
• an electronic component 100 has a number of contact points 110 arranged on a first surface 120 of the electronic component.
• the carrier 200 has a second main surface 210 and a third main surface 220 which are essentially parallel with each other.
• One or more first apertures 230 are arranged in the carrier 200, the depth of the apertures extending from the second main surface 210 towards the third main surface 220.
• the method according to the invention comprises the following stages:
• the connecting means 130 each have a first end 140 connected to one of the contact points 110 and a second end 150 at a distance from the contact point 110.
• the connecting means 130 can consist of already known so-called bumps, whereby chips according to industry standard (flip-chip) can be used.
• the connecting means 130 are to have a suitable diameter or cross-sectional dimension for the contact points and are to have a length which corresponds to stage 3) below.
• the connecting means 130 are to have a length which is such that the thickness of the dielectric layer 300 is slightly less than the total distance from the bottom surface of the aperture 230 to the second end 150 of the connecting means 130.
• the connecting means 130 will thus still protrude beyond the dielectric layer which covers the second main surface 210 of the carrier 200, while the second end 150 of the connecting means will still have been covered by a layer of dielectric material during the covering process.
• the dielectric layer 300 can be applied in liquid form or as a soft laminate.
• the connecting means 130 must not be deformed during application to such an extent that the connection of the second end 150 to the circuit paths 310 cannot be carried out in the required way, that is the connecting means must not be displaced from the required position preventing a good contact from being obtained between the connecting means and the circuit paths.
• Exposure of the second end 150 of the connecting means 130 in the dielectric layer is preferably carried out by means of a surface removing method such as for example grinding, etching or the like, of the surface of the dielectric layer 300.
• the connecting means for example bumps or the like, usually have a pointy second end 150, for which reason the majority of the dielectric material applied to the second end of the connecting means 130 will flow off, leaving a thinner layer of dielectric material than on the second main surface 210 of the carrier.
• the same amount of surface removing that will expose the metal of the second end 150 of the connecting means 130 will leave a layer of dielectric material on the second main surface 210 of the carrier.
• the second end 150 of t ⁇ j , connecting means 130 may be given a sloped or rounded surface, as shown in figs 3a and 3b respectively.
• connection of the second end 150 of the connecting means 130 to circuit paths 310 arranged on the free surface of the dielectric layer 300 This can be carried out by sputtering, plating, wire-bonding or the like.
• Figs 2a to 2c show three different stages in the method described above.
• Fig. 2a shows the electronic component 100 in position in the aperture 230 in the carrier 200.
• Fig. 2b shows the device after the dielectric layer 300 has been applied.
• the dielectric layer can consist, for example, of non-reinforced epoxy with a thickness to suit the size of the connecting means 130, that is either a required layer thickness is chosen and the dimensions of the connecting means 130 are adjusted to suit this dimension or a required size is selected for the connecting means 130 and the thickness of the dielectric layer 300 is adjusted to suit this thickness.
• Fig. 1 shows the electronic component 100 in position in the aperture 230 in the carrier 200.
• Fig. 2b shows the device after the dielectric layer 300 has been applied.
• the dielectric layer can consist, for example, of non-reinforced epoxy with a thickness to suit the size of the connecting means 130, that is either a required layer thickness is chosen and the dimensions of the connecting means 130 are adjusted to suit this dimension or a required size
• 2c shows the device after the second end 150 of the connecting means 130 has been exposed, for example by plasma etching, pumicing or chemical etching, making the second end exposed bright metal after which it can be connected to the circuit paths 310 on the free surface of the dielectric layer 300. Further surface treatment can be carried out on the second end of the connecting means during this stage if necessary, for example nickel plating of gold surfaces on the connecting means before applying copper plating (circuits or de-oxidation, etc).
• the method and device according to the invention have the advantages that no holes need to be made in the dielectric layer and no plating needs to be carried out in holes, i.e. the manufacturing operations are simpler and cheaper.
• the dimensions of the dielectric layer 300 can be varied as desired to alter the impedance of the circuit paths to suit the required application since a thickness can be selected that makes it possible to obtain circuit paths with dimensions which provide the required impedance.
• a layer which can be, in principle, any thickness is thus desirable for impedance-controlled circuit paths.
• the second end of the connecting means is visible for visual positioning after the stage of exposure, which makes the connection to the circuit paths easier during jmanufacture.
• the electronic components can consist of an individual chip and the carrier can consist of a chip housing, whereby the method and device according to the invention can be applied to the manufacture of chips.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Chemical & Material Sciences (AREA)
• Dispersion Chemistry (AREA)
• Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
• Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Applications Claiming Priority (3)

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• 1998
  • 1998-09-21 SE SE9803204A patent/SE514529C2/sv not_active IP Right Cessation
• 1999
  • 1999-09-21 AU AU63799/99A patent/AU6379999A/en not_active Abandoned
  • 1999-09-21 WO PCT/SE1999/001643 patent/WO2000017924A2/en active Application Filing
  • 1999-09-21 EP EP99951342A patent/EP1116268A2/en not_active Withdrawn

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