WO2000017924A2 - Method and device for buried chips - Google Patents

Method and device for buried chips Download PDF

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Publication number
WO2000017924A2
WO2000017924A2 PCT/SE1999/001643 SE9901643W WO0017924A2 WO 2000017924 A2 WO2000017924 A2 WO 2000017924A2 SE 9901643 W SE9901643 W SE 9901643W WO 0017924 A2 WO0017924 A2 WO 0017924A2
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WO
WIPO (PCT)
Prior art keywords
connecting means
carrier
dielectric layer
main surface
contact points
Prior art date
Application number
PCT/SE1999/001643
Other languages
French (fr)
Other versions
WO2000017924A3 (en
Inventor
Leif Bergstedt
Katarina Boustedt
Per Ligander
Original Assignee
Telefonaktiebolaget Lm Ericsson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget Lm Ericsson filed Critical Telefonaktiebolaget Lm Ericsson
Priority to AU63799/99A priority Critical patent/AU6379999A/en
Priority to EP99951342A priority patent/EP1116268A2/en
Publication of WO2000017924A2 publication Critical patent/WO2000017924A2/en
Publication of WO2000017924A3 publication Critical patent/WO2000017924A3/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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Definitions

  • the present invention relates to a method and device for buried electronic components, for example semi-conductor chips and passive networks such as resistor arrays or capacitance arrays, providing a simplified connection of the contacts of the component after installation of the electronic component in a substrate or carrier.
  • semi-conductor chips and passive networks such as resistor arrays or capacitance arrays
  • Most electronic constructions comprise electronic components which are installed on a carrier.
  • the purpose of the carrier is among other things to provide mechanical support for the components.
  • Common materials for the carrier include glass epoxy material or ceramic material. Examples of common materials are FR-4 or G-10.
  • a known way of arranging an electronic component, for example a so-called "bare" chip on a carrier is that the chip is placed in a cavity in the carrier.
  • US 5 353 498, US 5 497 033 describe a solution for fixing an electronic component in a cavity in a carrier.
  • the device in this document secures the component in a cavity in the carrier by a dielectric surface layer being applied over the carrier and component, after which electrical connections are made from the contact points on the component to contact points on the surface layer.
  • the electrical connections consist of metal plating in vias or holes drilled through the surface layer to the contact points on the component. As these vias are drilied after the component and the carrier have been covered by the surface layer, relatively high precision is required when drilling the holes with regard to finding the correct position to drill.
  • Another obvious disadvantage of this device is the difficulty in plating inside the holes.
  • the thickness of the plating at the bottom of the hole and on the sides of the hole is governed by the depth of the hole at the same time as the plating of circuit paths, etc., on the upper side of the surface layer will be about 20% thicker than the thickness of the plating in the hole.
  • This means that the dimension of the circuit paths will be governed by the hole dimension, and it will thus be difficult to obtain a higher density of circuits as a fine pattern cannot be achieved at the same time as satisfactory plating in narrow holes.
  • There are in addition certain absolute requirements concerning the hole dimension for which reason the width dimensions of the circuit paths cannot be varied arbitrarily.
  • difficulties arise in locating components prior to cutting holes without using expensive and/or complicated methods such as X-rays or index positioning.
  • UK Patent application GB 2 313 713 discloses another typical example of the backgrourfd art, which utilizes a chip located in an aperture in a carrier, the chip exhibiting a plurality of bumps.
  • the chip, including the bumps, are covered in an insulating layer, and the bumps are subsequently exposed using a laser to drill holes in the covering insulating layer.
  • a drawback of this design is the above- mentioned need for high precision in locating the correct positions for the laser.
  • the abstract of Japanese patent document JP57-7147 discloses a method of placing a chip provided with connecting bumps in an aperture in a substrate, and subsequently covering the chip and the bumps in a mound of resin. The bumps are then exposed by lapping along with a smooth surface of the substrate, leaving resin only in the aperture.
  • Drawbacks of this method are that due to the lapping along with the surface, the bumps cannot protrude out of the aperture above the surface of the substrate, thus degrading the degree of contact possible between the bumps and subsequent circuit patterns or other connections.
  • the lapping of two or more materials at the same time may cause contamination between the different materials, thus causing short-circuits, and may also deform the bumps.
  • a solid via as in the invention is also mechanically stronger than a via in the form of a hole and provides better cooling of the electronic component on account of its better heat conductivity. It is also possible to have dummy connecting means which only have a cooling function for the component. The contact between via and circuit path during the plating operation is also improved.
  • connection of the component by means of connecting means takes place directly on the component by which a better contact is achieved between the connecting means and the contact surface of the component.
  • Fig. 1 is a diagrammatic longitudinal section through a device according to
  • Fig. 2a is a diagrammatic longitudinal section through a device according to the invention, where a chip is placed in an aperture in a carrier,
  • Fig. 2b is a longitudinal section corresponding to Fig. 2a, where a dielectric layer is applied onto the device, and
  • Fig. 2c is a longitudinal section corresponding to Figs 2a and 2b, where the circuit paths are applied onto the dielectric layer after exposure of the contact points of the component
  • Figs 3a is a longitudinal section corresponding to fig 2b, of an alternative embodiment of the invention
  • Fig 3b is a longitudinal section corresponding to fig 2b, of another alternative embodiment of an the invention.
  • the method and the device according to the invention make possible the arranging of one or more electronic components 100 on a component carrier 200.
  • an electronic component 100 has a number of contact points 110 arranged on a first surface 120 of the electronic component.
  • the carrier 200 has a second main surface 210 and a third main surface 220 which are essentially parallel with each other.
  • One or more first apertures 230 are arranged in the carrier 200, the depth of the apertures extending from the second main surface 210 towards the third main surface 220.
  • the method according to the invention comprises the following stages:
  • the connecting means 130 each have a first end 140 connected to one of the contact points 110 and a second end 150 at a distance from the contact point 110.
  • the connecting means 130 can consist of already known so-called bumps, whereby chips according to industry standard (flip-chip) can be used.
  • the connecting means 130 are to have a suitable diameter or cross-sectional dimension for the contact points and are to have a length which corresponds to stage 3) below.
  • the connecting means 130 are to have a length which is such that the thickness of the dielectric layer 300 is slightly less than the total distance from the bottom surface of the aperture 230 to the second end 150 of the connecting means 130.
  • the connecting means 130 will thus still protrude beyond the dielectric layer which covers the second main surface 210 of the carrier 200, while the second end 150 of the connecting means will still have been covered by a layer of dielectric material during the covering process.
  • the dielectric layer 300 can be applied in liquid form or as a soft laminate.
  • the connecting means 130 must not be deformed during application to such an extent that the connection of the second end 150 to the circuit paths 310 cannot be carried out in the required way, that is the connecting means must not be displaced from the required position preventing a good contact from being obtained between the connecting means and the circuit paths.
  • Exposure of the second end 150 of the connecting means 130 in the dielectric layer is preferably carried out by means of a surface removing method such as for example grinding, etching or the like, of the surface of the dielectric layer 300.
  • the connecting means for example bumps or the like, usually have a pointy second end 150, for which reason the majority of the dielectric material applied to the second end of the connecting means 130 will flow off, leaving a thinner layer of dielectric material than on the second main surface 210 of the carrier.
  • the same amount of surface removing that will expose the metal of the second end 150 of the connecting means 130 will leave a layer of dielectric material on the second main surface 210 of the carrier.
  • the second end 150 of t ⁇ j , connecting means 130 may be given a sloped or rounded surface, as shown in figs 3a and 3b respectively.
  • connection of the second end 150 of the connecting means 130 to circuit paths 310 arranged on the free surface of the dielectric layer 300 This can be carried out by sputtering, plating, wire-bonding or the like.
  • Figs 2a to 2c show three different stages in the method described above.
  • Fig. 2a shows the electronic component 100 in position in the aperture 230 in the carrier 200.
  • Fig. 2b shows the device after the dielectric layer 300 has been applied.
  • the dielectric layer can consist, for example, of non-reinforced epoxy with a thickness to suit the size of the connecting means 130, that is either a required layer thickness is chosen and the dimensions of the connecting means 130 are adjusted to suit this dimension or a required size is selected for the connecting means 130 and the thickness of the dielectric layer 300 is adjusted to suit this thickness.
  • Fig. 1 shows the electronic component 100 in position in the aperture 230 in the carrier 200.
  • Fig. 2b shows the device after the dielectric layer 300 has been applied.
  • the dielectric layer can consist, for example, of non-reinforced epoxy with a thickness to suit the size of the connecting means 130, that is either a required layer thickness is chosen and the dimensions of the connecting means 130 are adjusted to suit this dimension or a required size
  • 2c shows the device after the second end 150 of the connecting means 130 has been exposed, for example by plasma etching, pumicing or chemical etching, making the second end exposed bright metal after which it can be connected to the circuit paths 310 on the free surface of the dielectric layer 300. Further surface treatment can be carried out on the second end of the connecting means during this stage if necessary, for example nickel plating of gold surfaces on the connecting means before applying copper plating (circuits or de-oxidation, etc).
  • the method and device according to the invention have the advantages that no holes need to be made in the dielectric layer and no plating needs to be carried out in holes, i.e. the manufacturing operations are simpler and cheaper.
  • the dimensions of the dielectric layer 300 can be varied as desired to alter the impedance of the circuit paths to suit the required application since a thickness can be selected that makes it possible to obtain circuit paths with dimensions which provide the required impedance.
  • a layer which can be, in principle, any thickness is thus desirable for impedance-controlled circuit paths.
  • the second end of the connecting means is visible for visual positioning after the stage of exposure, which makes the connection to the circuit paths easier during jmanufacture.
  • the electronic components can consist of an individual chip and the carrier can consist of a chip housing, whereby the method and device according to the invention can be applied to the manufacture of chips.

Abstract

A method for arranging one or more electronic components (100) on a carrier (200). The electronic components have a number of contact points (110) arranged on a first surface (120). The carrier has a second main surface (210) and a third main surface (220). In the carrier there are also arranged one or more first apertures (230) with a depth extending from the second main surface towards the third main surface. The method comprises the stages: arranging of connecting means (130) on the contact points, where the connecting means have a first end (140) connected to one of the contact points and a second end (150) at a distance from the contact point, arranging of the electronic components in the apertures in the carrier so that the connecting means are pointed away from the third main surface of the carrier, application of a dielectric layer (300) on the second main surface of the carrier, where the dielectric layer also covers the electronic component, exposure of the second end of the connecting means in the dielectric layer, and connection of the second end of the connecting means to circuit paths (310) arranged on the free surface of the dielectric layer.

Description

TITLE:
Method and device for buried chips
TECHNICAL FIELD:
The present invention relates to a method and device for buried electronic components, for example semi-conductor chips and passive networks such as resistor arrays or capacitance arrays, providing a simplified connection of the contacts of the component after installation of the electronic component in a substrate or carrier.
CURRENT TECHNOLOGY:
Most electronic constructions comprise electronic components which are installed on a carrier. The purpose of the carrier is among other things to provide mechanical support for the components. Common materials for the carrier include glass epoxy material or ceramic material. Examples of common materials are FR-4 or G-10.
A known way of arranging an electronic component, for example a so-called "bare" chip on a carrier is that the chip is placed in a cavity in the carrier. US 5 353 498, US 5 497 033 describe a solution for fixing an electronic component in a cavity in a carrier. The device in this document secures the component in a cavity in the carrier by a dielectric surface layer being applied over the carrier and component, after which electrical connections are made from the contact points on the component to contact points on the surface layer. The electrical connections consist of metal plating in vias or holes drilled through the surface layer to the contact points on the component. As these vias are drilied after the component and the carrier have been covered by the surface layer, relatively high precision is required when drilling the holes with regard to finding the correct position to drill.
Another obvious disadvantage of this device is the difficulty in plating inside the holes. The thickness of the plating at the bottom of the hole and on the sides of the hole is governed by the depth of the hole at the same time as the plating of circuit paths, etc., on the upper side of the surface layer will be about 20% thicker than the thickness of the plating in the hole. This means that the dimension of the circuit paths will be governed by the hole dimension, and it will thus be difficult to obtain a higher density of circuits as a fine pattern cannot be achieved at the same time as satisfactory plating in narrow holes. There are in addition certain absolute requirements concerning the hole dimension for which reason the width dimensions of the circuit paths cannot be varied arbitrarily. In addition, difficulties arise in locating components prior to cutting holes without using expensive and/or complicated methods such as X-rays or index positioning.
UK Patent application GB 2 313 713 discloses another typical example of the backgrourfd art, which utilizes a chip located in an aperture in a carrier, the chip exhibiting a plurality of bumps. The chip, including the bumps, are covered in an insulating layer, and the bumps are subsequently exposed using a laser to drill holes in the covering insulating layer. A drawback of this design is the above- mentioned need for high precision in locating the correct positions for the laser.
The abstract of Japanese patent document JP57-7147 discloses a method of placing a chip provided with connecting bumps in an aperture in a substrate, and subsequently covering the chip and the bumps in a mound of resin. The bumps are then exposed by lapping along with a smooth surface of the substrate, leaving resin only in the aperture. Drawbacks of this method are that due to the lapping along with the surface, the bumps cannot protrude out of the aperture above the surface of the substrate, thus degrading the degree of contact possible between the bumps and subsequent circuit patterns or other connections. In addition, the lapping of two or more materials at the same time may cause contamination between the different materials, thus causing short-circuits, and may also deform the bumps.
SUMMARY OF THE INVENTION:
It is therefore a general aim of this invention to provide a method and a device for buried electronic components where the time-consuming and complicated cutting of holes between the upper surface of the outer layer and the contact points of the component is eliminated.
These aims are achieved according to the present invention by means of a method for arranging one or more electronic components on a carrier, where the said electronic components have a number of contact points arranged on a first surface of the said electronic component, and where the said carrier has a second main surface and a third main surface, and in which said carrier there are arranged one or more first apertures with a depth extending from the said second main surface towards the said third main surface, where the said method is characterized by the stages: arranging of connecting means on said contact points, where said connecting means have a first end connected to said contact points and a second end at a distance from said contact points, arranging of said electronic component in said aperture in said carrier so that said connecting means are pointed away from said third main surface of said carrierJ giving said connecting means such an extension in the direction of the depth of the aperture that they protrude beyond the second main surface of the carrier, application of a layer of dielectric material on said second main surface of said carrier, where said dielectric layer also covers said electronic component, with such a thickness of the dielectric layer that the connecting means still protrude beyond the dielectric layer covering said second main surface of said carrier, and the second end of the connecting means being covered by dielectric material, exposure by means of a surface removing method of said second end of said connecting means in said dielectric layer, and connection of said second end of said connecting means to circuit paths arranged on the free surface of said dielectric layer.
By means of the method and device according to the invention, a cheaper and simpler method of arranging electronic components on a carrier is thus achieved. In addition, it is possible to detect on the surface of the carrier where a component is situated after the application of the dielectric layer and exposure of the second end of the connecting means. This solution also provides greater freedom of choice regarding the dimension (width) of the circuit paths. A solid via as in the invention is also mechanically stronger than a via in the form of a hole and provides better cooling of the electronic component on account of its better heat conductivity. It is also possible to have dummy connecting means which only have a cooling function for the component. The contact between via and circuit path during the plating operation is also improved. As cleaning after making the holes is no longer needed, this operation is completely omitted (it is also very difficult to clean completely). In addition the connection of the component by means of connecting means takes place directly on the component by which a better contact is achieved between the connecting means and the contact surface of the component.
Preferred embodiments according to this invention are described in the dependent claims. BRIEF DESCRIPTION OF THE FIGURES:
In the following, the invention will be described in greater detail utilizing examples of preferred embodiments and with reference to the attached figures, where:
Fig. 1 is a diagrammatic longitudinal section through a device according to
* known technology,
Fig. 2a is a diagrammatic longitudinal section through a device according to the invention, where a chip is placed in an aperture in a carrier,
Fig. 2b is a longitudinal section corresponding to Fig. 2a, where a dielectric layer is applied onto the device, and
Fig. 2c is a longitudinal section corresponding to Figs 2a and 2b, where the circuit paths are applied onto the dielectric layer after exposure of the contact points of the component, and Figs 3a is a longitudinal section corresponding to fig 2b, of an alternative embodiment of the invention, and Fig 3b is a longitudinal section corresponding to fig 2b, of another alternative embodiment of an the invention.
PREFERRED EMBODIMENTS:
The method and the device according to the invention make possible the arranging of one or more electronic components 100 on a component carrier 200. As is shown in Figs 2a to 2c, an electronic component 100 has a number of contact points 110 arranged on a first surface 120 of the electronic component. The carrier 200 has a second main surface 210 and a third main surface 220 which are essentially parallel with each other. One or more first apertures 230 are arranged in the carrier 200, the depth of the apertures extending from the second main surface 210 towards the third main surface 220.
The method according to the invention comprises the following stages:
1) Arranging of connecting means 130 on the contact points 110. The connecting means 130 each have a first end 140 connected to one of the contact points 110 and a second end 150 at a distance from the contact point 110. The connecting means 130 can consist of already known so-called bumps, whereby chips according to industry standard (flip-chip) can be used. The connecting means 130 are to have a suitable diameter or cross-sectional dimension for the contact points and are to have a length which corresponds to stage 3) below.
2) Arranging of the electronic component 100 in an aperture 230 in the carrier 200 sotøat the connecting means 130 are pointed away from the third main surface 220 of the carrier 200. The total distance from the bottom surface of the aperture 230 to the second end 150 of the connecting means 130 is to correspond to stage 3) below. The length of the connecting means 130 should be such that they protrude beyond the second main surface 210 of the carrier.
3) Application of a dielectric layer 300 on the second main surface 210 of the carrier 200, where the dielectric layer 300 also covers the electronic component 100. The connecting means 130 are to have a length which is such that the thickness of the dielectric layer 300 is slightly less than the total distance from the bottom surface of the aperture 230 to the second end 150 of the connecting means 130. The connecting means 130 will thus still protrude beyond the dielectric layer which covers the second main surface 210 of the carrier 200, while the second end 150 of the connecting means will still have been covered by a layer of dielectric material during the covering process.
The dielectric layer 300 can be applied in liquid form or as a soft laminate. The connecting means 130 must not be deformed during application to such an extent that the connection of the second end 150 to the circuit paths 310 cannot be carried out in the required way, that is the connecting means must not be displaced from the required position preventing a good contact from being obtained between the connecting means and the circuit paths.
4) Exposure of the second end 150 of the connecting means 130 in the dielectric layer. This is preferably carried out by means of a surface removing method such as for example grinding, etching or the like, of the surface of the dielectric layer 300. The connecting means, for example bumps or the like, usually have a pointy second end 150, for which reason the majority of the dielectric material applied to the second end of the connecting means 130 will flow off, leaving a thinner layer of dielectric material than on the second main surface 210 of the carrier. Thus, the same amount of surface removing that will expose the metal of the second end 150 of the connecting means 130 will leave a layer of dielectric material on the second main surface 210 of the carrier.
If it is desired to insure an extra degree of safety regarding the flowing-off of dielectric material from the second end of the connecting means, the second end 150 of t βj, connecting means 130 may be given a sloped or rounded surface, as shown in figs 3a and 3b respectively.
5) Connection of the second end 150 of the connecting means 130 to circuit paths 310 arranged on the free surface of the dielectric layer 300. This can be carried out by sputtering, plating, wire-bonding or the like.
Figs 2a to 2c show three different stages in the method described above. Fig. 2a shows the electronic component 100 in position in the aperture 230 in the carrier 200. Fig. 2b shows the device after the dielectric layer 300 has been applied. The dielectric layer can consist, for example, of non-reinforced epoxy with a thickness to suit the size of the connecting means 130, that is either a required layer thickness is chosen and the dimensions of the connecting means 130 are adjusted to suit this dimension or a required size is selected for the connecting means 130 and the thickness of the dielectric layer 300 is adjusted to suit this thickness. Fig. 2c shows the device after the second end 150 of the connecting means 130 has been exposed, for example by plasma etching, pumicing or chemical etching, making the second end exposed bright metal after which it can be connected to the circuit paths 310 on the free surface of the dielectric layer 300. Further surface treatment can be carried out on the second end of the connecting means during this stage if necessary, for example nickel plating of gold surfaces on the connecting means before applying copper plating (circuits or de-oxidation, etc).
The method and device according to the invention have the advantages that no holes need to be made in the dielectric layer and no plating needs to be carried out in holes, i.e. the manufacturing operations are simpler and cheaper. With the use of electronic components already provided with connecting means 130 before being buried in the carrier, on-going testing of the electronic components prior to installation is made easier. The dimensions of the dielectric layer 300 can be varied as desired to alter the impedance of the circuit paths to suit the required application since a thickness can be selected that makes it possible to obtain circuit paths with dimensions which provide the required impedance. A layer which can be, in principle, any thickness is thus desirable for impedance-controlled circuit paths.
In addition, the second end of the connecting means is visible for visual positioning after the stage of exposure, which makes the connection to the circuit paths easier during jmanufacture.
The invention is not limited to the embodiments described above but can be varied freely within the scope of the following patent claims. For example, the electronic components can consist of an individual chip and the carrier can consist of a chip housing, whereby the method and device according to the invention can be applied to the manufacture of chips.

Claims

PATENT CLAIMS:
1. A method for arranging one or more electronic components (100) on a component carrier (200), where said electronic component has a number of contact points (110) arranged on a first surface (120) of said electronic component, and where saϊd*- carrier has a second main surface (210) and a third main surface (220), and in which said carrier are arranged one or more first apertures (230) with a depth extending from said second main surface towards said third main surface, where said method is c h a r a c t e r i z e d b y the stages: arranging of connecting means (130) on said contact points (110), where said connecting means have a first end (140) connected to said contact points and a second end (150) at a distance from said contact points, arranging of said electronic component in said aperture in said carrier so that said connecting means are pointed away from said third main surface of said carrier, giving said connecting means (130) such an extension in the direction of the depth of the aperture (230) that they protrude beyond the second main surface
(210) of the carrier, application of a layer (300) of dielectric material on said second main surface of said carrier, where said dielectric layer also covers said electronic component, with such a thickness of the dielectric layer (300) that the connecting means (130) still protrude beyond the dielectric layer covering said second main surface of said carrier, and the second end (150) of the connecting means being covered by dielectric material (300), exposure by means of a surface removing method of said second end (150) of said connecting means (130) in said dielectric layer (300), and connection of said second end (150) of said connecting means (130) to circuit paths (310) arranged on the free surface of said dielectric layer.
2. Method according to claim 1 , in which said second end (150) of the connecting means (130) is given a sloped surface.
3. Method according to claim 1 , in which said second end (150) of the connecting means (130) is given a rounded surface.
4. Method according to any of claims 1-3, c h a r a c t e r i z e d i n that said connecting means (130) comprise bumps.
5. Method according to any of claims 1-4, characterized in that said dielectric layer (300) is applied by applying the dielectric material for said dielectric layer in liquid form.
6. Method according to any of claims 1-4, characterized in that said dielectric layer (300) is applied by application of the dielectric material for said dielectric layer in the form of a soft laminate so that said connecting means (130) are not deformed to such an extent that the connection of said second end (150) to said circuit paths (310) cannot be carried out in the required way.
7. Method according to any of claims 1-4, characterized in that said dielectric layer (300) comprises non-reinforced epoxy.
8. Method according to any of claims 1-7, characterized in that the exposure of said second end (150) is carried out by any of the methods plasma etching, pumicing or chemical etching.
9. Method according to any of claims 1-8, characterized in that said method further comprises a surface treatment of the second end (150) of said connecting means (130) after exposure of said second end.
10. Electronic device (1) comprising one or more electronic components (100) and one or more component carriers (200), where said electronic components are arranged on said carrier according to the method of any of claims 1-9.
PCT/SE1999/001643 1998-09-21 1999-09-21 Method and device for buried chips WO2000017924A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU63799/99A AU6379999A (en) 1998-09-21 1999-09-21 Method and device for buried chips
EP99951342A EP1116268A2 (en) 1998-09-21 1999-09-21 Method and device for buried chips

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9803204A SE514529C2 (en) 1998-09-21 1998-09-21 Method and apparatus for buried electronics components
SE9803204-8 1998-09-21

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WO2000017924A2 true WO2000017924A2 (en) 2000-03-30
WO2000017924A3 WO2000017924A3 (en) 2000-08-17

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Publication number Priority date Publication date Assignee Title
US6690583B1 (en) 1999-05-19 2004-02-10 Telefonaktiebolaget Lm Ericsson (Publ) Carrier for electronic components
WO2012011933A1 (en) 2010-07-23 2012-01-26 Tessera, Inc. Microelectronic elements with post-assembly planarization

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Publication number Priority date Publication date Assignee Title
JPS577147A (en) * 1980-06-17 1982-01-14 Citizen Watch Co Ltd Mounting construction of semiconductor device
GB2313713A (en) * 1996-05-31 1997-12-03 Nec Corp High-density mounting method for and structure of electronic circuit board
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577147A (en) * 1980-06-17 1982-01-14 Citizen Watch Co Ltd Mounting construction of semiconductor device
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
GB2313713A (en) * 1996-05-31 1997-12-03 Nec Corp High-density mounting method for and structure of electronic circuit board

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Title
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See also references of EP1116268A2 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6690583B1 (en) 1999-05-19 2004-02-10 Telefonaktiebolaget Lm Ericsson (Publ) Carrier for electronic components
WO2012011933A1 (en) 2010-07-23 2012-01-26 Tessera, Inc. Microelectronic elements with post-assembly planarization
US9659812B2 (en) 2010-07-23 2017-05-23 Tessera, Inc. Microelectronic elements with post-assembly planarization
EP2596689A4 (en) * 2010-07-23 2017-07-26 Tessera, Inc. Microelectronic elements with post-assembly planarization
US9966303B2 (en) 2010-07-23 2018-05-08 Tessera, Inc. Microelectronic elements with post-assembly planarization
US10559494B2 (en) 2010-07-23 2020-02-11 Tessera, Inc. Microelectronic elements with post-assembly planarization

Also Published As

Publication number Publication date
SE9803204L (en) 2000-03-22
AU6379999A (en) 2000-04-10
SE9803204D0 (en) 1998-09-21
EP1116268A2 (en) 2001-07-18
WO2000017924A3 (en) 2000-08-17
SE514529C2 (en) 2001-03-05

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