EP1114450A1 - Systeme et procede de metallisation d'un motif conducteur - Google Patents

Systeme et procede de metallisation d'un motif conducteur

Info

Publication number
EP1114450A1
EP1114450A1 EP99936188A EP99936188A EP1114450A1 EP 1114450 A1 EP1114450 A1 EP 1114450A1 EP 99936188 A EP99936188 A EP 99936188A EP 99936188 A EP99936188 A EP 99936188A EP 1114450 A1 EP1114450 A1 EP 1114450A1
Authority
EP
European Patent Office
Prior art keywords
substrate
contact
conductive pattern
plating
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99936188A
Other languages
German (de)
English (en)
Inventor
Filip Van Steenkiste
Kris Baert
Walter Gumbrecht
Philippe Arquint
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
INTERUNIVERSITAIRE MICROELEKTR
Interuniversitair Microelektronica Centrum vzw IMEC
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INTERUNIVERSITAIRE MICROELEKTR, Interuniversitair Microelektronica Centrum vzw IMEC, Siemens AG filed Critical INTERUNIVERSITAIRE MICROELEKTR
Publication of EP1114450A1 publication Critical patent/EP1114450A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to methods and systems for plating conductive patterns.
  • a plurality of components being active devices as well as passive devices are processed on a surface of a semiconductor wafer for instance to form an integrated circuit.
  • metallization structures are requested both as a part of the aforementioned devices and to interconnect these devices.
  • the formation of such metallization structures includes the plating of a conductive pattern, being part of a metallization structure and being formed at a first surface of a substrate, such as a wafer. Particularly this first surface can be the front side or the back side of the wafer.
  • the plating solution must be in contact with the first surface of the substrate comprising the conductive patterns to be plated and two electrically connectable electrodes have to be provided.
  • the first electrode is immersed in the plating solution, while the second electrode has to be electrically connected to the conductive patterns to be plated.
  • State-of-the-art plating techniques usually contact peripheral regions of the first surface of a substrate, comprising the conductive patterns to be plated. These peripheral contact regions are electrically connected to the second electrode as well as to the conductive patterns to be plated.
  • a problem is that often long metal lines are required to connect each conductive pattern to be plated with the contact in the peripheral region. Particularly, this is a problem when one wants to perform plating on wafer scale because the differences in distance between conductive patterns to be plated being located near the edges of the wafer and in the center of the wafer are huge. These differences are typically in the centimeter range. Consequently also the differences in resistance of the metal lines connecting the respective conductive patterns can be huge. This often results in a highly non-uniform plating process. All these metal connections between the conductive patterns to be plated and the peripheral regions can not be easily removed after the plating process and moreover, a lot of wafer-area is required to provide these connections thereby inhibiting dense integration.
  • Another problem is that the contact means in the peripheral regions are exposed to the plating solution. These contact means become parasitically plated and have to be cleaned regularly. A further problem can arise if the contact means do not simultaneously can be used as sealing means, then extra sealing means are required. These sealing means should then be positioned between the contact means and the edges of the wafer in order to avoid leakage of the plating solution to another surface of the wafer. Consequently, this leads again to a further decrease of the available area which can be plated.
  • the invention presents methods and systems for plating conductive patterns which at least result in a high uniformity and avoid parasitical plating effects.
  • a plating system for plating on a plurality of conductive patterns formed at a surface of a substrate.
  • a plating solution is applied on this surface and the exposure of other surfaces of the substrate to the plating solution is inhibited.
  • a first electrode of the system is immersed in the plating solution while the second electrode is in contact with another surface of the substrate.
  • the conductive patterns to be plated are temporary electrically connected with the second electrode resulting in a uniform and selective deposition over the exposed surface of the substrate.
  • a system for plating on at least one conductive pattern, said conductive pattern being positioned at a first surface of a substrate having at least a first surface and a second surface, said system comprising : a support with an electrically connectable electrode thereon; a sealing element to inhibit the exposure of the second surface of the substrate to a plating solution; and wherein said substrate is placeable on said support such that said electrode is in contact with said second surface of said substrate and wherein a contact to said first surface of said substrate is provided, said conductive pattern being temporary electrically connected with said contact and said contact being electrically connected with said electrode.
  • a substrate having at least a first surface and a second surface opposite to said first surface, said first surface being exposable to a plating solution, said substrate comprising a conductive pattern being positioned at said first surface of a substrate; a contact to the first surface of the substrate; and said conductive pattern being temporary electrically connected by a polysilicon or an amorphous silicon conductor with said contact and said contact being electrically connected with said second surface.
  • a method for plating on at least one conductive pattern formed at a surface of a substrate, said substrate having at least a first surface and a second surface, said method comprising the steps of: placing the substrate on an electrode being part of a plating holder such that said second surface of said substrate is in contact with said electrode and said conductive pattern is temporary electrically connected to said conductive pattern; and applying a plating solution on said first surface of said substrate thereby inhibiting exposure of said second surface to said plating solution.
  • Figure 1 shows a plurality of structures to be plated. Each one of said plurality of structures (with boundary (2)) is connected to a polysilicon stripe which crosses the dicing line (1) .
  • Figure 2 shows a metal (3) of a first die and a second die, being adjacent.
  • the polysilicon stripe (4) extends from said metal (3) over the dicing line (1) and is further connected to the substrate contact (5) on said second die .
  • Figure 3 shows a system for plating, comprising of a plating holder with a backside contact.
  • Means for sealing (6) , preventing the second surface of the wafer being exposed to the plating solution are foreseen.
  • a backside contact means is also present.
  • Figure 4 shows a cross-section view of the polysilicon stripes. Dicing over the polysilicon stripe, results in disconnecting the electroplated structures from the substrate contact .
  • Figure 5 shows a top vies of the polysilicon stripes .
  • a plating system for plating on a plurality of conductive patterns formed at a surface of a substrate.
  • a plating solution is applied on this surface and the exposure of other surfaces of the substrate to the plating solution is inhibited.
  • a first electrode of the system is immersed in the plating solution while the second electrode is in contact with another surface of the substrate.
  • the conductive patterns to be plated are temporary electrically connected with the second electrode resulting in a uniform and selective deposition over the exposed surface of the substrate.
  • a system for plating on at least one conductive pattern, said conductive pattern being positioned at a first surface of a substrate having at least a first surface and a second surface, said system comprising: a support with an electrically connectable electrode thereon; a sealing element to inhibit the exposure of the second surface of the substrate to a plating solution; and where said substrate is placeable on said support such that said electrode is in contact with said second surface of said substrate and wherein a contact to said first surface of said substrate is provided, said conductive pattern being temporary electrically connected with said contact and said contact being electrically connected with said electrode.
  • the electrical connection between the contact at the first surface of the substrate and the electrode at the second surface of the substrate can be a doped semi-conductive region of either an n-type conductivity or a p-type conductivity, or a metal via connection extending from the first surface to the second surface of the substrate.
  • a metal contact can be provided at the second surface of the substrate .
  • a system for plating on a plurality of conductive patterns formed at a surface of a substrate.
  • Each conductive pattern to be plated is temporary electrically connected with a contact to the first surface of the substrate by a polysilicon conductor or an amorphous silicon conductor.
  • the conductive pattern is positioned on a first die and the corresponding contact is positioned on a second die different from said first die.
  • said second die is adjacent to said first die to keep the polysilicon or amorphous silicon conductor as short as possible to minimize the resistance of the connection. Consequently the plating can be performed in a substantially uniform manner.
  • a system for plating on a plurality of conductive patterns formed at a surface of a substrate, where at least a part of a conductive pattern and/or a contact to a first surface of a substrate is covered with a layer to inhibit plating on said part.
  • this layer can be a resist layer.
  • the substrate can be a piece of a conductive material or a doped semi-conductive material. Particularly a silicon semiconductor wafer of a n-type or p-type conductivity can be used.
  • the plating solution can be any commercially available plating solution. Of particular interest are plating solutions containing an element selected from a group comprising Ag, Cu, Au, Pt, Ti , Ni and Co.
  • the conductive patterns are usually metal patterns. Particularly Al -containing or Cu-containing patterns can be used.
  • a substrate having at least a first surface and a second surface opposite to said first surface, said first surface being exposable to a plating solution, said substrate comprising a conductive pattern being positioned at said first surface of a substrate; a contact to the first surface of the substrate; and said conductive pattern being temporary electrically connected by a polysilicon or an amorphous silicon conductor with said contact and said contact being electrically connected with said second surface.
  • a method for plating on at least one conductive pattern formed at a surface of a substrate, said substrate having at least a first surface and a second surface, said method comprising the steps of: placing the substrate on an electrode being part of a plating holder such that said second surface of said substrate is in contact with said electrode and said conductive pattern is temporary electrically connected to said conductive pattern; and applying a plating solution on said first surface of said substrate thereby inhibiting exposure of said second surface to said plating solution.
  • a plating solution wherein said electrode and said conductive pattern are temporary electrically connected by forming a polysilicon or an amorphous silicon conductor to temporary connect said conductive pattern with a contact to the substrate, said contact being formed on the first surface of the substrate, and by providing an electrical connection between said contact and said electrode.
  • the resistance of the electrical connection between the contact and the electrode is substantially independent of the location of the contact on the first surface of the substrate. Therefore, to achieve a high degree of uniformity over the substrate of the plating process, preferably the length of the polysilicon or the amorphous silicon conductor should be kept as short as possible.
  • the conductive pattern is positioned on a first die and said contact is positioned on a second die different from said first die.
  • the connection can by cut by dicing the substrate. More preferably, said first and said second die are adjacent dies.
  • a method wherein prior to applying the plating solution, a resist layer is deposited on said conductive pattern and patterned in order to create at least one covered area an at least one uncovered area, said uncovered area being exposable to said plating solution.
  • a system and a method for selectively electroplating a plurality of aluminum patterns is disclosed.
  • the aluminum patterns to be plated are formed on the front side of a silicon wafer with a p-type conductivity.
  • Each aluminum pattern (Fig. 1) to be plated is connected by means of a polysilicon line to an aluminum contact to the p-type substrate region of the wafer at the front side of the wafer. This contact is positioned on an adjacent die.
  • the polysilicon line is isolated from the wafer by means of at least one dielectric layer.
  • the polysilicon line extends over a dicing line (Fig. 2) . Accordingly, all aluminum patterns to be plated are electrically connected to the back side of the wafer which can be provided with an aluminum metal contact .
  • the wafer Before applying a plating solution, the wafer is placed on a support with an electrically connectable electrode thereon such that there is an electrical connection between the back side of the wafer and the electrode.
  • This support is a part of a wafer holder designed for plating purposes.
  • the plating solution is brought in contact with the front side of the wafer, while the backside is sealed by means of a sealing element being part of the aforementioned wafer holder (Fig. 3) .
  • this sealing element is a sealing ring which inhibits the exposure of the backside of the substrate to the plating solution
  • the backside of the wafer is electrically connected with a backside electrode of the same size.
  • a homogeneous electrical field By immersing a similar electrode as counter electrode in the plating solution, a homogeneous electrical field can be created.
  • the plating process is galvanostatic, e.g. the current is held constant by regulating the potential between the backside and the counter electrode.
  • silver is electroplated and an alkaline silver solution is used as plating solution. A negative potential is applied at the backside electrode.
  • a positive photoresist layer (AZ4562) is used to cover those areas where no plating may occur. Finally, the wafers are stripped and diced.
  • Figure 4 and figure 5 show respectively a cross-section and top view of the polysilicon lines.
  • the electroplated structures are disconnected from the respective substrate contact.
  • the substrate as a contacting layer for an electrode
  • the electrical resistance between the areas to be plated and the electrical contact point is for all plated structures substantially the same, particularly if the length of the polysilicon lines is kept sufficiently short and the specific resistance of the polysilicon line is sufficiently low. This length has to be sufficiently short to assure that the resistance of the polysilicon lines has a negligible contribution to the total resistance of the connection between the conductive pattern and the backside of the wafer. Accordingly, the uniformity of the plating process is increased or in another words, the homogeneity of the deposited thickness of the plated material over the complete wafer is increased.
  • the plated material is silver.
  • the individual electroplated patterns are disconnected one from the other and are no longer in contact with the substrate .
  • polysilicon or amorphous silicon lines extending over the dicing lines, the risk to create electroplated patterns, being short-circuited to the substrate after dicing is reduced. If metal lines or leads would be used to provide the connection to the contact extending over the dicing line, the electroplated patterns can still be in contact with the substrate after dicing due to metal shavings or residues.
  • the same plating system and method as defined according the present invention can be used for electrochemical chloridation on wafer scale provided that a different solution is used and a positive potential is applied at the backside electrode instead of a negative potential.
  • electrochemical chloridation of silver Of particular interest is the electrochemical chloridation of silver.
  • the electrochemical chloridation of bulk silver electrodes (wires) can be used for producing standard reference electrodes.
  • An advantage is that the quality of the AgCl layer formed by using electrochemical chloridation is better than by using a chemical chloridation. So, according to the present invention, Ag/AgCl reference electrodes on wafer scale can be formed by using electroplated silver and electrochemically chloridized silver chloride.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention se rapporte à des procédés et à des systèmes de métallisation de motifs conducteurs qui permettent non seulement d'obtenir un résultat de grande uniformité mais suppriment également les effets parasites de la métallisation. L'invention se rapporte à un système de métallisation conçu pour métalliser des motifs conducteurs formés sur la première surface d'un substrat. Ledit système est conçu de sorte que les surfaces qui ne doivent pas être métallisées ne sont pas exposées. Une première électrode du système est immergée dans la solution de métallisation tandis qu'une seconde électrode est amenée au contact d'une autre surface que ladite première surface du substrat. Les motifs conducteurs à métalliser sont reliés électriquement de manière temporaire à la seconde électrode.
EP99936188A 1998-07-24 1999-07-14 Systeme et procede de metallisation d'un motif conducteur Withdrawn EP1114450A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US93974 1987-09-08
US9397498P 1998-07-24 1998-07-24
PCT/BE1999/000090 WO2000007229A1 (fr) 1998-07-24 1999-07-14 Systeme et procede de metallisation d'un motif conducteur

Publications (1)

Publication Number Publication Date
EP1114450A1 true EP1114450A1 (fr) 2001-07-11

Family

ID=22242015

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99936188A Withdrawn EP1114450A1 (fr) 1998-07-24 1999-07-14 Systeme et procede de metallisation d'un motif conducteur

Country Status (4)

Country Link
EP (1) EP1114450A1 (fr)
JP (1) JP2002521575A (fr)
AU (1) AU5141999A (fr)
WO (1) WO2000007229A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6782116B2 (ja) * 2016-08-02 2020-11-11 古河電気工業株式会社 銀被覆材料

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6701136A (fr) * 1967-01-25 1968-07-26
DE2830761A1 (de) * 1978-07-13 1980-01-24 Bosch Gmbh Robert Verfahren zur herstellung von halbleiterdioden
JPS57153431A (en) * 1981-03-17 1982-09-22 Mitsubishi Electric Corp Electroplating method for semiconductor wafer
JPS60128615A (ja) * 1983-12-15 1985-07-09 Sumitomo Electric Ind Ltd 半導体ウエハの電解メツキ方法
KR900008647B1 (ko) * 1986-03-20 1990-11-26 후지쓰 가부시끼가이샤 3차원 집적회로와 그의 제조방법
FR2742452B1 (fr) * 1995-12-18 1998-01-16 Commissariat Energie Atomique Support pour depot electrochimique

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0007229A1 *

Also Published As

Publication number Publication date
WO2000007229A1 (fr) 2000-02-10
JP2002521575A (ja) 2002-07-16
AU5141999A (en) 2000-02-21

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