EP0998795B1 - Method and apparatus for performance improvement by qualifying pulses in an oversampled, noise-shaping signal processor - Google Patents

Method and apparatus for performance improvement by qualifying pulses in an oversampled, noise-shaping signal processor Download PDF

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Publication number
EP0998795B1
EP0998795B1 EP98937027A EP98937027A EP0998795B1 EP 0998795 B1 EP0998795 B1 EP 0998795B1 EP 98937027 A EP98937027 A EP 98937027A EP 98937027 A EP98937027 A EP 98937027A EP 0998795 B1 EP0998795 B1 EP 0998795B1
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EP
European Patent Office
Prior art keywords
signal
pulse
processing circuit
signal processing
output
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Expired - Lifetime
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EP98937027A
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German (de)
English (en)
French (fr)
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EP0998795A4 (en
EP0998795A1 (en
Inventor
Adya S. Tripathi
Cary L. Delano
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Tripath Technology Inc
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Tripath Technology Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/06—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using differential modulation, e.g. delta modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/368—Continuously compensating for, or preventing, undesired influence of physical parameters of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
    • H03M3/376—Prevention or reduction of switching transients, e.g. glitches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/43—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
    • H03M3/454—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Definitions

  • the present invention relates to the field of oversampled, noise-shaping signal processing which includes, for example, sigma-delta modulation technology. More specifically, the present invention provides methods and apparatus for improving the dynamic range and noise performance of an oversampled, noise-shaping modulator. Even more specifically, some embodiments of the present invention improve the performance of such modulators for the purpose of driving power switching devices.
  • An integrator 102 is connected in series with a comparator 104 which is essentially a two-level quantizer with a sampling rate f s .
  • the output of comparator 104 is fed back to integrator 102 via digital-to-analog converter (D/A) 106 and adder 108.
  • D/A digital-to-analog converter
  • the feedback forces the low frequency content of the quantized output signal to track the low frequency content of the input to modulator 100. Any difference between the quantized output and modulator input is accumulated in integrator 102 and eventually corrected.
  • noise in the signal band due to quantization error is reduced by approximately 9 dB for each doubling of the oversampling ratio (OSR).
  • the OSR is given by f s /2 f o , where 2 f o is the Nyquist rate, i.e., twice the bandwidth f o of the baseband signal.
  • this noise is reduced by approximately 15 dB (9dB + 6 dB) for the same increase in OSR.
  • the reduction is 21 dB.
  • noise improvements achieved by increases in the OSR i.e., increases in f s , are ultimately constrained as the rise and fall times of the output signal become significant with respect to the sample period.
  • an oversampled, noise-shaping modulator which employs continuous-time feedback from the output of its switching stage rather than pure state feedback from before or after the power switching stage.
  • the continuous-time feedback is provided in such a way as to reduce the aliasing effects on the feedback path introduced by the switching stage which might otherwise interfere with the baseband to an unacceptable degree. That is, the improved modulator of the above-described application combines the use of continuous-time feedback to compensate for low frequency distortion, and some means of attenuating the aliasing effects of high frequency distortion introduced via the feedback path.
  • Fig. 2 is a simplified block diagram of an embodiment of a second-order modified oversampled, noise-shaping digital amplifier 200 designed according to a specific embodiment of the invention described in the above-referenced application.
  • An input signal is introduced to a first continuous-time integrator stage 202 via adder 204.
  • the output of first integrator stage 202 is transmitted to a second continuous-time integrator stage 206 via adder 208.
  • a clocked comparator stage 210 sampled at sample frequency f s receives the output of second integrator stage 206 and transmits the resulting logic signal to power switching stage 212.
  • the continuous-time output of power switching stage 212 is fed back to first integrator stage 202 via continuous-time gain stage 214 and adder 204.
  • Continuous-time feedback is also provided to second integrator stage 206 via continuous-time gain stage 216 and adder 208.
  • an anti-aliasing filter is not employed in the feedback path because the integrator stages are continuous-time integrators which inherently reject high frequencies.
  • integrator stages 202 and 206 comprise sampled integrators
  • the feedback to gain stages 214 and 216 would be via an anti-aliasing filter.
  • Such a filter would typically be a low pass filter which reduces the aliasing effects of the high frequency distortion generated by the power switching stage by removing the high frequency distortion from the continuous-time feedback signal.
  • the modified sigma-delta technology described in the above-referenced application provides a highly efficient, low noise alternative to PWM in a wide variety of applications.
  • the amount of gain which can be introduced in the oversampled modulator loop and therefore a limit on the dynamic range of the modulator
  • a very low noise floor and a high dynamic range with low distortion are obviously desirable.
  • other performance improvements e.g., reduced ripple and component size
  • the input pulses to the power switching stage must be sufficiently long and sufficiently far apart to ensure that the transitions do not overlap to an unacceptable degree.
  • Power MOSFETs Theory and Application by Duncan A. Grant and John Gowar ( ⁇ 1989 John Wiley & Sons, Inc.)
  • Smart Power ICs Technologies and Applications edited by B. Murari, F. Bertotti, and G.A. Vignola ( ⁇ 1996 Springer Verlag).
  • the noise floor of a power amplifier may be improved from 9 to 21 dB (or more) per octave of oversampling depending on the order of the modulator, i.e., 9 dB for a first-order modulator to 21 dB for a third-order modulator (see the references cited above and the above-referenced patent application).
  • 9 dB for a first-order modulator
  • 21 dB for a third-order modulator
  • today's power MOSFETs can typically be switched up to around 1.5 MHz.
  • a designer of an audio power amplifier might set the sampling frequency of the oversampled modulator at 3 MHz, providing 64X oversampling (i.e., 2 6 ) with respect to an audio input signal.
  • the corresponding theoretical input-referred noise floor, i.e., the dynamic range, of the amplifier would be given by (21 dB)x(log 2 64) or 126 dB.
  • Actual third-order modulator performance is typically 20-30 dB worse than this due to practical considerations. While this level of performance might be suitable for some low end applications, it is not sufficient for a high-end, high-power audio amplifier as the high gain associated with such an amplifier will boost the input-referred noise to unacceptable levels.
  • Increasing the sample frequency to 6 MHz yields an oversampling ratio of 128X which, in turn, provides a theoretical noise floor/dynamic range of (21 dB) ⁇ (log 2 ,128) or 147 dB. While this is sufficient for many high end applications, the sampling frequency is too fast for today's power devices.
  • US 5323156 discloses an integrator whose signal input is supplied through an integrating resistor with an analog signal.
  • a comparator has its comparator input connected to the integrator output and its reference input grounded and a pulse-width selector providing a narrow or wide pulse depending on the comparator output is provided, whose signal is connected to the comparator output, and whose first clock and second inputs are supplied with a clock signal and an additional clock signal derived from said clock signal by frequency division.
  • Series combined first and second electronic switches are provided which are connected between a unipolar reference voltage and ground or between the two terminals for a bipolar, balanced-to-ground reference voltage, with the control inputs of the electronic switches connected to the noninverted and inverted outputs, respectively, of the pulse-width selector, and with the junction of the electronic switches connected to a further-processing arrangement and through a feedback resistor to the signal input of the integrator.
  • the width of the narrow pulse is equal to the period of the clock signal, while the width of the wide pulse is equal to (n-1) times the period of the clock signal.
  • the invention is according to a signal processing circuit as disclosed in claim 1 and to a method for operating a signal processing circuit as disclosed in claim 16.
  • an improvement to the oversampled, noise-shaping modulator described in the above-referenced patent application is provided which achieves a lower input-referred noise floor, i.e., a higher dynamic range, by increasing the oversampling ratio without suffering the consequences of unacceptably narrow pulse widths.
  • the invention is especially useful in power switching applications in which narrow pulses are unacceptable such as, for example, audio amplifiers, switching regulators, power amplifiers, motor control, power factor correction, resonant mode switching, etc.
  • the present invention achieves this improvement by increasing the sampling frequency, i.e., the rate at which the oversampled modulator is clocked, and the gain of the modulator loop, while adding pulse qualification logic before the switching stage to eliminate unacceptably narrow pulses.
  • the pulse qualification logic of the present invention receives the output of the A/D converter (or comparator) in the oversampled modulator loop and does not allow transitions to be sent to the switching stage within some number of clock cycles.
  • the number of clock cycles may determined with reference to a number of considerations including, for example, the speed of the switching devices in the switching stage, a desired relationship between noise floor and output swing (for a given maximum clock rate), the desired switching frequency, etc. While this avoids the problems associated with the spacing between transitions, it introduces a delay and nonlinearity in the modulator loop which can actually degrade the dynamic range and cause instability. Therefore, to address this concern, the modulator sampling frequency is increased beyond what was necessary to achieve a lower noise floor. Thus, the modulator loop gain and the sampling frequency are simultaneously increased (with the sampling frequency being increased more rapidly to maintain loop stability), thereby improving the dynamic range and noise floor while not allowing unacceptably narrow pulses to go to the switching stage.
  • the present invention provides a signal processing circuit comprising a frequency selective network for generating a first signal.
  • a quantizer coupled to the frequency selective network receives the first signal and generates a quantized signal.
  • Qualification circuitry coupled to the quantizer receives the quantized signal and generates a qualified signal.
  • the qualification circuitry causes signal transitions in the qualified signal to occur at least a first time period apart.
  • the signal processing circuit also has a feedback path from its output to the frequency selective network.
  • a signal processing circuit comprising:
  • a method for operating a signal processing circuit comprising a frequency selective network, a quantizer, and an output connected in series, and a feedback path from the output to the frequency selective network, the method characterised by:
  • Fig. 3 is a block diagram of an oversampled, noise-shaping modulator 300 designed according to a specific embodiment of the present invention.
  • the input to integrator stage 302 is received via adder 304.
  • the input to integrator stage 306 is transmitted from integrator stage 302 via adder 308.
  • a comparator stage 310 with a sample frequency f s receives the output of second integrator stage 306 and transmits the resulting logic signal to qualification logic 318.
  • qualification logic 318 ensures that the width of pulses sent to power switching stage are at least some minimum width. The operation of a particular embodiment of qualification logic 318 is described below with reference to Fig. 5.
  • the qualified pulse waveform is then transmitted to power switching stage 312.
  • the continuous-time output of power switching stage 312 is fed back to first integrator stage 302 via continuous-time gain stage 314 and adder 304.
  • Continuous-time feedback is also provided to second integrator stage 306 via continuous-time gain stage 316 and adder 308.
  • An anti-aliasing filter is not employed in the feedback path because, as discussed above with reference to Fig. 2, the integrator stages in this embodiment are continuous-time integrators which inherently reject high frequencies.
  • Fig. 4 shows a series of waveforms from various points in the modulator 300 of Fig. 3.
  • the switching response shows the output of the power switching stage both with the pulse qualification of the invention enabled (solid waveform) and disabled (dashed waveform).
  • comparator stage 310 is a 1-bit analog-to-digital (A/D) converter which is triggered on the positive rising edge of the clock signal.
  • the clock signal is the sample frequency input to A/D converter 310
  • the A/D output signal is the output of A/D converter 310
  • the qualified output signal is the output of qualification logic 318
  • the switching response signal is the output of power switching stage 312.
  • the qualification logic ensures that pulses are sent to the power switching devices at most once every 2 clock cycles (see the qualified output signal).
  • the switching response signal shown would not have been possible without the qualification logic.
  • the qualification logic operates on the same edge as the A/D converter, i.e., the positive rising edge of the clock signal. This may be achieved by combining the qualification logic and the A/D converter to thereby avoid any additional and undesirable logic delays.
  • the output of the power switching stage never quite reaches the positive rail (i.e., the dotted line) because the input pulses to the power switching stage are too narrow and the upward and downward transitions of the power devices therefore overlap.
  • the operation of a comparator and a glitch-free state machine implementation of pulse qualification logic will be described with reference to the schematic of Fig. 5 for the purpose of illustrating the concept of the present invention.
  • Different qualification levels corresponding to different sampling frequencies may be selected using the mode 0 and mode 1 inputs.
  • the level of pulse qualification may be selected to match a desired multiple of the modulator clock rate as shown in Table 1.
  • the pulse qualification logic may be bypassed by bringing the BYPASS input high, thereby allowing pulses to go from the comparator to the power switching stage without qualification. As shown in Table 1 this might be done where an increase in the clock rate is not necessary.
  • Table 1 BYPASS mode 0 mode 1 multiple of clock rate 0 0 0 16X 0 0 1 8X 0 1 0 4X 0 1 1 2X 1 x x 1X x don't care
  • circuit 500 comprising a comparator and qualification logic
  • the output of nand 502 is low thereby clearing D flip-flops 504, 506, 508 and 510, and setting multiplexer 512 such that the output of comparator 514 goes directly to the D input of flip-flop 516.
  • the outputs of flip-flops 516 and 518 must be at the same level.
  • the output of nor 520 goes high.
  • multiplexer 522 selects the Q output of flip-flop 518 to be fed back to the D input of flip-flop 518, i.e., flip-flop 518 holds its state if its clock is triggered.
  • x-nor 526 acts as a non-inverting buffer of its input from flip-flop 504. This means flip-flop 504 holds its state when clocked, thereby preventing counter 528 (indicated by the dashed line) comprising flip-flops 504-510 from being clocked.
  • Flip-flops 504, 516 and 518 are then clocked via the clock input. If the state of flip-flop 516 remains unchanged, all of the above-described logic levels remain the same. If, however, the state of flip-flop 516 changes, it will no longer be the same as flip-flop 518 and the output of x-nor 524 will then go low. This, in turn, changes the state of multiplexer 512 (via nand 502) which connects the Q output of flip-flop 516 to its own D input, thereby latching the state of flip-flop 516.
  • a logic low on the output of x-nor 524 turns x-nor 526 into an inverter, thereby causing flip-flop 504 to act as a divide-by-two of the sample frequency from the clock input.
  • the counter will then only be clocked until the control logic causes the output of nor 520 to go low which changes the state of multiplexer 522 which then connects the Q output of flip-flop 516 to the D input of flip-flop 518.
  • This causes the states of flip-flops 516 and 518 to become the same again on the next clock edge, bringing the output of x-nor 524 high and the output of nand 502 low.
  • the output pulse width i.e., the qualification delay, is determined by programmable counter 528 plus one clock cycle.
  • the qualification logic may be bypassed. This is accomplished by bringing the BYPASS input high, thereby tying the output of nand 502 high. As a result, the output of comparator 514 is gated to the output (via multiplexer 512 and flip-flop 516) without the pulse qualification delay.
  • the pulse qualification circuitry of the present invention could be implemented using a one-shot configured to hold an input pulse high for at least some minimum time period.
  • a one-shot configured to hold an input pulse high for at least some minimum time period.
  • unclocked comparator 602 changes state
  • bi-directional one-shot 604 goes to a logic 1. This clocks the comparator output into flip-flop 606 and configures multiplexer 608 to transmit the output of flip-flop 606 to the output of the circuit via buffer 610.
  • multiplexer 608 is configured to transmit the output of comparator 602 to the output.of the circuit until another transition occurs.
  • the output pulse of the circuit is the length of the timeout.
  • the comparator pulse is longer than the timeout, the output pulse will be of the same duration as the comparator pulse.
  • the embodiment discussed with reference to Fig. 4 employs an A/D converter.
  • a comparator may be employed instead of the A/D converter.
  • the comparator need not be a clocked comparator as shown in Fig. 3, but may be an unclocked comparator as shown in Fig. 5 or any unclocked quantizer.
  • the pulse qualification logic of the present invention may be implemented using an analog RC timer (or any type of one-shot device) instead of the programmable digital timer shown in Fig. 5.
  • the present invention may be implemented using an RC timer and an unclocked comparator wherein the RC timer does not allow transitions to occur within a certain period of time determined by the RC constant.
  • the embodiment of Fig. 5 represents only one implementation of the qualification logic of the present invention. It will be understood that many others are possible.
  • the integrator stages may be replaced by some other type of frequency selective network such as, for example, resonators.
  • the pulse qualification circuitry of the present invention is not restricted to modulator loops which include a power switching stage.
  • the pulse qualification logic may be implemented in a fully digital sigma-delta modulator which is upstream from a switching stage for which the time between transitions is critical. In such an application, the output of the modulator is encoded to prevent narrowly spaced transitions downstream.
  • the pulse qualification circuitry of the present invention may be employed in a standard sigma-delta modulator such as the modulator of Fig. 1 Therefore, the scope of the invention should be determined with reference to the appended claims.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Noise Elimination (AREA)
  • Amplifiers (AREA)
EP98937027A 1997-07-22 1998-07-20 Method and apparatus for performance improvement by qualifying pulses in an oversampled, noise-shaping signal processor Expired - Lifetime EP0998795B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US898544 1997-07-22
US08/898,544 US5974089A (en) 1997-07-22 1997-07-22 Method and apparatus for performance improvement by qualifying pulses in an oversampled noise-shaping signal processor
PCT/US1998/015266 WO1999005806A1 (en) 1997-07-22 1998-07-20 Method and apparatus for performance improvement by qualifying pulses in an oversampled, noise-shaping signal processor

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EP0998795A1 EP0998795A1 (en) 2000-05-10
EP0998795A4 EP0998795A4 (en) 2004-03-17
EP0998795B1 true EP0998795B1 (en) 2006-02-22

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US (1) US5974089A (ja)
EP (1) EP0998795B1 (ja)
JP (1) JP4057774B2 (ja)
KR (1) KR20010022060A (ja)
CN (1) CN1271483A (ja)
AT (1) ATE318470T1 (ja)
CA (1) CA2296251A1 (ja)
DE (1) DE69833553T2 (ja)
WO (1) WO1999005806A1 (ja)

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DE69833553D1 (de) 2006-04-27
EP0998795A4 (en) 2004-03-17
WO1999005806A1 (en) 1999-02-04
CA2296251A1 (en) 1999-02-04
CN1271483A (zh) 2000-10-25
US5974089A (en) 1999-10-26
KR20010022060A (ko) 2001-03-15
EP0998795A1 (en) 2000-05-10
ATE318470T1 (de) 2006-03-15
JP4057774B2 (ja) 2008-03-05
JP2001511618A (ja) 2001-08-14
DE69833553T2 (de) 2006-12-14

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