US11616512B1 - Series-connected delta-sigma modulator - Google Patents

Series-connected delta-sigma modulator Download PDF

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US11616512B1
US11616512B1 US17/672,728 US202217672728A US11616512B1 US 11616512 B1 US11616512 B1 US 11616512B1 US 202217672728 A US202217672728 A US 202217672728A US 11616512 B1 US11616512 B1 US 11616512B1
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dsm
loop filter
signal
series
quantizer
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Tai-Haur Kuo
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National Cheng Kung University NCKU
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/368—Continuously compensating for, or preventing, undesired influence of physical parameters of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2175—Class D power amplifiers; Switching amplifiers using analogue-digital or digital-analogue conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
    • H03M3/452—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
    • H03M3/454—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation
    • H03M3/506—Details of the final digital/analogue conversion following the digital delta-sigma modulation the final digital/analogue converter being constituted by a pulse width modulator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications

Definitions

  • the present invention relates to a modulator, and more particularly, to a delta-sigma modulator (DSM) which is able to provide a high resolution, a high linearity, and to permit a large input range.
  • DSM delta-sigma modulator
  • a DSM achieves a high signal-to-noise-and-distortion ratio (SNDR) and is often applied to high-resolution applications.
  • SNDR signal-to-noise-and-distortion ratio
  • the output signal of the loop filter may include high-frequency-shaped noises, and may exceed the full scale of the quantizer, which leads to a significant clipping error.
  • the clipping error is then fed back to the loop filter and processed by its high out-of-band gain, which induces an additional distortion source and degrades the corresponding SNDR severely.
  • how to maintain the SNDR and the large input range of the DSM simultaneously is a problem to be solved.
  • the present invention therefore provides a series-connected DSM to solve the abovementioned problem.
  • a series-connected DSM comprises a first DSM, configured to receive an input signal, comprising a first loop filter, configured to generate a first processed signal; and a first quantizer, coupled to the first loop filter, configured to generate a first quantized signal according to the first processed signal, and to feed back the first quantized signal to the first loop filter, wherein the first loop filter generates the first processed signal according to the input signal and the first quantized signal fed back to the first loop filter, and the first quantized signal comprises a clipping error smaller than a first predetermined value; and a second DSM, coupled to the first DSM, configured to receive the first quantized signal from the first DSM, comprising a second loop filter, configured to generate a second processed signal; and a second quantizer, coupled to the second loop filter, configured to generate a second quantized signal according to the second processed signal, and to feed back the second quantized signal to the second loop filter, wherein the second loop filter generates the second processed signal according to the first quantized signal and the second quantized signal fed back to the second
  • FIG. 1 is a schematic diagram of a delta-sigma modulator (DSM) according to the prior art.
  • FIG. 2 is a schematic diagram of a series-connected DSM in general according to an example of the present invention.
  • FIG. 3 is a schematic diagram of a series-connected DSM in detail according to an example of the present invention.
  • FIG. 4 shows waveforms of the input signal, internal node signal and output signal of the DSM according to the prior art and the series-connected DSM according to an example of the present invention.
  • FIG. 5 is a schematic diagram of a series-connected DSM in z-domain according to an example of the present invention.
  • FIG. 6 is a comparison diagram of expected SNDRs between the DSM according to the prior art and the series-connected DSM according to an example of the present invention.
  • FIG. 7 is a comparison diagram of simulated SNDRs between the DSM according to the prior art and the series-connected DSM according to an example of the present invention.
  • FIG. 8 is a schematic diagram of a digital-input class-D audio amplifier.
  • FIG. 9 is a comparison diagram of performances between the DSM applied to a class-D audio amplifier according to the prior art and the series-connected DSM applied to a class-D audio amplifier according to an example of the present invention.
  • FIG. 1 is a schematic diagram of a delta-sigma modulator (DSM) 10 according to the prior art.
  • the DSM 10 is configured to receive an input signal XS, and includes a loop filter LF and a quantizer QT.
  • the loop filter LF is configured to generate a processed signal PS.
  • the quantizer QT receives the processed signal PS and generates a quantized signal QS according to the processed signal PS.
  • the quantized signal QS may be seen as an output signal of the DSM 10 .
  • the quantized signal QS is fed back to the loop filter LF.
  • the loop filter LF generates the processed signal PS according to the input signal XS and the quantized signal QS.
  • the quantizer QT may introduce a quantization error E Q and a clipping error E C in a quantization process.
  • the quantization error E Q is shaped to a high-frequency band by a noise transfer function of the loop filter LF.
  • the DSM 10 with more aggressive noise-shaping ability is utilized for suppressing the quantization error E Q .
  • SNDR signal-to-noise-and-distortion ratio
  • a full scale of the quantizer QT may be exceeded by the output signal of loop filter (i.e., the processed signal PS) with high-frequency-shaped noises, which induces the clipping error E C , when the input signal XS is large.
  • the clipping error E C is then fed back to the loop filter LF, which induces an additional distortion source and severely degrades a corresponding SNDR of the DSM 10 .
  • the DSM 10 with less noise-shaping ability provides a larger input range at the expense of SNDR degradation.
  • the DSM 10 may be designed to extend the input range (e.g., by proposing a root-loci-inside-unit-circle (RLiUC) technique or an adaptive-coefficient DSM (ACDSM)).
  • RLiUC root-loci-inside-unit-circle
  • ACDSM adaptive-coefficient DSM
  • in-band noise-shaping abilities of both techniques are degraded, which leads to a degraded SNDR.
  • FIG. 2 is a schematic diagram of a series-connected DSM 20 in general according to an example of the present invention.
  • the series-connected DSM 20 includes a first DSM 200 and a second DSM 210 .
  • the first DSM 200 receives an input signal XS.
  • the first DSM 200 may be a quantization-error-shaping DSM with aggressive noise-shaping ability to achieve a high SNDR of the series-connected DSM 20 .
  • the second DSM 210 transmits an output signal QS 2 .
  • the second DSM 210 may be a clipping-error-shaping DSM to ensure a large input range of the series-connected DSM 20 .
  • FIG. 3 is a schematic diagram of a series-connected DSM 30 in detail according to an example of the present invention.
  • the series-connected DSM 30 includes a first DSM 300 and a second DSM 310 .
  • the first DSM 300 is configured to receive an input signal XS, and includes a first loop filter LF 1 and a first quantizer Q EX .
  • the first loop filter LF 1 is configured to generate a first processed signal PS 1 .
  • the first quantizer Q EX is coupled to the first loop filter LF 1 , and is configured to generate a first quantized signal QS 1 according to the first processed signal PS 1 .
  • the first quantized signal QS 1 may be seen as an output signal of the first DSM 300 .
  • the first quantized signal QS 1 is fed back to the first loop filter LF 1 so that the first loop filter LF 1 may generate the first processed signal PS 1 according to the input signal XS and the first quantized signal QS 1 .
  • the first quantized signal QS 1 may include a clipping error E C smaller than a first predetermined value due to the extended full scale of the first quantizer Q EX . That is, the first DSM 300 may mainly suppress the quantization error E Q , forming a quantization-error-shaping DSM. Only little clipping error E C is processed by the first DSM 300 so that the SNDR of the first DSM 300 may be maintained at an appropriate level.
  • the second DSM 310 is coupled to the first DSM 300 , and is configured to receive the first quantized signal QS 1 (i.e., the output signal of the first DSM 300 ) from the first DSM 300 .
  • the second DSM 310 includes a second loop filter LF 2 and a second quantizer QT 2 .
  • the second loop filter LF 2 is configured to generate a second processed signal PS 2 .
  • the second quantizer QT 2 is coupled to the second loop filter LF 2 , and is configured to generate a second quantized signal QS 2 according to the second processed signal PS 2 .
  • the second quantized signal QS 2 may be seen as an output signal of the series-connected DSM 30 .
  • the second quantized signal QS 2 is fed back to the second loop filter LF 2 so that the second loop filter LF 2 may generate the second processed signal PS 2 according to the first quantized signal QS 1 (i.e., the input signal of the second DSM 310 ) and the second quantized signal QS 2 .
  • the second quantized signal QS 2 may include a quantization error E Q smaller than a second predetermined value. That is, the second DSM 310 may mainly suppress the clipping error E C , forming a clipping-error-shaping DSM. Only little quantization error E Q is processed by the second DSM 310 so that the input range is extended. It should be noted that only little quantization error is allowed to be introduced in the second DSM 310 to maintain a high SNDR.
  • the first loop filter LF 1 includes at least one first stage for receiving the input signal XS and the first quantized signal QS 1 .
  • the second loop filter LF 2 includes at least one second stage for receiving the first quantized signal QS 1 (i.e., the input signal of the second DSM 310 ) and the second quantized signal QS 2 .
  • the first loop filter LF 1 and the second loop filter LF 2 may include (e.g., may be realized as) at least one integrator or at least one resonator. In one example, the first loop filter LF 1 and the second loop filter LF 2 may include (e.g., may be realized in) at least one discrete-time circuit or at least one continuous-time circuit.
  • the first quantizer Q EX includes a first plurality of quantization levels
  • the second quantizer QT 2 includes a second plurality of quantization levels.
  • a number of the first plurality of quantization levels is larger than a number of the second plurality of quantization levels.
  • the second quantizer QT 2 may be a conventional quantizer (e.g., the quantizer QT of the DSM 10 ), and the first quantizer Q EX may be an extended quantizer with more quantization levels than the conventional quantizer (e.g., the second quantizer QT 2 ).
  • the additional quantization levels included in the first quantizer Q EX are beyond an original full scale to provide extra quantization levels. In this situation, most of the clipping error E C of the first quantizer Q EX is temporarily avoided even if an input of the first quantizer Q EX is large, which makes little clipping error E C processed by the first loop filter LF 1 .
  • the first quantizer Q EX and the second quantizer QT 2 perform a plurality of sampling operations at a same frequency. In one example, the first quantizer Q EX and the second quantizer QT 2 perform a plurality of sampling operations at different frequencies.
  • FIG. 4 shows waveforms of the input signal, internal node signal and output signal of the DSM 10 according to the prior art and the series-connected DSM 30 according to an example of the present invention.
  • the input signal XS is a 20-bit digital signal
  • the output signal QS of the DSM 10 and the output signal QS 2 of the series-connected DSM 30 are both 6-bit digital signals.
  • the output signal QS exceeds a full scale 401 (i.e., the original full scale) of the quantizer QT, which leads to a large clipping error.
  • the series-connected DSM 30 when the input signal XS is large, the first quantizer Q EX provides a full scale 402 (i.e., the extended full scale) with additional quantization levels to avoid clipping error on the first quantized signal QS 1 .
  • the clipping error is then processed by the second DSM 310 (e.g., the clipping-error shaping DSM), which maintains the output signal (i.e., the second quantized signal QS 2 ) nearly same as the input signal XS.
  • the second DSM 310 e.g., the clipping-error shaping DSM
  • FIG. 5 is a schematic diagram of a series-connected DSM 50 in z-domain according to an example of the present invention.
  • the series-connected DSM 50 includes a first DSM 500 and a second DSM 510 .
  • the first DSM 500 may be the first DSM 300 , and includes a first loop filter LF 1 and a first quantizer Q EX .
  • the first loop filter LF 1 may be a fifth-order DSM.
  • the loop filter LF 1 includes a plurality of transfer functions g 1 H, g 2 H, g 3 H, g 4 H and g 5 H and a plurality of DSM coefficients a 1 , a 2 , a 3 , a 4 , a 5 , b 1 , b 2 , b 3 and b 4 , for receiving the input signal XS.
  • the transfer function H is equal to z ⁇ 1 /(1 ⁇ z ⁇ 1 ).
  • the first quantizer Q EX introduces a quantization error E Q and feeds back little clipping error E C to the first loop filter LF 1 .
  • the first quantizer Q EX generates a quantized signal QS 1 and transmits the quantized signal QS 1 to the second DSM 510 .
  • the second DSM 510 may be the second DSM 310 , and includes a second loop filter LF 2 and a second quantizer QT 2 .
  • the second loop filter LF 2 may be a second-order DSM.
  • the loop filter LF 2 includes a plurality of transfer functions z ⁇ 1 and DSM coefficients 1 and ⁇ 2 which are both integers.
  • the second quantizer QT 2 introduces the clipping error E C .
  • the second quantizer QT 2 generates the output signal QS 2 of the series-connected DSM 50 .
  • the plurality of transfer functions g 1 H, g 2 H, g 3 H, g 4 H, g 5 H and z ⁇ 1 may be implemented as at least one integrator or at least one resonator, and may be implemented as at least one discrete-time circuit or at least one continuous-time circuit. All coefficients included in the second DSM 510 may be integers. The arithmetic results at each internal node may fall in a range of ⁇ 1, ⁇ 31/32, ⁇ 30/32, . . . , 0, . . . , +30/32, +31/32, +1 ⁇ . That is, little quantization error is introduced in the second DSM 310 . Thus, a SNDR of the series-connected DSM 50 is not affected by the second DSM 510 while an amplitude of the input signal XS is small.
  • FIG. 6 is a comparison diagram of expected SNDRs between the DSM 10 according to the prior art and the series-connected DSM 30 according to an example of the present invention.
  • the x-axis is an input amplitude of an input signal.
  • the unit of the input amplitude is decibel relative to full-scale (dBFS).
  • the y-axis is a SNDR.
  • the unit of the SNDR is decibel (dB).
  • a curve 600 is a schematic result of the DSM 10 with the aggressive noise-shaping ability. As shown in the curve 600 in FIG. 6 , the SNDR drops severely when the input amplitude becomes larger than a threshold V th .
  • a curve 602 is a schematic result of the DSM 10 for extending the input range.
  • a curve 610 is a schematic result of the series-connected DSM 30 according to an example of the present invention. As shown in the curve 610 in FIG. 6 , for the input amplitude smaller than the threshold Vth, the SNDR of the series-connected DSM 30 is similar to that of the DSM 10 with the aggressive noise-shaping ability, and is higher than that of the DSM 10 for extending the input range.
  • the SNDR of the series-connected DSM 30 drops slightly since only little clipping error is fed back to the loop filter.
  • the performance of the series-connected DSM 30 is better than the DSM 10 since the series-connected DSM 30 maintains the high SNDR and simultaneously extends the input range.
  • FIG. 7 is a comparison diagram of simulated SNDRs between the DSM 10 according to the prior art and the series-connected DSM 30 according to an example of the present invention.
  • the x-axis is an input amplitude of an input signal.
  • the unit of the input amplitude is dBFS.
  • the y-axis is a SNDR.
  • the unit of the SNDR is dB.
  • a curve 700 is a simulation result of the DSM 10
  • a curve 710 is a simulation result of the series-connected DSM 30 . As shown in FIG.
  • the input amplitudes of the DSM 10 and the series-connected DSM 30 are ⁇ 1.4 dBFS and 0.2 dBFS, respectively. That is, compared with the DSM 10 , the series-connected DSM 30 extends the maximum input amplitude with 40 dB SNDR from ⁇ 1.4 dBFS to 0.2 dBFS, and maintains the SNDR up to 60 dB for a 0-dBFS input amplitude.
  • FIG. 8 is a schematic diagram of a digital-input class-D audio amplifier 80 .
  • the digital input audio signal is oversampled and processed by an interpolator 810 .
  • the oversampled signal is processed by a DSM 820 to perform a high resolution with a pulse-code modulation (PCM) signal, and is converted into a pulse-width modulation (PWM) signal by a PCM-to-PWM converter 830 .
  • the PWM signal is used to drive a class-D power stage 840 (e.g., an H-bridge power stage) of the digital-input class-D audio amplifier 80 .
  • a class-D power stage 840 e.g., an H-bridge power stage
  • the series-connected DSM 30 may be used in Class-D audio amplifier to prevent clipping error from limiting the input range of the amplifier.
  • FIG. 9 is a comparison diagram of performances between the DSM 10 applied to a digital-input class-D audio amplifier 80 according to the prior art and the series-connected DSM 30 applied to a digital-input class-D audio amplifier 80 according to an example of the present invention.
  • the x-axis is an audio power to the speaker 850 of the digital-input class-D audio amplifier 80 .
  • the unit of the audio power is watt (W).
  • the y-axis is THD+N.
  • the unit of the THD+N is percent (%).
  • a curve 900 is a simulation result of the DSM 10 applied to the digital-input class-D audio amplifier 80
  • a curve 910 is a simulation result of the series-connected DSM 30 applied to the digital-input class-D audio amplifier 80 .
  • the output power of the digital-input class-D amplifier 80 applying the DSM 10 and the series-connected DSM 30 are 1 W and 1.4 W, respectively. That is, compared with the DSM 10 , the series-connected DSM 30 extends 40% of output power with the THD+N of 1%, and audio quality under conditions of low audio power is not sacrificed.
  • the present invention provides a series-connected DSM.
  • the series-connected DSM achieves a large input range and a high SNDR simultaneously.
  • the problem in the art is solved.

Abstract

A series-connected delta-sigma modulator (DSM) comprises a first DSM, configured to receive an input signal, comprising a first loop filter, configured to generate a first processed signal; and a first quantizer, coupled to the first loop filter, configured to generate a first quantized signal, and to feed back the first quantized signal to the first loop filter, wherein the first quantized signal comprises a clipping error smaller than a first predetermined value; and a second DSM, coupled to the first DSM, configured to receive the first quantized signal from the first DSM, comprising a second loop filter, configured to generate a second processed signal; and a second quantizer, coupled to the second loop filter, configured to generate a second quantized signal, and to feed back the second quantized signal to the second loop filter, wherein the second quantized signal comprises a quantization error smaller than a second predetermined value.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a modulator, and more particularly, to a delta-sigma modulator (DSM) which is able to provide a high resolution, a high linearity, and to permit a large input range.
2. Description of the Prior Art
A DSM achieves a high signal-to-noise-and-distortion ratio (SNDR) and is often applied to high-resolution applications. However, when the input signal of the DSM is large, the output signal of the loop filter may include high-frequency-shaped noises, and may exceed the full scale of the quantizer, which leads to a significant clipping error. The clipping error is then fed back to the loop filter and processed by its high out-of-band gain, which induces an additional distortion source and degrades the corresponding SNDR severely. Thus, how to maintain the SNDR and the large input range of the DSM simultaneously is a problem to be solved.
SUMMARY OF THE INVENTION
The present invention therefore provides a series-connected DSM to solve the abovementioned problem.
A series-connected DSM comprises a first DSM, configured to receive an input signal, comprising a first loop filter, configured to generate a first processed signal; and a first quantizer, coupled to the first loop filter, configured to generate a first quantized signal according to the first processed signal, and to feed back the first quantized signal to the first loop filter, wherein the first loop filter generates the first processed signal according to the input signal and the first quantized signal fed back to the first loop filter, and the first quantized signal comprises a clipping error smaller than a first predetermined value; and a second DSM, coupled to the first DSM, configured to receive the first quantized signal from the first DSM, comprising a second loop filter, configured to generate a second processed signal; and a second quantizer, coupled to the second loop filter, configured to generate a second quantized signal according to the second processed signal, and to feed back the second quantized signal to the second loop filter, wherein the second loop filter generates the second processed signal according to the first quantized signal and the second quantized signal fed back to the second loop filter, and the second quantized signal comprises a quantization error smaller than a second predetermined value.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a delta-sigma modulator (DSM) according to the prior art.
FIG. 2 is a schematic diagram of a series-connected DSM in general according to an example of the present invention.
FIG. 3 is a schematic diagram of a series-connected DSM in detail according to an example of the present invention.
FIG. 4 shows waveforms of the input signal, internal node signal and output signal of the DSM according to the prior art and the series-connected DSM according to an example of the present invention.
FIG. 5 is a schematic diagram of a series-connected DSM in z-domain according to an example of the present invention.
FIG. 6 is a comparison diagram of expected SNDRs between the DSM according to the prior art and the series-connected DSM according to an example of the present invention.
FIG. 7 is a comparison diagram of simulated SNDRs between the DSM according to the prior art and the series-connected DSM according to an example of the present invention.
FIG. 8 is a schematic diagram of a digital-input class-D audio amplifier.
FIG. 9 is a comparison diagram of performances between the DSM applied to a class-D audio amplifier according to the prior art and the series-connected DSM applied to a class-D audio amplifier according to an example of the present invention.
 DETAILED DESCRIPTION
FIG. 1 is a schematic diagram of a delta-sigma modulator (DSM) 10 according to the prior art. The DSM 10 is configured to receive an input signal XS, and includes a loop filter LF and a quantizer QT. The loop filter LF is configured to generate a processed signal PS. Then, the quantizer QT receives the processed signal PS and generates a quantized signal QS according to the processed signal PS. The quantized signal QS may be seen as an output signal of the DSM 10. The quantized signal QS is fed back to the loop filter LF. The loop filter LF generates the processed signal PS according to the input signal XS and the quantized signal QS. The quantizer QT may introduce a quantization error EQ and a clipping error EC in a quantization process. The quantization error EQ is shaped to a high-frequency band by a noise transfer function of the loop filter LF. To achieve a high signal-to-noise-and-distortion ratio (SNDR), the DSM 10 with more aggressive noise-shaping ability is utilized for suppressing the quantization error EQ. However, a full scale of the quantizer QT may be exceeded by the output signal of loop filter (i.e., the processed signal PS) with high-frequency-shaped noises, which induces the clipping error EC, when the input signal XS is large. The clipping error EC is then fed back to the loop filter LF, which induces an additional distortion source and severely degrades a corresponding SNDR of the DSM 10. On the other hand, the DSM 10 with less noise-shaping ability provides a larger input range at the expense of SNDR degradation.
The DSM 10 may be designed to extend the input range (e.g., by proposing a root-loci-inside-unit-circle (RLiUC) technique or an adaptive-coefficient DSM (ACDSM)). However, in-band noise-shaping abilities of both techniques are degraded, which leads to a degraded SNDR.
FIG. 2 is a schematic diagram of a series-connected DSM 20 in general according to an example of the present invention. The series-connected DSM 20 includes a first DSM 200 and a second DSM 210. The first DSM 200 receives an input signal XS. The first DSM 200 may be a quantization-error-shaping DSM with aggressive noise-shaping ability to achieve a high SNDR of the series-connected DSM 20. The second DSM 210 transmits an output signal QS2. The second DSM 210 may be a clipping-error-shaping DSM to ensure a large input range of the series-connected DSM 20.
FIG. 3 is a schematic diagram of a series-connected DSM 30 in detail according to an example of the present invention. The series-connected DSM 30 includes a first DSM 300 and a second DSM 310. The first DSM 300 is configured to receive an input signal XS, and includes a first loop filter LF1 and a first quantizer QEX. The first loop filter LF1 is configured to generate a first processed signal PS1. The first quantizer QEX is coupled to the first loop filter LF1, and is configured to generate a first quantized signal QS1 according to the first processed signal PS1. The first quantized signal QS1 may be seen as an output signal of the first DSM 300. Then, the first quantized signal QS1 is fed back to the first loop filter LF1 so that the first loop filter LF1 may generate the first processed signal PS1 according to the input signal XS and the first quantized signal QS1. The first quantized signal QS1 may include a clipping error EC smaller than a first predetermined value due to the extended full scale of the first quantizer QEX. That is, the first DSM 300 may mainly suppress the quantization error EQ, forming a quantization-error-shaping DSM. Only little clipping error EC is processed by the first DSM 300 so that the SNDR of the first DSM 300 may be maintained at an appropriate level.
The second DSM 310 is coupled to the first DSM 300, and is configured to receive the first quantized signal QS1 (i.e., the output signal of the first DSM 300) from the first DSM 300. The second DSM 310 includes a second loop filter LF2 and a second quantizer QT2. The second loop filter LF2 is configured to generate a second processed signal PS2. The second quantizer QT2 is coupled to the second loop filter LF2, and is configured to generate a second quantized signal QS2 according to the second processed signal PS2. The second quantized signal QS2 may be seen as an output signal of the series-connected DSM 30. Then, the second quantized signal QS2 is fed back to the second loop filter LF2 so that the second loop filter LF2 may generate the second processed signal PS2 according to the first quantized signal QS1 (i.e., the input signal of the second DSM 310) and the second quantized signal QS2. The second quantized signal QS2 may include a quantization error EQ smaller than a second predetermined value. That is, the second DSM 310 may mainly suppress the clipping error EC, forming a clipping-error-shaping DSM. Only little quantization error EQ is processed by the second DSM 310 so that the input range is extended. It should be noted that only little quantization error is allowed to be introduced in the second DSM 310 to maintain a high SNDR.
In one example, the first loop filter LF1 includes at least one first stage for receiving the input signal XS and the first quantized signal QS1. The second loop filter LF2 includes at least one second stage for receiving the first quantized signal QS1 (i.e., the input signal of the second DSM 310) and the second quantized signal QS2.
In one example, the first loop filter LF1 and the second loop filter LF2 may include (e.g., may be realized as) at least one integrator or at least one resonator. In one example, the first loop filter LF1 and the second loop filter LF2 may include (e.g., may be realized in) at least one discrete-time circuit or at least one continuous-time circuit.
In one example, the first quantizer QEX includes a first plurality of quantization levels, and the second quantizer QT2 includes a second plurality of quantization levels. A number of the first plurality of quantization levels is larger than a number of the second plurality of quantization levels. That is, the second quantizer QT2 may be a conventional quantizer (e.g., the quantizer QT of the DSM 10), and the first quantizer QEX may be an extended quantizer with more quantization levels than the conventional quantizer (e.g., the second quantizer QT2). The additional quantization levels included in the first quantizer QEX are beyond an original full scale to provide extra quantization levels. In this situation, most of the clipping error EC of the first quantizer QEX is temporarily avoided even if an input of the first quantizer QEX is large, which makes little clipping error EC processed by the first loop filter LF1.
In one example, the first quantizer QEX and the second quantizer QT2 perform a plurality of sampling operations at a same frequency. In one example, the first quantizer QEX and the second quantizer QT2 perform a plurality of sampling operations at different frequencies.
FIG. 4 shows waveforms of the input signal, internal node signal and output signal of the DSM 10 according to the prior art and the series-connected DSM 30 according to an example of the present invention. Taking a 20-bit input and a 6-bit resolution output as an example, the input signal XS is a 20-bit digital signal, while the output signal QS of the DSM 10 and the output signal QS2 of the series-connected DSM 30 are both 6-bit digital signals. Please refer to the top of FIG. 4 . For the DSM 10, when the input signal XS is large, the output signal QS exceeds a full scale 401 (i.e., the original full scale) of the quantizer QT, which leads to a large clipping error. Therefore, in-band components of the output signal QS suffer from a severe distortion source and is different from the input signal XS. Please refer to the bottom of FIG. 4 . As for the series-connected DSM 30, when the input signal XS is large, the first quantizer QEX provides a full scale 402 (i.e., the extended full scale) with additional quantization levels to avoid clipping error on the first quantized signal QS1. In addition, the clipping error is then processed by the second DSM 310 (e.g., the clipping-error shaping DSM), which maintains the output signal (i.e., the second quantized signal QS2) nearly same as the input signal XS.
FIG. 5 is a schematic diagram of a series-connected DSM 50 in z-domain according to an example of the present invention. The series-connected DSM 50 includes a first DSM 500 and a second DSM 510. The first DSM 500 may be the first DSM 300, and includes a first loop filter LF1 and a first quantizer QEX. The first loop filter LF1 may be a fifth-order DSM. The loop filter LF1 includes a plurality of transfer functions g1H, g2H, g3H, g4H and g5H and a plurality of DSM coefficients a1, a2, a3, a4, a5, b1, b2, b3 and b4, for receiving the input signal XS. The transfer function H is equal to z−1/(1−z−1). The first quantizer QEX introduces a quantization error EQ and feeds back little clipping error EC to the first loop filter LF1. The first quantizer QEX generates a quantized signal QS1 and transmits the quantized signal QS1 to the second DSM 510. The second DSM 510 may be the second DSM 310, and includes a second loop filter LF2 and a second quantizer QT2. The second loop filter LF2 may be a second-order DSM. The loop filter LF2 includes a plurality of transfer functions z−1 and DSM coefficients 1 and −2 which are both integers. The second quantizer QT2 introduces the clipping error EC. The second quantizer QT2 generates the output signal QS2 of the series-connected DSM 50. The plurality of transfer functions g1H, g2H, g3H, g4H, g5H and z−1 may be implemented as at least one integrator or at least one resonator, and may be implemented as at least one discrete-time circuit or at least one continuous-time circuit. All coefficients included in the second DSM 510 may be integers. The arithmetic results at each internal node may fall in a range of {−1, −31/32, −30/32, . . . , 0, . . . , +30/32, +31/32, +1}. That is, little quantization error is introduced in the second DSM 310. Thus, a SNDR of the series-connected DSM 50 is not affected by the second DSM 510 while an amplitude of the input signal XS is small.
FIG. 6 is a comparison diagram of expected SNDRs between the DSM 10 according to the prior art and the series-connected DSM 30 according to an example of the present invention. In FIG. 6 , the x-axis is an input amplitude of an input signal. The unit of the input amplitude is decibel relative to full-scale (dBFS). The y-axis is a SNDR. The unit of the SNDR is decibel (dB). A curve 600 is a schematic result of the DSM 10 with the aggressive noise-shaping ability. As shown in the curve 600 in FIG. 6 , the SNDR drops severely when the input amplitude becomes larger than a threshold Vth. A curve 602 is a schematic result of the DSM 10 for extending the input range. As shown in the curve 602 in FIG. 6 , although the SNDR does not drop as the input amplitude becomes larger than the threshold Vth, the SNDR is lower than that of the DSM 10 with the aggressive noise-shaping ability. A curve 610 is a schematic result of the series-connected DSM 30 according to an example of the present invention. As shown in the curve 610 in FIG. 6 , for the input amplitude smaller than the threshold Vth, the SNDR of the series-connected DSM 30 is similar to that of the DSM 10 with the aggressive noise-shaping ability, and is higher than that of the DSM 10 for extending the input range. As the input amplitude becomes larger than the threshold Vth, the SNDR of the series-connected DSM 30 drops slightly since only little clipping error is fed back to the loop filter. Thus, the performance of the series-connected DSM 30 is better than the DSM 10 since the series-connected DSM 30 maintains the high SNDR and simultaneously extends the input range.
FIG. 7 is a comparison diagram of simulated SNDRs between the DSM 10 according to the prior art and the series-connected DSM 30 according to an example of the present invention. In FIG. 7 , the x-axis is an input amplitude of an input signal. The unit of the input amplitude is dBFS. The y-axis is a SNDR. The unit of the SNDR is dB. A curve 700 is a simulation result of the DSM 10, and a curve 710 is a simulation result of the series-connected DSM 30. As shown in FIG. 7 , for the SNDR of 40 dB, the input amplitudes of the DSM 10 and the series-connected DSM 30 are −1.4 dBFS and 0.2 dBFS, respectively. That is, compared with the DSM 10, the series-connected DSM 30 extends the maximum input amplitude with 40 dB SNDR from −1.4 dBFS to 0.2 dBFS, and maintains the SNDR up to 60 dB for a 0-dBFS input amplitude.
FIG. 8 is a schematic diagram of a digital-input class-D audio amplifier 80. The digital input audio signal is oversampled and processed by an interpolator 810. Then, the oversampled signal is processed by a DSM 820 to perform a high resolution with a pulse-code modulation (PCM) signal, and is converted into a pulse-width modulation (PWM) signal by a PCM-to-PWM converter 830. The PWM signal is used to drive a class-D power stage 840 (e.g., an H-bridge power stage) of the digital-input class-D audio amplifier 80. When the digital audio signal is large, significant clipping error is induced in a conventional DSM (e.g., the DSM 10), leading to a severe degradation of total harmonic distortion plus noise (THD+N) when delivering high audio power levels to a speaker 850. Hence, the series-connected DSM 30 may be used in Class-D audio amplifier to prevent clipping error from limiting the input range of the amplifier.
FIG. 9 is a comparison diagram of performances between the DSM 10 applied to a digital-input class-D audio amplifier 80 according to the prior art and the series-connected DSM 30 applied to a digital-input class-D audio amplifier 80 according to an example of the present invention. In FIG. 9 , the x-axis is an audio power to the speaker 850 of the digital-input class-D audio amplifier 80. The unit of the audio power is watt (W). The y-axis is THD+N. The unit of the THD+N is percent (%). A curve 900 is a simulation result of the DSM 10 applied to the digital-input class-D audio amplifier 80, and a curve 910 is a simulation result of the series-connected DSM 30 applied to the digital-input class-D audio amplifier 80. As shown in FIG. 9 , as the THD+N reaches 1%, the output power of the digital-input class-D amplifier 80 applying the DSM 10 and the series-connected DSM 30 are 1 W and 1.4 W, respectively. That is, compared with the DSM 10, the series-connected DSM 30 extends 40% of output power with the THD+N of 1%, and audio quality under conditions of low audio power is not sacrificed.
To sum up, the present invention provides a series-connected DSM. The series-connected DSM achieves a large input range and a high SNDR simultaneously. Thus, the problem in the art is solved.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (9)

What is claimed is:
1. A series-connected delta-sigma modulator (DSM), comprising:
a first DSM, configured to receive an input signal, comprising:
a first loop filter, configured to generate a first processed signal; and
a first quantizer, coupled to the first loop filter, configured to generate a first quantized signal according to the first processed signal, and to feed back the first quantized signal to the first loop filter;
wherein the first loop filter generates the first processed signal according to the input signal and the first quantized signal fed back to the first loop filter, and the first quantized signal comprises a clipping error smaller than a first predetermined value; and
a second DSM, coupled to the first DSM, configured to receive the first quantized signal from the first DSM, comprising:
a second loop filter, configured to generate a second processed signal; and
a second quantizer, coupled to the second loop filter, configured to generate a second quantized signal according to the second processed signal, and to feedback the second quantized signal to the second loop filter;
wherein the second loop filter generates the second processed signal according to the first quantized signal and the second quantized signal fed back to the second loop filter, and the second quantized signal comprises a quantization error smaller than a second predetermined value.
2. The series-connected DSM of claim 1, wherein the first loop filter comprises at least one first stage for receiving the input signal and the first quantized signal.
3. The series-connected DSM of claim 1, wherein the second loop filter comprises at least one second stage for receiving the first quantized signal and the second quantized signal.
4. The series-connected DSM of claim 1, wherein the first loop filter and the second loop filter comprise at least one integrator or at least one resonator.
5. The series-connected DSM of claim 1, wherein the first loop filter and the second loop filter comprise at least one discrete-time circuit or at least one continuous-time circuit.
6. The series-connected DSM of claim 1, wherein the first quantizer comprises a first plurality of quantization levels, and the second quantizer comprises a second plurality of quantization levels.
7. The series-connected DSM of claim 6, wherein a number of the first plurality of quantization levels is larger than a number of the second plurality of quantization levels.
8. The series-connected DSM of claim 1, wherein the first quantizer and the second quantizer perform a plurality of sampling operations at a same frequency.
9. The series-connected DSM of claim 1, wherein the first quantizer and the second quantizer perform a plurality of sampling operations at different frequencies.
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