EP0996975B1 - Herstellungsverfahren eines feldeffekttransistors aus siliziumkarbid - Google Patents

Herstellungsverfahren eines feldeffekttransistors aus siliziumkarbid Download PDF

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Publication number
EP0996975B1
EP0996975B1 EP98934229A EP98934229A EP0996975B1 EP 0996975 B1 EP0996975 B1 EP 0996975B1 EP 98934229 A EP98934229 A EP 98934229A EP 98934229 A EP98934229 A EP 98934229A EP 0996975 B1 EP0996975 B1 EP 0996975B1
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EP
European Patent Office
Prior art keywords
substrate
silicon carbide
regions
conductive layer
electrically insulating
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Expired - Lifetime
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EP98934229A
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English (en)
French (fr)
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EP0996975A1 (de
EP0996975B8 (de
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Robert T. Fuller
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Harris Corp
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Harris Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/931—Silicon carbide semiconductor

Definitions

  • the present invention relates to a method of forming a field effect transistor (“FET”) device .
  • FET field effect transistor
  • Silicon carbide as a substrate is an excellent material for power devices due to its wideband gap and high blocking voltage.
  • dopants do not readily diffuse in silicon carbide substrate.
  • dopants have been implanted into a silicon carbide substrate to form lightly doped base regions and heavily doped source regions by using two separate masks.
  • J.N. Shenoy et al in "High-voltage double implanted power MOSFET's in 6H-SiC", IEEE Electron Device Letters, vol. 18, n o. 3, March 1997, pp. 93-95 discloses a silicon carbide field effect transistor including a silicon carbide substrate having an electrically insulating layer patterned on one surface thereof to form a gate insulator and an electrically conductive layer on the insulating layer to form a gate having a pair of spaced apart sidewalls.
  • lightly doped base regions are formed in the substrate located partially under the sidewalls of the gate and extending from the one surface of the substrate into an exposed substrate region, and heavily doped source regions are formed entirely within respective ones of the base regions.
  • a drain region is located on the surface of the substrate opposite the surface on which the gate is formed.
  • the base and source regions are formed by a double implantation process using two masks which need to be aligned and the source regions thus formed extend into the region of the substrate underlying the gate.
  • US-A-5 384 270 discloses a method of fabrication a silicon carbide field effect transistor wherein a gate electrode with inclined sidewalls is formed on the surface of a silicon carbide substrate and the gate electrode is used as a mask when injecting impurity ions into a region of the substrate not covered by the gate electrode to form a base region and in conjunction with a resist film mask when subsequently forming a source region within the base region.
  • the resulting base and source regions extend into the region of the substrate beneath the gate electrode.
  • the present invention avoids the use of two separate masks by providing a method of fabricating a field effect transistor as defined in claim 1.
  • a self-aligned implanted power FET preferably a MOSFET, in silicon carbide is fabricated with a single mask.
  • the cost for masks are decreased and alignment problems are diminished in relation to the two step technique.
  • Figure 1 illustrates a power FET device 10 formed in a monocrystalline silicon carbide substrate 12.
  • An insulative material gate 20 having a pair of spaced apart sidewalls 34, 36 is patterned on substrate 12.
  • Gate 20 comprises a first insulative material 14 overlayed with an electrically conductive layer 22.
  • Within substrate 12 is lightly doped base regions 16 located partially under sidewalls 34, 36 and extending into exposed substrate region 30. Associated with the lightly doped base regions 16 are heavily doped source regions 18 aligned with the exposed substrate 30.
  • a drain contact 32 is formed the FET 10.
  • first insulative material 14 is applied over a monocrystalline substrate 12.
  • substrate 12 is a starting wafer composed for example of monocrystalline silicon carbide.
  • First insulation material 14, preferably an oxide layer, is formed on the upper surface 38 of wafer 12.
  • Oxide layer 14 is formed by low temperature chemical vapor deposition techniques, epitaxially, or rapid thermal oxidation processes that form an insulative material ranging from 250 to 350 angstroms. These processes ensure first insulative material 14 is adequately attached on substrate 12 for further deposition of elements.
  • a layer of electrically conductive material 22, as illustrated in figure 2b is applied on insulative material 14.
  • Conductive material 22 ranges from 4,500 to 5,500 angstroms thick and can be applied by a low-pressure chemical vapor deposition (LPCVD) process.
  • LPCVD low-pressure chemical vapor deposition
  • conductive material 22 is polysilicon.
  • the next step entails depositing a layer of a second insulative material 24 on conductive material 22.
  • Second insulative material 24, preferably an oxide layer, is deposited by the same techniques as first insulation material 14.
  • second insulation material 24, preferably, is thinner than the desired thickness of substrate 12.
  • an etch resistant mask 40 is patterned on second insulative material 24. Portions of second insulative material 24 not aligned with mask 40 are removed by conventional etching techniques, such as reactive ion etching, to expose first portion 26 of conductive material 22.
  • a first dopant of one polarity is implanted in substrate 12 aligned with first portion 26.
  • the first dopant is a high implant energy source used to penetrate conductive material 22, first insulative material 14 and substrate 12.
  • the implant is a dose of 2e12, energy of 360KeV of boron and forms a lightly doped base regions 16, commonly a p-well.
  • Second insulative material 24 and mask 40 block the boron ions from penetrating into substrate 12 aligned with material 24 and mask 40.
  • mask 40 is removed exposing the remaining second insulation material 24.
  • a third insulative material 28 is formed on the sidewalls of second insulative material 24. Portions of conductive material 22 not aligned with second insulative material 24 and third insulative material 28, preferably a nitride material, is removed. Conductive material 22 is removed by conventional etching techniques disclosed above. Thereby, exposing area 30 of the first insulative material 14 that is smaller than first portion 26.
  • a second dopant of opposite polarity to the first dopant is then implanted in substrate 12 aligned with area 30.
  • the second dopant normally forms a heavily doped source regions 18, commonly a n-well, with arsenic ions. Heavily doped source regions 18 are located within associated lightly doped base regions 16.
  • Second insulative material 24 and third insulative material 28 blocks the arsenic ions from entering the underlying substrate 12.
  • remaining second insulative material 24 and third insulative material 28 are removed.
  • This removal process preferably, occurs by known stripping procedures known in the semiconductor industry.
  • remaining conductive material 22 and first insulation material 14 aligned with conductive material 22 is gate 20.
  • first insulation material 14 not aligned with conductive material 22 can be removed as well by conventional semiconductor processes.
  • Underside of substrate 12 is subsequently planarized to a desired thickness. Once the underside of substrate 12 is planarized, a drain contact 32 is applied to the underside. In one embodiment of drain contact 32, underside of substrate 12 is metalized.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Junction Field-Effect Transistors (AREA)

Claims (5)

  1. Verfahren zur Herstellung eines Feldeffekttransistors (10) in einem monokristallinen Substrat (12) aus Siliziumkarbid, folgende Schritte umfassend:
    a) Bilden einer ersten elektrisch isolierenden Schicht (14) auf einer Oberfläche des Siliziumkarbidsubstrats (12),
    b) Abscheiden einer elektrisch leitenden Schicht (22) auf der Oberfläche der ersten elektrisch isolierenden Schicht (14),
    c) Abscheiden einer zweiten elektrisch isolierenden Schicht (24) auf der Oberfläche der elektrisch leitenden Schicht (22),
    d) teilweises Entfernen der zweiten elektrisch isolierenden Schicht (24), um erste freiliegende Abschnitte (26) der elektrisch leitenden Schicht (22) zu bilden und um zwei erste, voneinander beabstandetete Bereiche des monokristallinen Substrats (12) aus Siliziumkarbid zu definieren, um Basis-Bereiche zu bilden,
    e) leichtes Implantieren eines ersten Dotierstoffes einer ersten Polarität in die ersten, voneinander beabstandeten Bereiche des monokristallinen Substrats (12) aus Siliziumkarbid durch die ersten freiliegenden Bereiche (26) der elektrisch leitenden Schicht (22) und durch die darunterliegenden Abschnitte der ersten elektrisch isolierenden Schicht, um leicht dotierte Basis-Bereiche (16) in den ersten, voneinander beabstandeten Bereichen zu bilden,
    f) Bilden eines dritten elektrisch isolierenden Materials (28) an den Seitenwandungen der zweiten elektrisch isolierenden Schicht (24), um zweite freiliegende Abschnitte (26) der elektrisch leitenden Schicht (22) zu definieren,
    g) Entfernen der zweiten elektrisch leitenden Schicht (22) an den zweiten freiliegenden Bereichen, um freiliegende Abschnitte (30) der ersten elektrisch isolierenden Schicht zu bilden und um zweite, voneinander beabstandete Bereiche des monokristallinen Substrats (12) aus Siliziumkarbid in den entsprechenden ersten, voneinander beabstandeten Bereichen zu definieren,
    h) starkes Implantieren eines zweiten Dotierstoffes einer zweiten, zur ersten Polarität entgegengesetzten Polarität in die zweiten, voneinander beabstandeten Bereiche des monokristallinen Substrats (12) aus Siliziumkarbid durch die freiliegenden Abschnitte (30) der ersten elektrisch isolierenden Schicht, um stark dotierte Source-Bereiche (18) in den zweiten, voneinander beabstandeten Bereichen (12) innerhalb der leicht dotierten Basis-Bereiche (16) zu bilden, wodurch sich die Basis-Bereiche zu der einen Oberfläche des Substrats erstrecken, und
    i) Entfernen des dritten elektrisch isolierenden Materials und der Reste der zweiten elektrisch isolierenden Schicht, um nach Schritt h) ein Gate (20) zu bilden.
  2. Verfahren nach Anspruch 1, wobei die zweite elektrisch isolierende Schicht dünner als eine festgelegte Dicke ist und die andere Oberfläche des monokristallinen Substrats (12) aus Siliziumkarbid gegenüber der einen Oberfläche derart planarisiert wird, dass die Dicke des monokristallinen Substrats (12) aus Siliziumkarbid auf die festgelegten Dicke reduziert wird.
  3. Verfahren nach Anspruch 1 oder 2, wobei das dritte elektrisch isolierende Material ein Nitridmaterial ist.
  4. Verfahren nach einem der Ansprüche 1 bis 3, wobei die erste und die zweite elektrisch isolierende Schicht aus Oxidmaterialien bestehen.
  5. Verfahren nach einem der Ansprüche 1 bis 4, wobei die elektrisch leitende Schicht aus einem Polysiliziummaterial besteht.
EP98934229A 1997-06-30 1998-06-30 Herstellungsverfahren eines feldeffekttransistors aus siliziumkarbid Expired - Lifetime EP0996975B8 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US884726 1997-06-30
US08/884,726 US5877041A (en) 1997-06-30 1997-06-30 Self-aligned power field effect transistor in silicon carbide
PCT/US1998/013703 WO1999000833A1 (en) 1997-06-30 1998-06-30 Self-aligned power field effect transistor in silicon carbide

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EP0996975A1 EP0996975A1 (de) 2000-05-03
EP0996975B1 true EP0996975B1 (de) 2011-01-05
EP0996975B8 EP0996975B8 (de) 2011-09-14

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US (1) US5877041A (de)
EP (1) EP0996975B8 (de)
JP (1) JP4173629B2 (de)
KR (1) KR100592401B1 (de)
AT (1) ATE494630T1 (de)
AU (1) AU8380098A (de)
CA (1) CA2296103A1 (de)
DE (1) DE69842085D1 (de)
WO (1) WO1999000833A1 (de)

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Also Published As

Publication number Publication date
DE69842085D1 (de) 2011-02-17
JP4173629B2 (ja) 2008-10-29
KR20010020583A (ko) 2001-03-15
JP2001509637A (ja) 2001-07-24
US5877041A (en) 1999-03-02
ATE494630T1 (de) 2011-01-15
AU8380098A (en) 1999-01-19
EP0996975A1 (de) 2000-05-03
EP0996975B8 (de) 2011-09-14
CA2296103A1 (en) 1999-01-07
KR100592401B1 (ko) 2006-06-22
WO1999000833A1 (en) 1999-01-07

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