EP0974112A1 - Procede pour la conception de circuits numeriques et integres complexes et structure de circuit pour la mise en oeuvre de ce procede - Google Patents

Procede pour la conception de circuits numeriques et integres complexes et structure de circuit pour la mise en oeuvre de ce procede

Info

Publication number
EP0974112A1
EP0974112A1 EP98930641A EP98930641A EP0974112A1 EP 0974112 A1 EP0974112 A1 EP 0974112A1 EP 98930641 A EP98930641 A EP 98930641A EP 98930641 A EP98930641 A EP 98930641A EP 0974112 A1 EP0974112 A1 EP 0974112A1
Authority
EP
European Patent Office
Prior art keywords
alu
circuit structure
ram
circuit
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98930641A
Other languages
German (de)
English (en)
Inventor
Andreas Frank Böthel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19714756A external-priority patent/DE19714756A1/de
Priority claimed from DE19731043A external-priority patent/DE19731043A1/de
Application filed by Individual filed Critical Individual
Publication of EP0974112A1 publication Critical patent/EP0974112A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318591—Tools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices

Definitions

  • the invention relates to a method for designing complex, digital, integrated circuits to ensure a testability of at least 95% error coverage with automatically generated test patterns.
  • ASICs Complex, digital, integrated circuits
  • registers RAM structures
  • combinatorial elements e.g., combinatorial elements
  • Methods for designing complex, digital, integrated circuits (ASIC's) include the following basic procedural steps:
  • VHDL Hardware Description Language
  • testability of an ASIC is required during the manufacturing phase of the ASIC in order to recognize manufacturing-related defects of the manufactured ASICs in a short time and to sort out defective ASICs.
  • the fault coverage of an ASIC is the measure of how many internal line networks of an ASIC can be checked by test samples for manufacturing-related defects, especially short-circuit faults. In practice, this measure, including TeSt coverage, is at least 95% of all internal line networks of an ASIC. Test patterns describe cyclic state sequences, which are applied to the matterss1eititch an ASIC and output lines to the off ⁇ an ASIC are expected with accuracy.
  • ATPG Automatic Test Pattern Generator
  • BIST Built-In Self-Test
  • Test structures must be implemented so that ATPG can calculate test patterns with a high error coverage in a complex ASIC. (Literature reference: "Self-test of digital circuits", M. Gerner / B. Müller / G. Sandweg, Verlag Oldenburg).
  • a synthesis-capable RTL model can be created using ECAD tools, for example behavior compiler from Synopsys Inc. ("Behavioral Compiler Methology Note", version 3.3a, April 1995, Synopsys Inc .). After one of the two said paths has been completed and a synthesis of the finished RTL models is done, the circuit structure is in the form of registers, before combinatorial ⁇ graphic elements, RAM modules.
  • test structures can now be defined in detail in order to ensure that ATPGs can be used to generate the test patterns with defined error coverage. This is done by inserting special test registers (scan registers), automatic test generators especially for RAM cells (BIST cells).
  • scan registers special test registers
  • BIST cells automatic test generators especially for RAM cells (BIST cells).
  • BIST cells RAM cells
  • ECAD software test compiler from Synopsys Inc.
  • Table 1 shows the principle of the method of the preferred embodiment according to the invention.
  • Table 1 and Table 2 show t he V er f ahrens steps (Table 1) and known as the results thereof, f o l gen d M ilestones (Table 2), the Ver f a h proceedings according to the invention of the preferred embodiment (see Fig 1 )
  • P recondition for the start of the process ( Figure 1 / Table 1 / Table. 2) is to provide an ASIC - Specification 0 which th at least the functional Verha l of describing to be designed ASICs with textual resources.
  • a circuit estimate 2 is made according to the amount of work involved in register and RAM structures.
  • a prerequisite for starting the method according to the invention (FIG. 1 / table 1 / table 2) is the provision of an ASIC specification 0, which at least describes the functional behavior of the ASIC to be designed using textual means.
  • a circuit estimate 2 is made according to the amount of work involved in register and RAM structures.
  • This circuit estimate 2 is the basis of the circuit configuration 3, in which the register and RAM cells are defined in number and structure to form a functioning circuit. In practice, this circuit is usually described with HDL language, for example VHDL.
  • test structures are added to this circuit (also ATPG configuration 4). These include, for example, BIST cells for the RAM cells used, test multiplexers for the inputs and outputs of the ASIC or scan register.
  • parts of the test structures are also added during ECAD design 10 with ECAD programs, for example Test Compiler from Synopsys Inc. This route is preferred especially for scan registers and the associated connections to scan chains.
  • ECAD draft 10 synthesis, layout of the implemented circuit and generation of the test pattern set 11 using ATPG.
  • test pattern set 11 is also transferred for production, which ensures the quality during the production of the ASIC.
  • the invention further relates to a circuit structure for carrying out the method as disclosed in claims 8 to 14 and a circuit structure for processing multiple data streams for describing or modeling digital circuits, which can also function as a digital signal processor, hereinafter referred to as DSP, as it can is defined in claims 15 to 21.
  • DSP digital signal processor
  • Circuit structure describes a template or an executed digital circuit for the realization of digital circuits of the above-mentioned task.
  • Data streams consist of incoming and outgoing signals from combined sub-functions of the overall function.
  • complex formats of data streams for example a serial bit stream with a bit-coded data format, or only simple, parallel data buses as data streams, for example in a digital signal processor.
  • Processing tasks consist either in processing the complex formats of the data streams, for example decoding a serial bit stream, or in performing special operations for simple parallel data formats, for example complex arithmetic operations in a DSP.
  • DSP complex arithmetic operations
  • a description or model of a circuit can also mean descriptions in the register transfer level or behavioral descriptions of any kind, for example in VHDL or Verilog. These can be converted into a circuit form with known means (circuit synthesis), with which circuitry implementation can take place.
  • MPS microprocessor systems
  • a bus system connects the above-mentioned elements to one another (for example in the published documents DE 36 36 095, DE 29 44 419 or in the patent DE 43 12 090 C2).
  • the task is implemented in an MPS by assigning the different data streams to the peripheral connection options of an MPS and by pre-assigning the RAM unit with a microcode. This ensures that the MPS polls each individual state of all incoming lines of the data streams one after the other and stores them in registers or RAM cells. With the help of a central ALU or control logic, new states of the outgoing lines of all data streams are calculated and modified. This means that only one ALU or control logic for controlling the RAM unit or the registers is used to process the data streams. This means that the data streams are combined to form an overall data stream. The function of the individual ALU or control logic must therefore solve all processing tasks of the data streams equally.
  • the ALU or control logic is thus designed with relatively simple arithmetic and logic functions, so that different complex processing functions of the individual individual data streams have to be processed in many cycle steps.
  • VLIW Very Long Instruction Word
  • the arithmetic data manipulation is parallelized using several ALU units. This makes it possible to reduce the number of clock cycles.
  • these ALU units do not process the RAM / register control. As with the simple MPS with only one ALU unit, this can only be influenced centrally. This means that, for example for complex address calculations, the address data via the ALU units must first be modified as normal data information and stored in an address register.
  • MPS are specified as hardware, for example as a finished microchip, or as a CAD system description for integration into a larger ASIC (Application Specific Integrated Circuits) in CAD design, in practice also referred to as a core or macro cell.
  • ASIC Application Specific Integrated Circuits
  • the second implementation group includes digital circuits in which the complex processing tasks are implemented purely in terms of circuitry.
  • This type of digital circuit is usually implemented using a hierarchical design method (top down).
  • Sub-modules of the overall circuit are usually as sequential state machines, for example as Mealy or Moore machines, designed.
  • This form of implementation is called special circuit in the following.
  • the processing of a data stream usually requires a large number of clock cycles. These are required to receive and store the information of all incoming signal streams. After reading the microcode from RAM, this information is modified in the ALU and made available to the outgoing signal streams again at the specified time.
  • the strictly sequential processing results from the use of only one ALU or only one control logic (see superscalar or VLIW machines) with relatively simple, generally usable logical or arithmetic basic functions, which is used for processing all data streams. This requires that the MPS operate at a higher clock frequency, relative to the highest frequency of a data stream. During the design process, this creates greater requirements with regard to the delay times of the hardware to be used.
  • the invention has for its object to provide a circuit structure for processing multiple data streams, from which a digital circuit can be described and modeled with reduced development effort. This should ensure flexibility of function even after completion. Furthermore, the required electrical operating power is to be reduced and testability in an early phase of the design is to be ensured with little effort from test structures. Only a few clock cycles are required for the gradual processing of the data streams.
  • the circuit should also be suitable for many applications in the processing of data streams. In addition, a high level of clarity of the circuit should be ensured by a few sub-modules. guaranteed to modify an existing circuit with little special knowledge.
  • circuit structure which has at least the following elements (see FIGS. 2, 3, 4):
  • an ALU (3c) is assigned, the assigned ALU (3c) is specially designed for the processing task (11, 12, 13, 14, 15) and processes the processing task comprehensively (IDLE, TRA3.0 / REC3. 0 to TRA3. N / REC3.
  • the assigned ALU (3c) is generated by the controller (11, 13, 14 or 3d, 3f, 3g or 4a, 4c, 4d or 6a, 6c, 6d) and the input data (12 or 3e or 4b or 6b) for the RAM (7) or the registers (6), the control is fed back (6a) or the RAM or register output data (9, 10) for the assigned ALU (3c), there are at least two ALU units (le, 2e, 3c) assigned for data streams (1,2,3) , if an ALU function cannot be divided into several assigned ALU units with the aforementioned features.
  • a circuit structure with the properties mentioned is characterized by the following advantageous secondary points (see FIGS. 2, 3, 4, 5, 6: Clock-controlled registers are inserted (6,8) so that a large part of all ALU functions lie in a signal path between a minimum number of register stages (6,8).
  • the ALU units alternately generate the RAM write accesses.
  • Outgoing signal lines lc, ld, 2d, 2c, 3b) are controlled with every clock change.
  • the circuit structure described can be created as a template from which specific digital circuits are developed or from which a model is created for simulation.
  • the circuit structure or circuits derived from its template, have test structures, some of the test structures serving the RAM and the other test structures being inserted in such a way that the ALU functions can be observed.
  • Each ALU (27, 28, 29, 30) is assigned a part (21, 22, 23, 24, 25) of the RAM area (26) in which the assigned ALU can carry out write operations.
  • Fig. 2 shows the block diagram of the preferred embodiment
  • Fig. 3 shows a basic sequence for operating the
  • Circuit structure Fig. 4 shows a basic sequence for operating the
  • FIG. 5a shows a basic circuit of the circuit structure as a DSP
  • FIG. 5b shows an example of a RAM subdivision for the ALU write accesses (based on FIG. 5a).
  • the preferred embodiment of a circuit structure processes three data streams 1, 2, 3.
  • the first data stream 1 consists of 2 incoming signals, each with an outgoing (outgoing) and incoming (incoming) 1-bit line la, lc and an outgoing data bus ld with a bus width of u and one incoming.
  • Data bus lb with the bus width of z.
  • the second data stream 3 consists of an ank. 1-bit line 3a and a ner ded. 1-bit line 3b.
  • 3 ALU units le, 2e, 3c are assigned to these data streams, the functions of which are adapted to the processing tasks of the data streams.
  • RAM control signals lf, lg, 2f, 2g, 3f, 3h run from each ALU, which, like the ALU address lines li, 2i, 3d and data lines lh, 2h, 3c, are routed to the ALU-MUX 4 module.
  • ALU-MUX 4 module all inputs are combined into one control group each, consisting of control signals 4c, 4d, as well as address 4a and RAM input data bus 4b.
  • a register stage 6 consisting of (x + y + 2) registers, is interposed, for example D flip-flops, which are controlled by the clock 5.
  • the register outputs act as RAM control.
  • the address lines 6a are fed back to the ALU units le, 2e, 3c. This is also done with the RAM output data 10 after it also passes through a register stage 8, which comprises y registers, controlled with the clock 5.
  • the RAM 7 usually consists of a memory field, an address decoder and control logic.
  • FIG. 3 shows the inner realization principle of the ALU3 3c.
  • Line 3a serves as inputs for the ALU3 components SUB-ALU3.1 11, for generating the ALU3 address bus 3d.
  • the ALU3 data input bus 3e is generated via the SUB-ALU 3.2 12.
  • the control logic 3.1 13 generates the ALU 3 control line Read 3f.
  • the control logic 3.2 14 serves to generate the ALU3 control line Write 3g and with SUB-ALU3.2 15 the generated line 3b is generated.
  • the ALU1 le and ALU 2 2e are implemented in a similar way.
  • the data can be manipulated, for example by a data bit (a bit line from RAM Output data bus 10) with the previous data bit (another bit line from RAM output data bus 10) via XOR logic (implemented in SUB-ALU 3.2 12 and SUB-ALU 3.3 15 Fig. 3).
  • this link can be activated or deactivated in the ALU.
  • Table 3 lists the states and their functional relationship in the overall circuit.
  • Table 4 lists all the actions that are received during the individual status changes or are generated by the circuit. (Continuation of table 3: Explanation of the states in FIG. 4)
  • the power consumption of the overall circuit is limited because only a few power-intensive edge-controlled registers are used.
  • the area requirement of the circuit is less because a large part of the system states and data are in the RAM, which is usually optimized in terms of the area requirement (for ASICs), because only a few (test) registers exist and because a large part of all combinatorial elements used are between two register levels. This makes it possible to eliminate redundant combinatorics with relatively simple means of Boolean algebra. This is usually done automatically by a synthesis program if the circuit is available as a synthesis-capable description, VHDL or Verilog. (In the case of special circuits, the combinatorial elements lie between many register levels.) 4.
  • the spatial separation of combinatorial elements and the coherent structures of the registers prevents problems in the ASIC layout (see clock skew).
  • the circuit structure is particularly easy to implement with HDL programming languages, VHDL or Verilog, since there are only a few submodules.
  • the ALU submodules in particular can also be implemented by developers with relatively little knowledge of the HDL programming languages mentioned. It also allows templates
  • the circuit structure can be designed to be functionally flexible. This depends on how specifically the individual ALU functions are designed for the processing task. Relatively simple ALU functions can process processing tasks more universally by processing RAM contents in a microcode-like MPS manner. The functional sequence can then also be influenced after production as an ASIC by modifying the microcode.
  • a data stream with ALU can take over the function of loading, for example an initial state, or reading out the RAM content.
  • Point 6 just described is the starting point for a further possibility of using the circuit structure described. Attention is drawn to the fact that even a circuit structure with the least flexibility, ie close to a special circuit, has the advantages mentioned (see points 1 to 5).
  • the circuit structure which is similar in function and structure to an MPS or a DSP, is shown in principle in FIG. 5a.
  • special arithmetic functions are used as processing tasks of the data streams of the same format.
  • a structure with 4 ALU blocks is shown, whereby an ALU 27 exists, which has conventional functionality, and primarily serves the interface to standard inputs / outputs 16, 17.
  • the 4th ALU block 30 is the ALU with the specialized function. This is intended to serve an external control object 18 and thus represents the control function of a control chain. All data are routed to a data bus 20 here. Furthermore, the address control of this DSP is influenced in all ALU functions (27, 28, 29, 30).
  • the standard ALU 27 and standard I / O 17 have write access 25 to the entire RAM area 26. This allows presettings, for example for the ALU 30 controller, to be made. After initialization, this write access is limited to part of the RAM area 21.
  • the ALU blocks 28, 29, 30 can only access limited RAM areas 22, 23, 24.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

Pour les flux de données d'un système, chaque bloc fonctionnel est affecté d'une fonction arithmétique ou logique (bloc ALU) formant une commande RAM. Les blocs ALU sont spécialisés pour les tâches de traitement individuelles des flux de données. L'état actuel de l'adresse RAM ainsi que des données de sortie RAM sont rebouclés aux blocs ALU. En régime de fonctionnement, les blocs ALU fournissent mutuellement des accès en écriture sur le RAM. A chaque cadence, des accès en lecture de tous les blocs ALU peuvent être réalisés et, de ce fait, commander les lignes de signaux détachées des flux de données. Les registres sont insérés de façon que les blocs ALU soient disposés entre les étapes de registres, afin d'assurer une génération automatique de motifs de contrôle avec des programmes CAE connus. Une faible dépense en structures de contrôle garantit une bonne aptitude au contrôle du circuit de base avec un jeu minimum de motifs de contrôle dans une phase antérieure de la conception du circuit. La structure de circuit conforme à l'invention peut être également réalisée sous la forme d'un processeur de signaux numérique.
EP98930641A 1997-04-10 1998-04-08 Procede pour la conception de circuits numeriques et integres complexes et structure de circuit pour la mise en oeuvre de ce procede Withdrawn EP0974112A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE19714756A DE19714756A1 (de) 1997-04-10 1997-04-10 Schaltungsstruktur zur Verarbeitung mehrerer Datenströme zum Beschreiben oder Modellieren digitaler Schaltungen
DE19714756 1997-04-10
DE19731043 1997-07-19
DE19731043A DE19731043A1 (de) 1997-07-19 1997-07-19 Verfahren zum Entwurf komplexer, digitaler und integrierter Schaltungen (ASIC's)
PCT/DE1998/001019 WO1998045794A1 (fr) 1997-04-10 1998-04-08 Procede pour la conception de circuits numeriques et integres complexes et structure de circuit pour la mise en oeuvre de ce procede

Publications (1)

Publication Number Publication Date
EP0974112A1 true EP0974112A1 (fr) 2000-01-26

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EP98930641A Withdrawn EP0974112A1 (fr) 1997-04-10 1998-04-08 Procede pour la conception de circuits numeriques et integres complexes et structure de circuit pour la mise en oeuvre de ce procede

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Country Link
US (1) US6557157B1 (fr)
EP (1) EP0974112A1 (fr)
JP (1) JP2000515658A (fr)
WO (1) WO1998045794A1 (fr)

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JP4029959B2 (ja) * 2001-08-31 2008-01-09 シャープ株式会社 演算器アロケーション設計装置および演算器アロケーション設計方法
WO2007037017A1 (fr) * 2005-09-29 2007-04-05 Fujitsu Limited Procédé et dispositif d'analyse de puissance consommée
JP4396987B2 (ja) * 2006-02-08 2010-01-13 シャープ株式会社 動作合成装置および動作合成方法、ディジタル回路の製造方法、動作合成制御プログラム、可読記録媒体
CN105136138B (zh) * 2015-08-05 2018-04-10 西安电子科技大学 基于核极限学习机的x射线脉冲星光子信号辨识方法

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US5263169A (en) * 1989-11-03 1993-11-16 Zoran Corporation Bus arbitration and resource management for concurrent vector signal processor architecture
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US5222030A (en) * 1990-04-06 1993-06-22 Lsi Logic Corporation Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof
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Publication number Publication date
WO1998045794A1 (fr) 1998-10-15
US6557157B1 (en) 2003-04-29
JP2000515658A (ja) 2000-11-21

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