EP0966762A1 - JONCTION A ZONES nLDD HYBRIDES As/P AVEC FONCTIONNEMENT A TENSION D'ALIMENTATION MOYENNE POUR MICROPROCESSEURS A GRANDE VITESSE - Google Patents

JONCTION A ZONES nLDD HYBRIDES As/P AVEC FONCTIONNEMENT A TENSION D'ALIMENTATION MOYENNE POUR MICROPROCESSEURS A GRANDE VITESSE

Info

Publication number
EP0966762A1
EP0966762A1 EP98904623A EP98904623A EP0966762A1 EP 0966762 A1 EP0966762 A1 EP 0966762A1 EP 98904623 A EP98904623 A EP 98904623A EP 98904623 A EP98904623 A EP 98904623A EP 0966762 A1 EP0966762 A1 EP 0966762A1
Authority
EP
European Patent Office
Prior art keywords
region
hybrid
nldd
arsenic
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98904623A
Other languages
German (de)
English (en)
Inventor
Deepak Kumar Nayak
Rajat Rakkhit
Ming-Yin Hao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP0966762A1 publication Critical patent/EP0966762A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode

Definitions

  • This invention relates generally to the manufacture of high performance semiconductor devices and, more particularly, to the manufacture of submicron semiconductor devices, and even more particularly, to the manufacture of submicron semiconductor devices having hybrid nLDD regions doped with arsenic and phosphorous.
  • the semiconductor industry is increasingly characterized by a growing trend toward fabricating more complex circuits on a given semiconductor chip. This is being achieved by reducing the size of individual devices within the circuits and spacing the devices closer together. The reduction of the size of individual devices and the closer spacing has the potential to bring about improved electrical performance .
  • the present invention is directed to a method of manufacturing a semiconductor device having hybrid nLDD regions doped with arsenic and phosphorus .
  • the drain and source regions are formed by implanting either arsenic or phosphorus ions.
  • the hybrid nLDD regions are implanted with arsenic ions in a concentration of 1-10E14 ions per cm 2 .
  • the hybrid nLDD regions are implanted with phosphorus ions in a concentration of 1-10E13 ions per cm 2 .
  • the present invention is further directed to a semiconductor device having hybrid nLDD regions .
  • the hybrid nLDD regions are doped with arsenic ions in a concentration of 1-10E14 ions per cm 2 and with phosphorus ions in a concentration of 1-10E13 ions per cm 2 .
  • the semiconductor device has source and drain regions doped with either phosphorous ions or arsenic ions.
  • the semiconductor device has a layer of suicide formed on the surface of the substrate over the source and drain regions .
  • Figure 1 shows a portion of a wafer substrate with an active region in the substrate defined by isolation trench regions and a layer of gate oxide formed in the substrate between the isolation trench regions .
  • Figure 2 shows the portion of the wafer shown in Figure 1 with a layer of polysilicon on the wafer and a layer of photoresist on the layer of polysilicon.
  • Figure 3 shows the portion of the wafer shown in Figure 2 with the photoresist layer selectively removed by photolithography to define the gate region.
  • Figure 4 shows the portion of the wafer shown in Figure 3 with a polysilicon gate and a gate oxide region formed by etching the polysilicon layer and removing the remaining photoresist layer.
  • Figure 5 shows protective layers formed on selected portions of the portion of the wafer shown in Figure 4 and shows the implantation of arsenic ions to form the nLDD regions .
  • Figure 6 shows the implantation of phosphorus ions to form the hybrid nLDD regions .
  • Figure 7 shows the formation of sidewall spacers around the gate and the protective layers removed.
  • Figure 8 shows the implantation of P or As ions to form the source and drain regions .
  • Figure 9 shows the semiconductor device with the source and drain regions formed, the hybrid nLDD regions formed, a suicide layer formed over the source and drain regions, and electrical contacts made to the source, drain, and gate regions.
  • Figure 10 is a graphical representation of the experimental results of the I dsat life time as a function of l/Vdd for a device having phosphorous only junctions, a device having arsenic/phosphorous hybrid junctions, and a device having arsenic only junctions.
  • Figure 11 is a graphical representation of the experimental results showing the ring oscillator delay/stage for a device having phosphorous only junctions, a device having arsenic/phosphorous hybrid junctions, and a device having arsenic junctions with all three having an L eff of 0.20 microns.
  • Figure 12 is a graphical representation of the experimental results showing the ring oscillator delay/stage for expected nominal L e££ for three different junctions; phosphorous only junctions, arsenic/phosphorous hybrid junctions, and arsenic only junctions.
  • Figure 13 is a graphical representation of the experimental results of the ring oscillator delay/stage for expected subnominal L eff for three different junction; phosphorous only junctions, arsenic/phosphorous hybrid junctions, and arsenic only junctions.
  • Figure 14 is a graphical representation of the experimental results showing the comparison of off-state leakage for arsenic/phosphorous hybrid junctions and for arsenic only junctions.
  • Figure 15 is a graphical representation of the experimental results of the effect of arsenic/phosphorous junction doping on substrate current.
  • the device 100 is made up of a substrate material 102 selectively doped.
  • the substrate is doped with a p type dopant to provide a p-doped substrate.
  • the method of obtaining a p- doped substrate is well known in the semiconductor art and will not be discussed.
  • the substrate 102 has trench isolation regions, indicated at 104 and 106, formed to define an active region, indicated at 108, and to isolate the active area 108 from other parts of the wafer.
  • the isolation regions 104 and 106 are shown as being trench oxide regions. Any method of forming trench oxide regions can be used to form the isolation regions.
  • An alternate method is to form oxide regions, known in the art as field oxide (FOX) regions.
  • the device 100 is shown with a layer of oxide 110 formed on the surface of the active region 108 between the isolation regions 104 and 106.
  • FOX field oxide
  • One method, as discussed here, is to form a layer of oxide and then selectively remove the portions of the oxide that will not be needed.
  • Another method is to mask the device with a protective layer (to form a protective layer over the portions of the device for which an oxide layer is not wanted) and to grow or form an oxide layer on the portions of the device that are not masked. Either method could be used and would be the choice of the process designer.
  • FIG. 2 there is shown the device 100 with a layer of polysilicon 200 formed on the surface of the wafer 100 shown in Figure 1 and a layer of photoresist 202 formed on the layer of polysilicon 200.
  • a layer of polysilicon 200 formed on the surface of the wafer 100 shown in Figure 1 and a layer of photoresist 202 formed on the layer of polysilicon 200.
  • like numeral designations will be used for like elements.
  • Figure 3 shows the device 100 with the photoresist layer 202 selectively removed to define a gate region which will be subsequently formed on the surface of the substrate 102.
  • Figure 4 shows the device 100 shown in Figure 3 with a gate 400 formed on the gate oxide region 402.
  • the method of forming the gate 400 is well known in the art and can be accomplished by conventional methods.
  • the gate 400 is typically formed of polysilicon and selectively doped to make it conductive.
  • Figure 5 shows the device 100 with protective photoresist layers 500 and 504 formed on portions of the device 100 to protect the device where nLDD is not required.
  • Arrows, indicated at 506, represent the implantation of arsenic ions (As ions) into and beneath the surface 508 of the substrate 102.
  • the implantation of the arsenic ions is at a concentration of 1-10E14 (1-lOxlO 14 ) and forms regions known as nLDD regions, indicated at 510 and 512.
  • nLDD means a Lightly Doped Drain_region doped with an n type dopant. It is conventional in the semiconductor art to designate a region as an LDD region even if the region is or will be doped with medium or high doses. These regions are also referred to as source/drain extensions.
  • Figure 6 shows the device as shown in Figure 5 with the protective layers 500 and 502 still in place and arrows, indicated at
  • phosphorous (P) ions into and beneath the surface 510 of the substrate 102 to form the hybrid nLDD regions 600 and 602.
  • the phosphorous ions penetrate further into the substrate as indicated at 600 and 602.
  • the implantation of ions into the surface of a substrate causes the surface to be damaged.
  • an annealing process is done to cure the surface damage and also to drive the ions to a selected depth in the substrate. This annealing process can be done at any point subsequent to the implantation of the ions.
  • Figure 7 shows the device shown in Figure 6 with the protective layers 500 and 502 removed and sidewall spacers 700 and 702 formed around the gate 400.
  • Figure 8 shows the device 100 with protective layers 800 and 802 formed on selected surfaces of the device 100. It is noted that some surfaces may not require a protective surface for some processes. For example, a trench oxide surface such as those at 104 and 106 may not require a protective surface. However, this would be known by a person of ordinary skill in the semiconductor processing art and will not be further addressed. Also shown in Figure 8 is the implantation of ions, indicated by arrows 804. The ion implantation at this point in the manufacturing process is to form the source region 806 and drain region 808. The ion implantation can be either phosphorous ions or arsenic ions at a sufficient concentration to form the source and drain regions. The required concentration would be dependent upon the particular process and application and would be determinable by a person of ordinary skill in the semiconductor processing art and the determination of the required concentration is not considered to constitute undue experimentation.
  • Figure 9 shows the device 100 with the source and drain regions formed at 806 and 808, respectively and the protective layers 800 and 802 removed.
  • suicide layers which are optional are indicated at 902 and 904 and are shown formed on the source and drain regions 906 and 908, respectively.
  • Electrical connections to the source region 906, the gate 400, and the drain region 908 are indicated at 910, 912, and 914, respectively.
  • Figure 10 is a graphical representation of the experimental results of the I dsat life time as a function of l/Vdd for a device having phosphorous only junctions 1000, a device having arsenic/phosphorous hybrid junctions in accordance with the present invention 1002, and a device having arsenic only junctions 1004.
  • Figure 11 is a graphical representation of the experimental results showing the ring oscillator delay/stage for a device having phosphorous only junctions 1100, a device having arsenic/phosphorous hybrid junctions in accordance with the present invention 1102, and a device having arsenic junctions 1104 with all three devices having an
  • Figure 12 is a graphical representation of the experimental results showing the ring oscillator delay/stage for expected nominal
  • FIG. 13 is a graphical representation of the experimental results of the ring oscillator delay/state for expected subnominal L ef£ for three different junctions; a device having phosphorous only junctions 1300, a device having arsenic/phosphorous hybrid junctions in accordance with the present invention 1302, and a device having arsenic junctions 1304.
  • Figure 14 is a graphical representation of the experimental results showing the comparison of off-state leakage for arsenic/phosphorous hybrid junctions in accordance with the present invention 1400 and for arsenic only junctions 1402. I do££ for nominal devices at 1404 and subnominal devices at 1406 are given. In the case of the subnominal devices, I do££ for the arsenic only junction 1408 is more than 10 times higher than that of the arsenic/phosphorous hybrid junctions 1410 in accordance of the present invention.
  • Figure 15 is a graphical representation of the experimental results of the effect of arsenic/phosphorous junction doping on substrate current.
  • the experimental results indicates that substrate current is a strong function of the light phosphorous dose in the hybrid junction in accordance with the present invention, whereas substrate current is a weak function of arsenic dose in the hybrid junction.
  • Open squares and circles at 1500 compare the effect of tripling arsenic dose.
  • Open squares and closed triangles at 1502 compare the effect of doubling the phosphorous dose. It is anticipated that any appropriate process technology can be adapted for the present invention.
  • One example of a process technology is a technology that uses a p-epi/p+substrate, LOCOS isolation, dual-gate poly, 7 nanometer gate oxide, and DUV lithography to define 0.30 micron Ldrawn poly lines.
  • the implant is driven to obtain the required channel length.
  • Gate poly and S/D regions are doped simultaneously, and RTA (rapid thermal anneal) processes are used for n+ and p+ dopant activation.
  • Self-aligned Ti suicide is formed over the gate and S/D regions.
  • Figure 10 shows the experimental I dsat DC life time for three different junctions.
  • the highest operating voltages for arsenic only devices 1004, the hybrid arsenic/ phosphorous junctions 1002 in the devices of the present invention, and the phosphorous junctions 1000 devices are 2.4, 3.1, and 3.7 V respectively.
  • the inverter delays were compared at a constant L e££ of 0.20 microns.
  • Figure 11 shows that the delay/stage at a given Vdd are approximately the same for all junctions. A slightly higher propagation delay/stage, especially at lower Vdd, found for the arsenic only junction.
  • inverter delay performance is given for different channel lengths. Three different channel lengths were used corresponding approximately to the expected nominal regime of operation for these junctions. At 3.1 volts and an L ef£ of 0.215 microns, the hybrid junction delivers 37 picoseconds delay/stage, as shown by the dotted lines 1206 in Figure 12. For the arsenic only junction, the same gate delay is achieved with a smaller L ef£ of 0.164 microns at only 1.9 volts. The reliability constraint of 10-year life time can still be sustained at this voltage for the arsenic only junction as shown in Figure 10.
  • L ef£ variations due to poly gate lithography, etch, and other process parameters must be considered.
  • a 25 nanometer manufacturing variation in L e££ causes the delay/stage for the hybrid junction is reduced to 31 picoseconds at 3.1 volts for L e££ of 0.19 microns as shown by the dotted lines 1306 in Figure 13.
  • This 31 picoseconds delay can be achieved by the arsenic only junctions at 1.8 volts, as shown in Figure 13, at an L e££ of 0.14 microns.
  • I dsat maximum substrate current
  • I sub decreases significantly when the phosphorous dose is doubled (compare the open squares with the closed triangles in Figure 15)
  • tripling the arsenic doses increases I sub only marginally (compare open squares with open circles in Figure 15) .
  • the light phosphorous dose in the hybrid junctions helps in grading the nLDD junction profile, thereby reducing -lithe peak electric field at this junction. No degradation of the universal I do££ -I dsat characteristics is found when the phosphorous dose in hybrid junctions is doubled.
  • Increasing the arsenic or phosphorous dose in the hybrid junction decreased the inverter propagation delay.
  • Vdd from 2.9 to 3.1 volts
  • the inverter gate delay was reduced from 32 to 31 picoseconds for an L e£f of 0.19 microns.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un procédé destiné à la fabrication d'un dispositif semi-conducteur, dans lequel des zones nLDD hybrides sont formées par implantation d'ions arsenic et d'ions phosphore dans des zones de source et de drain d'un substrat. Les zones de source et de drain sont formées par implantation d'ions arsenic ou phosphore.
EP98904623A 1997-01-21 1998-01-21 JONCTION A ZONES nLDD HYBRIDES As/P AVEC FONCTIONNEMENT A TENSION D'ALIMENTATION MOYENNE POUR MICROPROCESSEURS A GRANDE VITESSE Withdrawn EP0966762A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US78682197A 1997-01-21 1997-01-21
US786821 1997-01-21
PCT/US1998/001153 WO1998032176A1 (fr) 1997-01-21 1998-01-21 JONCTION A ZONES nLDD HYBRIDES As/P AVEC FONCTIONNEMENT A TENSION D'ALIMENTATION MOYENNE POUR MICROPROCESSEURS A GRANDE VITESSE

Publications (1)

Publication Number Publication Date
EP0966762A1 true EP0966762A1 (fr) 1999-12-29

Family

ID=25139679

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98904623A Withdrawn EP0966762A1 (fr) 1997-01-21 1998-01-21 JONCTION A ZONES nLDD HYBRIDES As/P AVEC FONCTIONNEMENT A TENSION D'ALIMENTATION MOYENNE POUR MICROPROCESSEURS A GRANDE VITESSE

Country Status (2)

Country Link
EP (1) EP0966762A1 (fr)
WO (1) WO1998032176A1 (fr)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0187016B1 (fr) * 1984-12-27 1991-02-20 Kabushiki Kaisha Toshiba Transistor à effet de champ métal isolateur-semi-conducteur à drain faiblement dopé et procédé pour sa fabrication
JPS61216364A (ja) * 1985-03-20 1986-09-26 Fujitsu Ltd 半導体装置
JPS61234077A (ja) * 1985-04-10 1986-10-18 Oki Electric Ind Co Ltd Ｍｉｓ型電界効果トランジスタ
JPH04206933A (ja) * 1990-11-30 1992-07-28 Nec Corp 半導体装置
US5097301A (en) * 1990-12-19 1992-03-17 Intel Corporation Composite inverse T-gate metal oxide semiconductor device and method of fabrication
JPH04269836A (ja) * 1991-02-25 1992-09-25 Sony Corp ｎチャンネルＭＩＳ半導体装置
JPH05109762A (ja) * 1991-05-16 1993-04-30 Internatl Business Mach Corp <Ibm> 半導体装置及びその製造方法
US5268317A (en) * 1991-11-12 1993-12-07 Siemens Aktiengesellschaft Method of forming shallow junctions in field effect transistors
JPH05267338A (ja) * 1992-03-19 1993-10-15 Olympus Optical Co Ltd 半導体装置の製造方法
US5376566A (en) * 1993-11-12 1994-12-27 Micron Semiconductor, Inc. N-channel field effect transistor having an oblique arsenic implant for lowered series resistance

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9832176A1 *

Also Published As

Publication number Publication date
WO1998032176A1 (fr) 1998-07-23

Similar Documents

Publication Publication Date Title
US7064399B2 (en) Advanced CMOS using super steep retrograde wells
US7180136B2 (en) Biased, triple-well fully depleted SOI structure
US7192816B2 (en) Self-aligned body tie for a partially depleted SOI device structure
US5952693A (en) CMOS semiconductor device comprising graded junctions with reduced junction capacitance
US7304353B2 (en) Formation of standard voltage threshold and low voltage threshold MOSFET devices
JP4470011B2 (ja) ゲート電極を備えたトランジスタを有するデバイス及びその形成方法
US9142564B2 (en) Pseudo butted junction structure for back plane connection
US6291302B1 (en) Selective laser anneal process using highly reflective aluminum mask
EP1191577A1 (fr) Transistor à effet de champs
KR20110119768A (ko) 축소된 게이트 전극 피치를 가지는 비대칭 트랜지스터를 위한 경사 우물 주입
WO2001037333A1 (fr) Procede de fabrication de mosfets a canal n et canal p a double tension de seuil avec une seule operation d&#39;implant masque supplementaire
EP1026738A2 (fr) Procédé de fabrication utilisant un nombre de masques réduits pour un circuit CMOS à tension multiple comprenant des transistors et des transistors I/O à haute performance et haute fiabilité
KR100391959B1 (ko) 반도체 장치 및 제조 방법
US5844276A (en) CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof
US6040222A (en) Method for fabricating an electrostatistic discharge protection device to protect an integrated circuit
US6333244B1 (en) CMOS fabrication process with differential rapid thermal anneal scheme
US6114210A (en) Method of forming semiconductor device comprising a drain region with a graded N-LDD junction with increased HCI lifetime
US6677208B2 (en) Transistor with bottomwall/sidewall junction capacitance reduction region and method
EP1036409A2 (fr) Procede de fabrication d&#39;un dispositif a semi-conducteur pourvu d&#39;un transistor mos
KR100281397B1 (ko) 초박형 ｓｏｉ 정전기방전 보호 소자의 형성 방법
KR19990078277A (ko) 유기 게이트 측벽 스페이서
EP0966762A1 (fr) JONCTION A ZONES nLDD HYBRIDES As/P AVEC FONCTIONNEMENT A TENSION D&#39;ALIMENTATION MOYENNE POUR MICROPROCESSEURS A GRANDE VITESSE
US6638832B2 (en) Elimination of narrow device width effects in complementary metal oxide semiconductor (CMOS) devices
KR100233707B1 (ko) 듀얼 게이트 씨모오스 트랜지스터의 제조방법
US6872628B2 (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19990805

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB NL

RIN1 Information on inventor provided before grant (corrected)

Inventor name: HAO, MING-YIN

Inventor name: RAKKHIT, RAJAT

Inventor name: NAYAK, DEEPAK, KUMAR

17Q First examination report despatched

Effective date: 20010626

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20030321