EP0958606A1 - Bosse de contact en etain ou en alliage de soudage pour microcircuits non encapsules, et procede de realisation d'une telle bosse - Google Patents

Bosse de contact en etain ou en alliage de soudage pour microcircuits non encapsules, et procede de realisation d'une telle bosse

Info

Publication number
EP0958606A1
EP0958606A1 EP97924046A EP97924046A EP0958606A1 EP 0958606 A1 EP0958606 A1 EP 0958606A1 EP 97924046 A EP97924046 A EP 97924046A EP 97924046 A EP97924046 A EP 97924046A EP 0958606 A1 EP0958606 A1 EP 0958606A1
Authority
EP
European Patent Office
Prior art keywords
layer
tiw
solder
contact bump
bump structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97924046A
Other languages
German (de)
English (en)
Inventor
Jorma Kivilahti
Petteri Palm
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elcoteq Network Oy
Original Assignee
Elcoteq Network Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elcoteq Network Oy filed Critical Elcoteq Network Oy
Publication of EP0958606A1 publication Critical patent/EP0958606A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Definitions

  • the invention relates to a solder or tin contact bump structure according to the preamble of claim 1 for unencapsulated microcircuits.
  • the invention also relates to a process for producing the solder bump structure.
  • One interesting bonding method is the so called flip-chip method which comprises bonding a microcircuit directly to its mounting substrate in exposed, unencapsulated form.
  • the method is based on depositing a solder contact bump on the aluminium contact areas of the microcircuit and then melting the bump to bond the circuit to its substrate.
  • the benefits of the method include the small size of the bonding footprint and the lightness of the structure. The method has, however, been hampered by the inadequate reliability of the bonding structure.
  • Japanese Patent Specification No. 07321114 discloses a contact bump structure where a titanium-tungsten layer is first formed on the contact substrate followed by a gold layer formed in two steps, whereafter a nickel layer is formed. The actual tin contact bump is deposited on this multilayer structure. The deposition of the gold layer in two steps complicates the process, and the titanium-tungsten thin film is, in the manner described, left with weaker diffusion-barrier properties, thus impairing the reliability of the structure.
  • the present invention aims at eliminating the drawbacks of the above-described techniques and at obtaining an entirely novel type of solder contact bump structure for unencapsulated microcircuits.
  • the invention is achieved by forming the gold layer of the contact bump structure in one step only, and by processing the titanium-tungsten thin film in a nitrogen- argon environment and subjecting it to oxygen treatment. More specifically, the solder or tin contact bump structure is characterized by what is stated in the characterizing part of claim 1.
  • the invention provides considerable benefits.
  • the compatible metal layers have improved the reliability of the structure.
  • the TiW thin film has good adhesion to aluminium and offers good diffusion-barrier properties.
  • an Au thin-film layer has been used as the adhesion-fo ⁇ ning film in combination with a gold bump.
  • electrolytically deposited nickel provides good adhesion to a gold layer. Having both an exceptionally low stable and metastable solubility in most tin-based alloys when these are in their molten state, nickel is most suitable for use as an adhesion layer for tin-based solders. Primarily for this reason, nickel has a clearly lower rate of dissolution in a eutectic Sn37Pb solder than, e.g., copper which is conventionally used as an adhesion layer in solder bump structures. Particularly for this reason nickel forms clearly thinner intermetallic compound layers than copper. What is more, the oxidation and nitrogen treatment of the titanium-tungsten essentially improve the diffusion barrier properties of the titanium-tungsten layer.
  • Fig. 1 is a longitudinally sectioned side view of the UMB structure in a solder bump made using conventional techniques.
  • Fig. 2 is a graph of the dissolution rate of different metals into eutectic Sn37Pb solder as a function of temperature (ref. Klean Wassink, Soldering in Electronics, 2nd
  • Fig. 3 is a longitudinally sectioned side view of a contact bump structure according to the invention.
  • Fig. 4 is a detail of the structure shown in Fig. 3.
  • Figure 5 is a more detailed view of the structure shown in Fig. 3.
  • Figures 6a to 6c are longitudinally sectioned side views of alternative contact bump geometries according to the invention.
  • FIGS 7a to 7i are process steps of the process according to the invention.
  • both the TAB and flip-chip techniques conventionally used for bonding components are based on depositing contact bumps 6 typically having a height of 10 to 100 ⁇ m on the electric bonding pad areas 3 of a microcircuit 15, after which the microcircuit 15 itself is bonded on a desired bonding substrate (e.g., a TAB film, FR4, or a so called flexible substrate).
  • a desired bonding substrate e.g., a TAB film, FR4, or a so called flexible substrate.
  • a required number of different thin metal or metal alloy layers must be processed between the bump 6 and the electric contact pad area 3.
  • the structure formed by these metallization layers is generally termed UBM (Under Bump Metallurgy) or BLM (Ball Limiting Metallurgy) and serves to improve adhesion and retard or even prevent diffusion therethrough.
  • UBM Under Bump Metallurgy
  • BLM Bit Limiting Metallurgy
  • the metal layers may be two or more in number, with a typical thickness of 0.1 to 5 ⁇ m.
  • UBM structure is formed from TiW and Au thin-film layers.
  • the most widely known UBM structure is the Cr-Cu-Au used by IBM Corp.
  • each of the layers serves for the above-mentioned purposes to improve the reliability of the structure.
  • the metals used and their layer thicknesses must be selected such that they will also meet the basic metallurgic requirements. Furthermore, they need to retain their properties under normal operating and processing conditions and temperatures, meaning that the structure must not exhibit any undesirable reactions or changes in its properties.
  • the purpose of the first intermediate metal layer 11 is to provide good adherence to the silicon- alloyed contact pad area 3 of aluirjinium. When required, it also functions as a diffusion barrier layer serving to prevent intermetallic reactions between the aluminium 3 and other metals in the structure. Furthermore, the layer acts to protect the contact pad areas 3 of the microcircuit 15 against possible corrosion.
  • the purpose of the second intermediate metal layer 10 is to provide good adhesion between the adherence layer 9 of the bump 6 and the metallized contact pad area 3.
  • the adherence layer 9 of the contact bump 6 forms the actual base layer for the solder bump 6 itself.
  • the adherence layer 9 must be metallurgically compatible with the solder used.
  • Fig. 2 shows the dissolution rate of metals commonly used in electronics into eutectic Sn37Pb solder as a function of temperature.
  • the structure according to the invention is selected such that all metallizations are metallurgically more compatible with each other than those used in the prior art, and what is more, the layer structure obtained is stable and easy to manufacture.
  • the substrate of the microcircuit 15 is formed by alu ⁇ iinium contact pad areas 3 on the surface of a substrate wafer 1 and a passivation layer 2 which partly covers the contact pad areas and which entirely covers the wafer 1.
  • the tJam-film layer 7 is formed on the surface of the contact pad area 3 of the microcircuit 15 from a thin film 7 of TiW (10/90) alloy sputtered in the presence of oxygen and nitrogen, whereby the alloying ratio is typically 10/90 (Ti/W).
  • the alloying ratio may typically be varied in the range 1/99 - 50/50.
  • the thickness of the thin film 7 is typically approximately 100 to 350 nm, most appropriately about 140 nm.
  • the TiW ⁇ in-film layer 7 acts as an adhesion layer thus providing good adherence to the contact pad area 3 of the microcircuit 15.
  • the layer also acts as a diffusion barrier layer preventing undesirable reactions between the aluminium metallization and the gold layer of the contact bump.
  • Another function of the Au thin-film layer 4 is to protect the TiW thin-film layer 7 against oxidation prior to the electrolytic deposition of the contact bumps.
  • the nickel layer 5 serves as the base metallization layer of the actual contact bump 6.
  • the height of the contact blimp 6 is typically 10 to 100 ⁇ m.
  • the height is typically in the range from 10 to 60 ⁇ m, and correspondingly, for a solder bump it is typically in the range from 20 to 100 ⁇ m
  • the contact bump 6 may be either straight-walled as in Fig. 6b, mushroom-shaped as in
  • the height ratios of the composite metal structures are, e.g., 1: 1:20 (TiW: Au:Ni).
  • the contact bump 6 can be made from different compositions of tin-lead alloys, tin or other electrolytically depositable tin-based solder alloys.
  • the wafers are RF etched at a slightly elevated temperature.
  • the structure then consists of a substrate 1, an insulation layer 20 on the substrate, and a passivation layer 2.
  • the TiW layer 7 is DC sputtered in two parts.
  • the total thickness is typically 1400 ⁇ 10 ⁇ A.
  • the first TiWN (700 A) is sputtered in a N 2 (1 part)/Ar (three parts) atmosphere and the second TiW layer in a pure Ar atmosphere.
  • the total thickness of the layer is controlled periodically.
  • the TiWN/T ⁇ W layer 7 is oxidized in an oxygen chamber in order to improve its diffusion barrier properties. During this treatment, the oxygen is dissolved into the TiWN/TiW structure. Before etching the next layer, the wafers are RF etched.
  • the second intermediate metal layer U (the Au thin film) is RF sputtered into a thickness of 1200 ⁇ 10 ⁇ A in an Ar atmosphere.
  • the thickness of the layer is controlled periodically.
  • the photoresist of Fig. 7d is made by conventional methods using a thick photoresist layer 21.
  • the thickness is typically 23 mm
  • the pre-light exposure baking is carried out on the line at a temperature of about 100 °C.
  • the mask is aligned and the exposure is carried out by means of commercially available apparatuses.
  • the wafers are exposed to UV light.
  • the exposed areas are dissolved by means of a developing phase carried out either by the spray or the immersion method.
  • the thickness of the photoresist is measured and registered.
  • the after-baking of the wafers takes place in the oven.
  • the exposed areas are purified by oxygen plasma just before the electrolytic deposition of the bumps.
  • an Ni layer 5 is electrolytically deposited into the openings in the photoresist
  • the nickel bath is periodically monitored and the deposition parameters are registered.
  • a tin solder bump 6 is electrolytically deposited onto the thin nickel bump 5. Even this bath is monitored and the parameters are registered.
  • the photoresist is removed using wet chemistry, and rinsed with ion-exchanged (DI) water.
  • DI ion-exchanged
  • the removal of the photoresist is checked on one wafer.
  • the height of the bumps is measured by means of a Profilometer at five points on a wafer, and at least two wafers in one production lot are subjected to such measurement.
  • the Au layer is removed by wet etching from the areas outside the contact bumps. The etching times are registered and the wafers are rinsed and examined.
  • the wafers are reflow heat treated in glycerol at a temperature of 210 °C in order to obtain the final shape and structure of the tin bumps 6. After this treatment the wafers are rinsed and the end result is examined.

Abstract

L'invention concerne une bosse de contact en étain ou en brasure et un procédé de réalisation d'une telle bosse pour des microcircuits (15) non encapsulés. Ces derniers comprennent un substrat (15), des zones (3) formant plages de contact en aluminium, formées sur ce substrat, une structure de métal composite formée sur les zones (3) formant plages de contact, constituée d'une couche de TiW (7), d'une couche d'Au (4) formée sur cette dernière et d'une couche de Ni (5) formée sur la couche d'Au et enfin une bosse de contact en brasure (6) formée sur la structure de métal composite (7, 4, 5). Selon l'invention, la couche de TiW (7) est pulvérisée par voie cathodique en présence d'azote et d'argon lors de la formation des couches. Ensuite, un traitement par oxygène est effectué, et la couche d'Au (4) est formée par un procédé de dépôt uniquement.
EP97924046A 1996-05-31 1997-05-30 Bosse de contact en etain ou en alliage de soudage pour microcircuits non encapsules, et procede de realisation d'une telle bosse Withdrawn EP0958606A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FI962277 1996-05-31
FI962277A FI962277A0 (fi) 1996-05-31 1996-05-31 Loed- eller tennknoelstruktur foer oinkapslade mikrokretsar
PCT/FI1997/000331 WO1997045871A1 (fr) 1996-05-31 1997-05-30 Bosse de contact en etain ou en alliage de soudage pour microcircuits non encapsules, et procede de realisation d'une telle bosse

Publications (1)

Publication Number Publication Date
EP0958606A1 true EP0958606A1 (fr) 1999-11-24

Family

ID=8546126

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97924046A Withdrawn EP0958606A1 (fr) 1996-05-31 1997-05-30 Bosse de contact en etain ou en alliage de soudage pour microcircuits non encapsules, et procede de realisation d'une telle bosse

Country Status (5)

Country Link
EP (1) EP0958606A1 (fr)
JP (1) JP2000511001A (fr)
AU (1) AU2964297A (fr)
FI (1) FI962277A0 (fr)
WO (1) WO1997045871A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2799578B1 (fr) 1999-10-08 2003-07-18 St Microelectronics Sa Procede de realisation de connexions electriques sur un boitier semi-conducteur et boitier semi-conducteur
US6413851B1 (en) * 2001-06-12 2002-07-02 Advanced Interconnect Technology, Ltd. Method of fabrication of barrier cap for under bump metal
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4782380A (en) * 1987-01-22 1988-11-01 Advanced Micro Devices, Inc. Multilayer interconnection for integrated circuit structure having two or more conductive metal layers
US4880708A (en) * 1988-07-05 1989-11-14 Motorola, Inc. Metallization scheme providing adhesion and barrier properties
JPH07321114A (ja) * 1994-05-23 1995-12-08 Sharp Corp 半導体装置のハンダバンプ形成の方法および構造
US5587336A (en) * 1994-12-09 1996-12-24 Vlsi Technology Bump formation on yielded semiconductor dies

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9745871A1 *

Also Published As

Publication number Publication date
WO1997045871A1 (fr) 1997-12-04
FI962277A0 (fi) 1996-05-31
JP2000511001A (ja) 2000-08-22
AU2964297A (en) 1998-01-05

Similar Documents

Publication Publication Date Title
US6251501B1 (en) Surface mount circuit device and solder bumping method therefor
US6281106B1 (en) Method of solder bumping a circuit component
US6501185B1 (en) Barrier cap for under bump metal
JP2842692B2 (ja) はんだバンプの製造方法および相互接続システム
EP2405469B1 (fr) Procédé pour la formation de dépôts d'alliage de soudure sur des substrats
US5767010A (en) Solder bump fabrication methods and structure including a titanium barrier layer
US6638847B1 (en) Method of forming lead-free bump interconnections
US6111321A (en) Ball limiting metalization process for interconnection
US6015505A (en) Process improvements for titanium-tungsten etching in the presence of electroplated C4's
US7098126B2 (en) Formation of electroplate solder on an organic circuit board for flip chip joints and board to board solder joints
KR100482721B1 (ko) 배선 기판 및 그 제조 방법, 반도체 장치 및 그 제조방법, 및 전자 기기
US6375062B1 (en) Surface bumping method and structure formed thereby
KR20010068233A (ko) 유비엠 언더컷을 개선한 솔더 범프의 형성 방법
US20020086520A1 (en) Semiconductor device having bump electrode
JPH0145976B2 (fr)
US8164188B2 (en) Methods of forming solder connections and structure thereof
WO1997045871A1 (fr) Bosse de contact en etain ou en alliage de soudage pour microcircuits non encapsules, et procede de realisation d'une telle bosse
US20080119056A1 (en) Method for improved copper layer etching of wafers with c4 connection structures
JP3362573B2 (ja) バリアメタルの形成方法
EP1322146A1 (fr) Méthode de dépôt électrolytique de bosses de soudure sur une carte de circuits imprimés organique
KR20020060307A (ko) 솔더 범프의 형성 방법
WO2002027790A1 (fr) Couches barriere pour joints de soudure
KR100597994B1 (ko) 반도체 패키지의 솔더 범프 및 그 제조 방법
WO1997028562A1 (fr) Structure de bosse de contact et procede pour la fabriquer
JPH08172096A (ja) 突起電極の形成方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19981125

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE DK FI FR GB IE IT NL SE

17Q First examination report despatched

Effective date: 20031113

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20040324