KR100597994B1 - 반도체 패키지의 솔더 범프 및 그 제조 방법 - Google Patents
반도체 패키지의 솔더 범프 및 그 제조 방법 Download PDFInfo
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- KR100597994B1 KR100597994B1 KR1020050007762A KR20050007762A KR100597994B1 KR 100597994 B1 KR100597994 B1 KR 100597994B1 KR 1020050007762 A KR1020050007762 A KR 1020050007762A KR 20050007762 A KR20050007762 A KR 20050007762A KR 100597994 B1 KR100597994 B1 KR 100597994B1
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- South Korea
- Prior art keywords
- solder
- metal
- base layer
- metal base
- solder bump
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
- H01L2224/1152—Self-assembly, e.g. self-agglomeration of the bump material in a fluid
- H01L2224/11526—Self-assembly, e.g. self-agglomeration of the bump material in a fluid involving the material of the bonding area, e.g. bonding pad or under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (7)
- 반도체 칩의 표면에 금속패드와;상기 금속 패드에서 중앙 혹은 칩 외부로 배선을 형성한 재배치 배선과;재배치 배선 위에 선택적으로 오픈된 절연막과; 상기 절연막의 선택적으로 오픈된 영역에 금속기저층으로 형성된 솔더 터미널과; 상기 터미널 상에 형성된 솔더로 구성되며,상기 솔더 터미널은 상기 솔더, 금속기저층 및 재배치 배선 간의 반응에 의하여 금속간 화합물이 형성되어 있는 것을 특징으로 하는반도체 패키지의 솔더 범프.
- 제1항에 있어서, 상기 금속기저층은 단층인 것을 특징으로 하는 솔더 범프.
- 제2항에 있어서, 금속 기저층은 Cu, Au ,Fe, Al, Ni 및 이들의 합금 중에서 선택되는 어느 하나의 물질로 형성된 것을 특징으로 하는 솔더 범프.
- 제2항에 있어서, 상기 금속기저층의 두께는 0.0001 ~ 1 ㎛인 것을 특징으로 하는 솔더 범프.
- 제1항에 있어서, 상기 재배치 배선의 두께는 0.001 ~ 200 ㎛인 것을 특징으 로 하는 솔더 범프.
- 제1항에 있어서, 상기 솔더는 Sn, Pb, Ag, Ni, Cu, V, Fe, In 및 이들의 합금중에서 선택되는 어느 하나의 물질로 형성된 것을 특징으로 하는 솔더 범프.
- 보호막에 의해 선택적으로 노출되는 적어도 하나의 전극패드가 형성된 반도체 칩상에 금속 배선을 칩 중앙 혹은 칩 외각으로 재배치하는 공정과;상기 금속 배선의 상부에 보호막을 도포하고 선택적으로 노출하는 공정과;상기 반도체 칩 전면에 금속 박막을 증착하는 공정과;상기 금속 박막에 감광성 포토레지스트를 도포하고 선택적으로 노출하는 공정과;상기 감광성 포토레지스트가 현상되어 노출되는 금속 박막 상에 솔더 범프를 형성하는 공정과;상기 감광성 포토 레지스트를 제거하는 공정과;상기 금속 박막층을 선택적으로 에칭하는 공정과;상기 솔더 범프를 열을 가하여 구형의 범프를 형성하면서, 이와 동시에 상기 솔더 범프와 금속 박막 및 금속 재배선 간에 금속간 화합물을 형성하는 공정을 포함하여 구성되는 솔더 범프 제조방법.
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KR1020050007762A KR100597994B1 (ko) | 2005-01-27 | 2005-01-27 | 반도체 패키지의 솔더 범프 및 그 제조 방법 |
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KR1020050007762A KR100597994B1 (ko) | 2005-01-27 | 2005-01-27 | 반도체 패키지의 솔더 범프 및 그 제조 방법 |
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KR100597994B1 true KR100597994B1 (ko) | 2006-07-10 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5317801A (en) | 1990-04-23 | 1994-06-07 | Nippon Mektron, Ltd. | Method of manufacture of multilayer circuit board |
US6204074B1 (en) | 1995-01-09 | 2001-03-20 | International Business Machines Corporation | Chip design process for wire bond and flip-chip package |
US6630736B1 (en) | 2000-07-27 | 2003-10-07 | National Semiconductor Corporation | Light barrier for light sensitive semiconductor devices |
US6756294B1 (en) | 2002-01-30 | 2004-06-29 | Taiwan Semiconductor Manufacturing Company | Method for improving bump reliability for flip chip devices |
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- 2005-01-27 KR KR1020050007762A patent/KR100597994B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5317801A (en) | 1990-04-23 | 1994-06-07 | Nippon Mektron, Ltd. | Method of manufacture of multilayer circuit board |
US6204074B1 (en) | 1995-01-09 | 2001-03-20 | International Business Machines Corporation | Chip design process for wire bond and flip-chip package |
US6630736B1 (en) | 2000-07-27 | 2003-10-07 | National Semiconductor Corporation | Light barrier for light sensitive semiconductor devices |
US6756294B1 (en) | 2002-01-30 | 2004-06-29 | Taiwan Semiconductor Manufacturing Company | Method for improving bump reliability for flip chip devices |
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