EP0948132B1 - Verstärker mit programmierbarer Verstärkungs- und Eingangslinearität für Hochfrequenzleitungen - Google Patents

Verstärker mit programmierbarer Verstärkungs- und Eingangslinearität für Hochfrequenzleitungen Download PDF

Info

Publication number
EP0948132B1
EP0948132B1 EP98830192A EP98830192A EP0948132B1 EP 0948132 B1 EP0948132 B1 EP 0948132B1 EP 98830192 A EP98830192 A EP 98830192A EP 98830192 A EP98830192 A EP 98830192A EP 0948132 B1 EP0948132 B1 EP 0948132B1
Authority
EP
European Patent Office
Prior art keywords
stage
amplifier
current
gain
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP98830192A
Other languages
English (en)
French (fr)
Other versions
EP0948132A1 (de
Inventor
Stefano Marchese
Valerio Pisati
Salvatore Portaluri
Alessandro Savo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, SGS Thomson Microelectronics SRL filed Critical STMicroelectronics SRL
Priority to DE69824143T priority Critical patent/DE69824143D1/de
Priority to EP98830192A priority patent/EP0948132B1/de
Priority to US09/264,296 priority patent/US6037838A/en
Publication of EP0948132A1 publication Critical patent/EP0948132A1/de
Application granted granted Critical
Publication of EP0948132B1 publication Critical patent/EP0948132B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G7/00—Volume compression or expansion in amplifiers
    • H03G7/06—Volume compression or expansion in amplifiers having semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers

Definitions

  • the present invention relates to an amplifier with programmable gain and input linearity usable in high-frequency lines.
  • a data read channel is an example of a case in which signal processing requires a gain-programmable amplifier.
  • Figure 1 accordingly illustrates four signals A, B, C and D which have different amplitudes and are voltage-added in a node 1 and then amplified in gain means 2 which set the gain, so as to obtain a sum signal which is sent to equalizer means 3 and finally to a buffer 4.
  • the intended result is a dB-linear gain variation with a linear variation of the current.
  • a gain setting circuit of the prior art is shown in Figure 2, in which a differential input stage, designated by the reference numeral 10, is connected to a differential output stage, designated by the reference numeral 11, and in which the gain A v is determined by a resistance ratio multiplied by a current ratio.
  • the resistance ratio is determined by the ratio between the resistances of the output stage with respect to those of the input stage, while the current ratio is the ratio between the current of the output stage and the current of the input stage.
  • the above-described circuit solution is effective as to gain programming, since said gain can be changed not only by varying the resistive ratio (which is difficult to implement and in any case entails large area occupation) but also by mainly varying the current ratio, which can be achieved easily with a modest utilization of the physical area of the device.
  • EP-A-0 369 469 discloses a variable gain amplifier having a wider range wherein a gain can be controlled or varied.
  • Patent Abstracts of Japan vol. 095, no. 008, 29 September 1995 & JP 07 135432 A, 23 May 1995 disclose a variable gain amplifier.
  • the aim of the present invention is to provide an amplifier with programmable gain and input linearity usable in high-frequency lines and which allows to increase the gain without altering input linearity and without increasing current consumption excessively.
  • an object of the present invention is to provide an amplifier with programmable gain and input linearity, usable in high-frequency lines, in which the gain of the amplifier is closely correlated to current variation.
  • Another object of the present invention is to provide an amplifier with programmable gain and input linearity, usable in high-frequency lines, having high gain and high gain precision.
  • Another object of the present invention is to provide an amplifier with programmable gain and input linearity, usable in high-frequency lines, which is highly reliable, relatively easy to implement and at competitive costs.
  • the circuit according to the invention comprises a first differential input stage 10 (similar to the differential input stage shown in Figure 2) composed of a first bipolar transistor 15 and of a second bipolar transistor 16, which are arranged so that their emitter terminals are connected to resistors R E and their collector terminals are connected to respective diodes 17 and 18.
  • a current source 2I 1 is connected to the common point between the resistors R E .
  • the first differential input stage (a differential stage is shown in this case, but the circuit according to the invention is equally valid if a single-input stage or a single-output output stage is used) is connected to at least one current amplifier stage, designated by the reference numeral 20, which is interposed between the differential input stage 10 and a differential output stage 30.
  • the current amplifier stage 20 is constituted by a first bipolar transistor 21 and by a second bipolar transistor 22 which have common-connected emitter terminals; a current source 2I 2 is connected thereto.
  • the base terminals of the bipolar transistors 21 and 22 are respectively connected to the collector terminals of the transistors 15 and 16, while voltage signals V + and V - are supplied to the base terminals of the transistors 15 and 16 of the first differential input stage.
  • the collector terminals of the transistors 21 and 22 are connected, respectively, to diodes 23 and 24 in which the anode terminal is connected to the collector terminal of the respective transistor.
  • the second stage i.e., the current amplifier stage 20
  • the output stage which is also of the differential type (the same considerations made earlier apply to this case also) and is constituted by two transistors 31 and 32 in which the emitter terminals are common-connected and whereto a current source 2I 3 is connected.
  • the collector terminals of the transistors 31 and 32 are respectively connected to resistors R L .
  • the base terminals of the bipolar transistors 31 and 32 are respectively connected to the collector terminals of the transistors 21 and 22 of the current amplifier stage 20.
  • the input stage 10 receives in input a pair of voltage signals and converts them into current signals, compressing them; said signals are sent to the second current amplifier stage 20, which amplifies the gain and then sends the signals thus amplified to the differential output stage 30, which converts the current signals back to voltage signals in order to have a voltage output.
  • the transconductance of the diodes 23 and 24 of the second current amplifier stage 20 can be modulated by varying the static current supplied by the sources I 2 *, which is independent of the current of the input stage 10.
  • the current sources I 2 * are therefore means for subtracting static current from the diodes 23 and 24 which thus allow to reduce the transconductances of the diodes 23 and 24.
  • gm1, gm2, gm3 and gm2* are, respectively, the transconductances of the diodes 17 and 18, of the transistors 21 and 22, of the diodes 23 and 24 and of the transistors 31 and 32.
  • I 2 I 2 -I 2 * can be varied continuously or stepwise by changing the current I 2 *.
  • the limit of the above-described structure consists in preventing the term I 2 -I 2 * from becoming smaller than 0: in this case, the load diodes of the second stage 20, i.e., the diodes 23 and 24, switch off and the linear region is abandoned.
  • Figure 4 is a partial circuit diagram in which only one branch of the corresponding differential circuits is illustrated and the second branch is omitted; the diagram describes a circuit in which two current amplifier stages are interposed between the differential input stage 10 and the differential output stage 30; said amplifier stages are now designated by the reference numerals 20' and 20" and are provided according to the invention, like the stage 20 shown in Figure 3.
  • gm4 is the transconductance of the bipolar transistors of the output stage 30, while gm3 and gm3* are, respectively, the transconductances of the bipolar transistors and of the diodes of the second current amplifier stage 20".
  • the secondary poles are due to the impedance of the diodes and to the parasitic capacitors that occur on the respective nodes and are thus localized at high frequencies (this is true if the transconductance of the diodes is kept relatively high).
  • Figure 4 illustrates a capacitor C L representing a load capacitance due to a load which is connected to the amplifier according to the invention.
  • the differential output stage 30 is formed, in this case, by a modified current mirror, as shown in Figure 5, in which an additional bipolar transistor 35 is provided which is connected, by means of its base terminal, to the collector terminal of a transistor 36 which receives, on its emitter terminal, a control current I cont and is connected to the transistor 37 by means of its base terminal.
  • Said common-mode circuit is an amplifier which has a reference voltage and receives in input the voltages received on the collectors of the transistors 31 and 32 and provides feedback control in output of current sources 45 and 46.
  • the amplifier thus controls the half-sum of the inputs taken from the collectors of the transistors 31 and 32 and compares said half-sum with the reference voltage in order to generate an error signal and control the current sources 45 and 46.
  • the half-sum of the voltages in input to the common-mode circuit 50 must be equal to the reference voltage. In this case, the circuit 50 performs no action on the current sources 45 and 46.
  • the circuit according to the invention achieves low power dissipation and can have a current output, which is useful for applying for example filters etcetera.
  • the materials employed may be any according to requirements and to the state of the art.

Landscapes

  • Amplifiers (AREA)

Claims (5)

  1. Verstärker mit programmierbarer Verstärkungs- und Eingangslinearität, mit:
    einer Eingangsstufe (10), die geeignet ist, ein Spannungssignal (V+, V-) zu empfangen und eine Stromwandlung mit Kompression durchzuführen;
    einer Ausgangsstufe (30), die an die Eingangsstufe (10) angeschlossen und geeignet ist, das Signal im Ausgang von der Eingangsstufe zu dekomprimieren, um deren Verstärkungsfaktor zu erzeugen;
    mindestens einer Stromverstärkerstufe (20), die zwischen der Eingangsstufe (10) und der Ausgangsstufe (30) geschaltet ist und mindestens einen bipolaren Transistor (21, 22) aufweist, der mit einer Lastdiode (23, 24) und einer Stromquelle (2I2) in Reihe geschaltet ist;
    Programmiermittel (I2, I2*) zur Reduktion des Gegenwirkleitwertes der Lastdiode (23, 24), welche in mindestens einer Verstärkerstufe (20) vorgesehen ist, um einen programmierbaren Verstärkungsfaktor für die Verstärkung des Verstärkers zu ermitteln, wobei die programmierbaren Mittel eine statische Stromquelle aufweisen, die zur Lastdiode parallel geschaltet ist;
       wobei in mindestens einer Stromverstärkerstufe, die zwischen der Eingangsstufe und der Ausgangsstufe zwischengeschaltet ist, die statische Stromquelle zusammen mit der Stromquelle einen Verstärkungsfaktor für die Verstärkung des Verstärkers erzeugt, der durch Veränderung des Wertes der statischen Stromquelle programmiert werden kann.
  2. Verstärker nach Anspruch 1,
    dadurch gekennzeichnet, dass die Eingangsstufe (10), die Ausgangsstufe (30) und die mindestens eine Stromverstärkerstufe (20) Differentialstufen sind.
  3. Verstärker nach Anspruch 2,
    dadurch gekennzeichnet, dass die Differentialausgangsstufe (30) an eine Common-Mode-Rückkoppelungsschaltung (50) angeschlossen ist, die an ihrem Eingang die Differentialspannungssignale vom Ausgang der Ausgangsstufe (30) empfängt und diese mit einer Referenzspannung vergleicht, um ein Signal zu erzeugen, um ein Paar von Stromquellen zu treiben, die jeweils zu Lastwiderständen der Ausgangsstufe parallel geschaltet sind.
  4. Verstärker nach Anspruch 3,
    dadurch gekennzeichnet, dass die Differentialeingangsstufe (10) zwei Transistoren (15, 16) aufweist, die in einer Spiegelbildanordnung verschaltet sind, und wobei entsprechende Lastdioden (17, 18) an die Kollektoranschlüsse angeschlossen sind, wobei die Kollektoranschlüsse an die Basisanschlüsse eines Paares von Transistoren (21, 22) der mindestens einen Stromverstärkerstufe angeschlossen sind.
  5. Verstärker nach Anspruch 4,
    dadurch gekennzeichnet, dass die Differentialeingangsstufe (10) zwei Widerstände (RE) aufweist, die jeweils an die Emitteranschlüsse des Paares der Transistoren der Differentialeingangsstufe angeschlossen sind.
EP98830192A 1998-03-31 1998-03-31 Verstärker mit programmierbarer Verstärkungs- und Eingangslinearität für Hochfrequenzleitungen Expired - Lifetime EP0948132B1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE69824143T DE69824143D1 (de) 1998-03-31 1998-03-31 Verstärker mit programmierbarer Verstärkungs- und Eingangslinearität für Hochfrequenzleitungen
EP98830192A EP0948132B1 (de) 1998-03-31 1998-03-31 Verstärker mit programmierbarer Verstärkungs- und Eingangslinearität für Hochfrequenzleitungen
US09/264,296 US6037838A (en) 1998-03-31 1999-03-08 Amplifier with programmable gain and input linearity usable in high-frequency lines

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP98830192A EP0948132B1 (de) 1998-03-31 1998-03-31 Verstärker mit programmierbarer Verstärkungs- und Eingangslinearität für Hochfrequenzleitungen

Publications (2)

Publication Number Publication Date
EP0948132A1 EP0948132A1 (de) 1999-10-06
EP0948132B1 true EP0948132B1 (de) 2004-05-26

Family

ID=8236600

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98830192A Expired - Lifetime EP0948132B1 (de) 1998-03-31 1998-03-31 Verstärker mit programmierbarer Verstärkungs- und Eingangslinearität für Hochfrequenzleitungen

Country Status (3)

Country Link
US (1) US6037838A (de)
EP (1) EP0948132B1 (de)
DE (1) DE69824143D1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10064207A1 (de) * 2000-12-22 2002-07-11 Infineon Technologies Ag Schaltungsanordnung zur rauscharmen volldifferenziellen Verstärkung
US6429690B1 (en) 2001-11-02 2002-08-06 International Business Machines Corporation Programmable linear transconductor circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3972010A (en) * 1968-01-10 1976-07-27 Ray Milton Dolby Compressors, expanders and noise reduction systems
US3895322A (en) * 1974-03-14 1975-07-15 Gte Automatic Electric Lab Inc Tone controlled compandored system
JPH0666614B2 (ja) * 1988-11-18 1994-08-24 三洋電機株式会社 利得制御増幅回路
JPH07135432A (ja) * 1993-01-14 1995-05-23 Sharp Corp 利得可変増幅器
JP3251759B2 (ja) * 1994-02-24 2002-01-28 株式会社東芝 可変利得増幅回路
US5631968A (en) * 1995-06-06 1997-05-20 Analog Devices, Inc. Signal conditioning circuit for compressing audio signals
US5589791A (en) * 1995-06-09 1996-12-31 Analog Devices, Inc. Variable gain mixer having improved linearity and lower switching noise

Also Published As

Publication number Publication date
US6037838A (en) 2000-03-14
EP0948132A1 (de) 1999-10-06
DE69824143D1 (de) 2004-07-01

Similar Documents

Publication Publication Date Title
US6060935A (en) Continuous time capacitor-tuner integrator
US6373337B1 (en) Differential amplifier
KR100946815B1 (ko) 프로그램 가능한 저잡음 증폭기 및 방법
US5872475A (en) Variable attenuator
US7400195B2 (en) Variable-gain differential amplifier
US20010019288A1 (en) Variable resistance circuit, operational amplification curcuit, semiconductor integrated circuit, time constant switching circuit and waveform shaping circuit
CA1192275A (en) Circuit for amplifying and/or attenuating a signal
EP1030442B1 (de) Mehrstufiger Verstärker mit variabler Verstärkung, grosser Bandbreite und reduzierten Phasenvariationen
JP2003516082A (ja) 増幅器
JP2007053794A (ja) 制御可能なフィルタ装置
US6034568A (en) Broadband dc amplifier technique with very low offset voltage
US5495201A (en) Transconductor stage
US6972624B1 (en) Low-voltage high dynamic range variable-gain amplifier
US6400933B1 (en) Amplifier
EP0948132B1 (de) Verstärker mit programmierbarer Verstärkungs- und Eingangslinearität für Hochfrequenzleitungen
GB2436651A (en) Variable gain low noise amplifier
US7138867B2 (en) Balanced variable gain amplifier capable of achieving performance by low source voltage
US6078218A (en) Negative amplifier circuit
JP2000134046A (ja) 電流増幅器
RU2310268C1 (ru) Каскодный дифференциальный усилитель с низковольтным питанием
US6278299B1 (en) Voltage to current converter
US6693492B2 (en) Variable gain low-noise amplifier and method
RU2053592C1 (ru) Усилитель
US5166983A (en) Mute circuit for audio amplifiers
JP3388196B2 (ja) 利得制御回路

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

RIN1 Information on inventor provided before grant (corrected)

Inventor name: SAVO, ALESSANDRO

Inventor name: PORTALURI, SALVATORE

Inventor name: PISATI, VALERIO

Inventor name: MARCHESE, STEFANO

17P Request for examination filed

Effective date: 20000329

AKX Designation fees paid

Free format text: DE FR GB IT

17Q First examination report despatched

Effective date: 20021218

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20040526

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 69824143

Country of ref document: DE

Date of ref document: 20040701

Kind code of ref document: P

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20040827

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20050301

EN Fr: translation not filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20060331

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20070226

Year of fee payment: 10

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20080331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20070331