GB2436651A

GB2436651A - Variable gain low noise amplifier

Info

Publication number: GB2436651A
Application number: GB0606421A
Authority: GB
Inventors: David Lomas; Stephan Ahles
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2006-03-30
Filing date: 2006-03-30
Publication date: 2007-10-03
Anticipated expiration: 2026-03-30
Also published as: GB0606421D0; GB2436651B

Abstract

A commonly used variable gain low noise amplifier (lna) works as a simple cascaded differential pair. In this invention the second cascade output is crossed over to the output node of opposite polarity rather than connected to the supply. The cascade voltages cancel each other out and this can be used to further control the amplifier performance. An additional variable tail current source may be used to add dc tail current for lower gain modes. This increases the IP1dB by decreasing the modulation depth in the input transistor pairs. Attenuation and gain ranging from -10dB to +20dB can be achieved.

Description

Variable Gain Low Noise Amplifier The present invention relates to

amplifiers and particularly to variable gain low noise amplifiers (LNAs).

For many applications it is sufficient to use an LNA with fixed gain, which is optimised either for large input signal level or low noise operation, or is often a compromise between the two requirements. However, if the possible range of input signal powers varies beyond that which can be handled by a fixed gain LNA, it then becomes necessary to employ an LNA with variable gain which can handle both weak input signals and attenuate large ones.

While the ability to handle a weak signal is generally limited by the noise an amplifier creates (which is expressed by the Noise Figure, NF), the handling of large signals is limited by the amplifiers' large-signal linearity expressed by the input-referred third order intercept point 11P3 and the input-referred 1 -dB-gain-compression point (IPIdB). The relative levels of 11P3 and IP1dB required are also heavily dependent upon the modulation scheme used. Therefore, an amplifier which handles large as well as small signals, needs to have a large IPldB point as well as low NF and as a consequence needs to have variable gain. A circuit topology that satisfies these requirements is proposed here.

The circuit commonly used for variably-gain LNAs is current steering, as shown in Figure 1. Most published work is based on this approach (see [1] and [2J as

examples).

The circuit of Figure 1 can generally be considered as having an amplification stage generally indicated by reference numeral 10, control stage 11 and output stage 12.

The amplification stage 10 comprises a pair of transistors 20,21 connected to respective inductors 22,23 which in turn are connected to a current source 25. A differential input signal IN+IN-is supplied to the gates of transistor pair 20,21. The output nodes 26,27 of the amplification stage 10 taken from respective transistors 20,21 are connected to respective transistor pairs of the control stage to be described in more detail below.

The control stage consists of transistor pairs 28,29 and 30,31. Transistors 28,29 are connected in common to node 26 and transistors 30, 31 are connected in common to node 27. Each transistor pair is supplied with a differential control signal CTRL+, CTRL-. The remaining terminals of transistors 28,31 are connected to supply voltage \TDD. The output signal is taken from the like polarity transistors in each pair, in this case transistors 29,3 0, via load impedance ZL.

The control circuit in this example works as a simple cascoded differential pair. The highest gain achievable with this architecture is A=IGIIIZLI where Gm is the effective transconductance of the degenerated input transistors. Gain variation is achieved by steering the DC and AC current away from the load ZL, which reduces the gain.

The circuit of Figure 1 is shown using MOS transistors but the architecture is also commonly used with bipolar transistors.

The problem with the circuit of Figure 1 is that the cascode devices can become current starved to such an extent that they no longer work in the active region, resulting in low IP 1dB points or low gains. As mentioned earlier in order to achieve a large dynamic range it is actually important to have a high IPl dB point in low gain mode. Therefore, this architecture is only suitable for input signals with limited dynamic range.

The present invention provides a variable gain amplifier having an amplifier stage and a control stage, wherein: the control stage comprises two pairs of transistors connected in parallel to each of which a differential control signal is applied, each pair having a common input node and two output nodes; the amplification stage receives a differential input signal and supplies a differential signal to the input nodes of the transistor pairs; and the output signal is taken from two same polarity nodes of the transistor pairs and each other output node of each transistor pair is connected to the other output node of opposite polarity in the other pair.

In order to arrive at the present invention, the circuit architecture shown in Figure 1 was modified so that gain variation is achieved by current cancellation with AC currents of the opposite phase polarity. This way, no transistor is starved of current.

An additional variable tail current source may be interviewed to add DC tail' current for lower gain modes. This increases the achievable IPIdB by decreasing the modulation depth of the input transistor pairs.

In order that the present invention be more readily understood, an embodiment will now be described by way of example only with reference to the accompanying drawings in which: Figure 1 shows a prior art variable gain LNA, described above; Figure 2 shows a schematic diagram of a variable gain LNA according to an embodiment of the present invention; Figure 3 shows a representation of Figure 2 identifying the currents flowing at various parts of the circuit; Figure 4 shows a detailed view of the digital gain control block shown in Figures 2 and3;and Figure 5 shows a comparison of the simulation results for 11P3 and IP I dB of the circuit shown in Figure 1 and the circuit shown in Figure 2.

Detailed Description

The simplified circuit diagram in Figure 2 shows how the ideas outlined above are applied. Like items in Figures 1 and 2 have like reference numerals.

The basic circuit structure is similar to the one shown in Figure 1. However, the second cascode output is crossed-over to the output node of opposite polarity rather than connected to supply. Thus, the output node of transistor 28 is crossed over to the output node of transistor 30 and the output node of transistor 31 is crossed over to the output node of transistor 29. This means the currents from both cascodes are combined, and converted to an output voltage in the load impedance ZL. Because the relative signal phases are 180 degrees out of phase, the two cascode voltages can cancel each other out.

The amount of cancellation depends on the relative amplitude of the two cascode currents. These amplitudes are set via the voltage on nodes CTRL+ and CTRL-. This means we can achieve gain control by varying the cascode voltages.

Figure 3 explains the concept further. The AC currents i, and i (which are 1 80 degrees out of phase because of the differential nature of the circuit), are split into four currents in the cascode stage: i,+, i1,, i+, i. The currents and n as well as n+ and are combined at the output of the cascodes. Because and i1 as well as n+ and i1 are scaled as shown below, variable current-cancellation is achieved.

A = 0.. 1 (scaling factor) = . A = A -A) i,,_ = jfl(1 -A) The currents flowing into the load impedance ZL can be written as a function of A: i'=i.A+i,, .(1A) i,1.(1A) A is a scaling factor dependant on the voltage between CTRL+ and CTRL-. When the voltage between these nodes is large, the factor A is close to 0, when the voltage is small, the factor A is close to 1. For the purpose of this explanation it is assumed that the relationship between the control voltage and the current scaling of A is a linear one. In reality, of course, this is not the case which means that the relationship between gain-in-dB and the control voltage is not a linear one.

Additionally, a variable tail current source 35 is employed, which is activated at low gains. Its purpose is to decrease the modulation depth of the input transistor pair, thus increasing its linearity.

As the variable tail current needs to be activated only at very low gains, it is preferable to employ a digital gain control 40, the implementation of which is shown Figure 4.

The digital gain control 40 comprises load transistors 41,42 shared between a number of scaled current sources two of which are indicated by numerals 43 and 44. A digital control signal switches an appropriate ones to he current sources to supply current to the transistors. The current sources will have different magnitudes, source 44 produces twice the current of source 43 and so on so that the total current is variable in digital steps. The transistors 41 and 42 are matched to the cascode transistors and their sources and their sources and gates are connected in common to supply voltage VDD.

Finally, simulation results, showing 11P3 and IP1dB of the circuits shown in Figure 1 and Figure 2 are shown in Figure 5. Two issues can be clearly identified with the current steering approach.

1) The 11P3 in dBm should always be higher than the IP1dB of a circuit.

However, the simulation results shown that the two measures cross over near the 0dB mark.

2) It can be clearly seen that the IP I dB and 11P3 fall off at low gains for the current steer method.

The quality of the matching of the cascode transistors with each other determines the amount of attenuation that is possible with this architecture. At the time of writing, gains ranging from -10 dB to +20 dB are easily achievable with this circuit.

Also, the proposed architecture can be implemented with bipolar as well as MOS transistors.

[1] K.W. Kobayashi et. at., "A Monolithically Integrated HEMT-HBT Low Noise High Linearity Variable Gain Amplifier" 1996. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO.5.

[2J Gwilym F. Luff et. a!., "A Compact Triple-Band Eureka-147 RF Tuner with an FM Receiver" 2005. ISSCC 2005, Session 23.

Claims

CLAIMS: 1. A variable gain amplifier having an amplifier stage and a

control stage, wherein: the control stage comprises two pairs of transistors connected in parallel to each of which a differential control signal is applied, each pair having a common input node and two output nodes; the amplification stage receives a differential input signal and supplies a differential signal to the input nodes of the transistor pairs; and the output signal is taken from two same polarity nodes of the transistor pairs and each other output node of each transistor pair is connected to the other output node of opposite polarity in the other pair.

2. An amplifier as claimed in claim 1 in which the amplifier stage includes a degenerated input transistor connected to each transistor pair of the control stage.

3. An amplifier as claimed in claim 1 or 2 including an d.c. current supply connected to the amplifier stage.

4. An amplifier as claimed in claim 3 including means for controlling the d.c.

current supply whereby to control the performance of the amplifier.

5. An amplifier as claimed in claim 4 in which the means for controlling the d.c.

current supply also controls the differential control signal applied to the transistor pairs.

6. A radio frequency receiver having at its r.f front end an amplifier as claimed in any preceding claim. C'

Amendments to the claims have been flied as follows 1. A variable gain amplifier having an amplifier stage and a control stage, wherein: the control stage comprises two pairs of transistors to each of which a differential control signal is applied, each pair having a common input node and two output nodes; the amplification stage receives a differential input signal and supplies a differential signal to the input nodes of the transistor pairs; and the output signal is taken from two same polarity nodes of the transistor pairs and each other output node of each transistor pair is connected to the other output node of opposite polarity in the other pair.

2. An amplifier as claimed in claim 1 in which the amplifier stage includes a degenerated input transistor connected to each transistor pair of the control stage.

3. An amplifier as claimed in claim 1 or 2 including an d.c. current supply connected to the amplifier stage.

4. An amplifier as claimed in claim 3 including means for controlling the d.c.

current supply whereby to control the performance of the amplifier.

5. An amplifier as claimed in claim 4 in which the means for controlling the d.c.

current supply also controls the differential control signal applied to the transistor pairs.

6. A radio frequency receiver having at its r.f front end an amplifier as claimed in any preceding claim.