Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
  • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/53204—Conductive materials
  • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
  • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
  • H01L23/53233—Copper alloys
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/53204—Conductive materials
  • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
  • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
  • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• This invention relates to interconnection wiring on electronic devices such as on integrated circuit (IC) chips and more particularly to void-free and seamless submicron structures fabricated by Cu electroplating from baths that contain additives conventionally used to produce bright, level, low-stress deposits.
• IC integrated circuit
• AlCu and its related alloys are a preferred alloy for forming interconnections on electronic devices such as integrated circuit chips .
• the amount of Cu in AlCu is typically in the range from .3 to 4 percent.
• Copper metallization has been the subject of extensive research as documented by two entire issues of the Materials Research Society (MRS) Bulletin, one dedicated to academic research on this subject in MRS Bulletin, Volume XVIII, No. 6 (June 1993) and the other dedicated to industrial research in MRS Bulletin, Volume XIX, No. 8 (March 1994) .
• MRS Materials Research Society
• a 1993 paper by Luther et al . Planar Copper- Polyimide Back End of the Line Interconnections for ULSI Devices, in PROC. IEEE VLSI MULTILEVEL INTERCONNECTIONS CONF., Santa Clara, CA, June 8-9, 1993, p. 15, describes the fabrication of Cu chip interconnections with four levels of metallization.
• Processes such as Chemical Vapor Deposition (CVD) and electroless plating are popular methods for depositing Cu.
• CVD Chemical Vapor Deposition
• electroless plating are popular methods for depositing Cu.
• a process for fabricating a low cost, highly reliable Cu interconnect structure for wiring in integrated circuit chips with void-free seamless conductors of sub-micron dimensions.
• the process comprises deposition of an insulating material on a wafer, lithographically defining and forming sub-micron trenches or holes in the insulating material into which the conductor will be deposited to ultimately form lines or vias, depositing a thin conductive layer serving as a seed layer or plating base, depositing the conductor by electroplating from a bath containing additives and planarizing or chemical -mechanical polishing the resulting structure to accomplish electrical isolation of individual lines and/or vias.
• the invention further provides a process for fabricating an interconnect structure on an electronic device comprising the steps of forming a seed layer on a substrate having insulating regions and conductive regions, forming a patterned resist layer on the seed layer, electroplating conductor material on the seed layer not covered by the patterned resist from a bath containing additives, and removing the patterned resist .
• the invention further provides a process for fabricating an interconnect structure on an electronic device with void-free seamless conductors comprising the steps of forming an insulating material on a substrate, lithographically defining and forming lines and/or vias in which interconnection conductor material will be deposited, forming a conductive layer serving as a plating base, forming a patterned resist layer on the plating base, depositing the conductor material by electroplating from a bath containing additives, and removing the resist.
• the invention further provides a process for fabricating an interconnect structure on an electronic device comprising the steps of forming a seed layer on a substrate having insulating regions and conductive regions, forming a blanket layer of conductor material on the seed layer from a bath containing additives, forming a patterned resist layer on the blanket layer, removing the conductor material where not covered by the patterned resist, and removing the patterned resist .
• the invention further provides a conductor for use in interconnections on an electronic device comprising Cu including small amounts of a material in the Cu selected from the group consisting of C (less than 2 weight percent) , 0 (less than 1 weight percent) , N (less than 1 weight percent) , S (less than 1 weight percent) , and Cl (less than 1 weight percent) formed by electroplating from a bath containing additives .
• the interconnection material may be Cu electroplated from baths that contain additives conventionally used to produce bright, level, low-stress deposits.
• the rate of Cu electroplating from such baths is higher deep within cavities than elsewhere. This plating process thus exhibits unique superfilling properties and results in void-free seamless deposits that cannot be obtained by any other method.
• Interconnection structures made by Cu electroplated in this manner are highly electromigration-resistant with an activation energy for electromigration equal to or greater than 1.0 eV.
• the conductor is composed substantially of Cu and small amounts of atoms and/or molecular fragments of C (less than 2 weight percent) , O (less than 1 weight percent) , N (less than 1 weight percent) , S (less than 1 weight percent) , and Cl (less than 1 weight percent) .
• Cu which is highly electromigration-resistant is electroplated from plating solutions that contain additives conventionally used to produce bright, ductile, and low-stress plated deposits.
• the depth to width ratio of a conductor may be equal to or greater than 1.
• the depth to width ratio of a via may exceed 1.
• Figures 1-5 are cross-sectional views of intermediate structures illustrating the formation of interconnection wiring.
• Figure 6 shows multi-level wiring patterns formed with one plating step.
• Figure 7 illustrates early stages of deposition with the deposition rate deep within the feature being greater than the deposition rate outside of the features.
• Figure 8 shows late stages of deposition with the deposition rate inside of the features being greater than the deposition rate outside of the features.
• Figure 9 illustrates early stages of deposition with the deposition rate inside of the features being slower than the deposition rate outside of the features.
• Figure 10 shows late stages of deposition with the deposition rate inside of the features being slower than the deposition rate outside of the features.
• Figure 11 illustrates early stages of deposition with the deposition rate being the same inside and outside of the features .
• Figure 12 shows late stages of deposition with the deposition rate being the same inside and outside of the features.
• Figure 13 shows a cross-sectional view of a sequence of plating profiles.
• Figure 14 shows a cross-sectional view of a feature plated electrolytically using a plating bath without additives .
• Figure 15 shows a cross-sectional view of a feature plated electrolytically using a plating bath with additives.
• Figure 16 is a cross-sectional view of a substrate having both submicron and wide cavities to be plated.
• Figure 17 is a cross-sectional view of the substrate of Figure 16 which has been subsequently plated in a wafer immersion-type plating cell.
• Figure 18 is a cross-sectional view of the substrate of Figure 16 which has been subsequently plated in a meniscus-type plating cell (cup plater) where the wafer surface is brought into contact with the upper surface or meniscus of the electrolyte.
• Figures 19 a-d are a grain orientation map, grain contrast map, inverse pole figure and (111) pole figure of the same region for a 1 micron thick plated Cu film.
• the grain size is approximately 1.4 microns and the crystallographic texture is random.
• Figures 20 a-d are a grain orientation map, grain contrast map, inverse pole figure and (111) pole figure of the same region for a 1 micron thick PVD (physical vapor deposition, magnetron sputter deposited) Cu film.
• the grain size is approximately 0.4 microns and this film has a strong (111)/ (100) crystallographic texture.
• Figures 21a and 21b show the change in resistance versus time (hours) for plated Cu versus a) CVD Cu and b) PVC Cu films.
• the change in resistance is related to the amount of electromigration damage in the Cu line.
• Clearly plated Cu has a much improved electromigration behavior than either CVD or PVD Cu.
• the activation energy for plated Cu is 1.1-1.3 eV while that for PVD Cu is considerably less (0.7-0.8 eV) .
• Figures 22-26 are cross-sectional views illustrating through-mask plating on a planar base.
• Figures 27-31 are cross-sectional views illustrating through-mask plating on an excavated base.
• Figures 32-35 are cross-sectional views illustrating blanket plating followed by pattern etching.
• a Damascene plating process is one in which plating is done over the entire wafer surface and is followed by a planarization process that isolates and defines the features. Plating is preceded by the deposition of a plating base over the entire wiring pattern that has been defined lithographically. Layers that improve adhesion and prevent conductor/insulator interactions and diffusion are deposited between the plating base and the insulator. A schematic representation of the process is shown in Figs. 1-5.
• the insulator layer (Si oxide, polymer) 1 cladded by etch/planarization layers (Si nitride) 2 and 7 is first deposited on the wafer 8; a resist pattern 3 is formed on the cladded insulator and transferred to the insulator; a barrier material 4 and a seed layer (Cu) 5 are subsequently deposited, and Cu 6 is electroplated so that all features are filled; the structure is brought to its final shape as shown in Fig. 5 by planarization. It is possible to define lithographically multiple levels of patterns onto the insulator as shown in Fig. 6; in this cost-saving fabrication method, the same sequence of layer deposition is followed.
• the rate of electroplating should be higher at low or deep points within the feature than elsewhere. This is illustrated in Figs. 7-12 where three possible cases of metal deposition are described.
• metal deposition within features 11 by using additives to the plating bath is faster than outside feature 11 at point 12 and results in void-free and seamless deposits (superfilling) shown in Fig. 8.
• the preferential deposition in the interior of features may be due to lower transport rates of additives at those locations which in turn leads to an increase in the local rate of Cu deposition. Specifically at interior corners, the rate of additive transport is lowest thus the rate of Copper deposition is highest.
• metal deposition within features 14 is slower than outside the feature 14 at point 15 and results in voids and high-resistivity lines or vias because deposition within low points 16 of features 14 is from a bath with higher degree of depletion of the depositing ion.
• the higher degree of ion depletion gives rise to a locally elevated overpotential in the plating bath for the deposition reaction.
• deposition rates everywhere, inside feature 17 and outside feature 17 at point 18, are equal (conformal filling) because there is no local ion depletion in the liquid plating bath and because the additives and their beneficial effects (preferential deposition in interior features) are missing.
• Electroplating according to the invention herein is one of the best ways by which void- free and seamless lines and vias can be accomplished.
• Copper plating from solutions incorporating additives conventionally used to produce level deposits on a rough surface can be used to accomplish superfilling required to fill sub-micron cavities.
• One suitable system of additives is the one marketed by Enthone-OMI, Inc., of New Haven, Connecticut and is known as the SelRex Cubath M system. The above additives are referred to by the manufacturer as MHy.
• Another suitable system of additives is the one marketed by LeaRonal, Inc., of Freeport, New York, and is known as the Copper Gleam 2001 system. The additives are referred to by the manufacturer as Copper Gleam 2001 Carrier, Copper Gleam 2001-HTL, and Copper Gleam 2001 Leveller.
• Cupracid HS Cupracid HS
• the additives in this system are referred to by the manufacturer as Cupracid Brightener and Cupracid HS Basic Leveller.
• Table II lists a number of sulfur-containing compounds with water-solubilizing groups such as 3-mercaptopropane-l-sulfonic acid which may be added to a bath in the instant invention.
• Table III lists organic compounds such as polyethylene glycol which may be added to a bath as surfactants in the instant invention.
• H-G Creutz et al . entitled “Electrodeposition of Copper from Acidic Baths,” describes copper sulfate and fluoborate baths for obtaining bright, low-stress deposits with good leveling properties that contain organic sulfide compounds of the formula XR X - (S n ) -R 2 -S0 3 H, where R x and R 2 are the same or different and are polymethylene groups or alkyne groups containing 1-6 carbon atoms, X is hydrogen or a sulfonic group, and n is an integer of 2-5 inclusive, which patent is incorporated herein by reference.
• baths may contain polyether compounds, organic sulfides with vicinal sulphur atoms, and phenazine dyes.
• Table I lists a number of polysulfide compounds which may be added to a bath in the instant invention.
• Table II lists a number of polyethers which may be added to a bath in the instant invention.
• Additives may be added to the bath for accomplishing various objectives.
• the bath may include a copper salt and a mineral acid.
• Additives may be included for inducing in the conductor specific film microstructures including large grain size relative to film thickness or randomly oriented grains.
• additives may be added to the bath for incorporating in the conductor material molecular fragments containing atoms selected from the group consisting of C, 0, N, S and Cl whereby the electromigration resistance is enhanced over pure Cu .
• additives may be added to the bath for inducing in the conductor specific film microstructures including large grain size relative to film thickness or randomly oriented grains, whereby the electromigration behavior is enhanced over non-electroplated Cu.
• Figure 14 shows a cross-sectional view of the cavity-filling behavior of a plating solution containing 0.3 M cupric sulfate and 10% by volume sulfuric acid of the prior art.
• Plating has been interrupted before complete cavity filling to measure deposit thickness at various locations of the feature thus determining the type of filling. It is seen that conformal deposits of Cu 30 are obtained. However, a deposit obtained by the same solution to which chloride ion and MHy additive have been added, exhibits superfilling as shown in Figure 15. The deposition rate deep within the feature is higher than elsewhere, and finally the deposit of Cu 36 shown in Fig. 15 will be void- free and seamless due to higher plating rates inside the feature than outside the feature .
• MHy concentrations that produce superfilling are in the range from about 0.1 to about 2.5 percent by volume. Chloride ion concentrations are in the range from 10 to 300 ppm.
• Copper Gleam 2001-HTL in the range from 0.1 to 1% by volume
• Copper Gleam 2001 Leveller in the range 0 to 1% by volume.
• similar superfilling results are obtained from a solution containing cupric sulfate, sulfuric acid, and chloride in the ranges mentioned above and Atotech additives Cupracid Brightener in the range from 0.5 to 3% by volume and Cupracid HS Basic Leveller in the range from 0.01 to 0.5% by volume .
• wide features in the range from 1 to 100 microns will fill more slowly than do narrow features having a width less than 1 micron, such as about 0.1 and above; hence wide features necessitate both a longer plating time and a longer polishing time to produce a planarized structure with no dimples or depressions on the top plated surface.
• cavities of greatly different widths such as less than 1 micron and greater than 10 microns are filled rapidly and evenly at the same rate.
• the meniscus of the electrolyte is the curved upper surface of a column of liquid.
• the curved upper surface may be convex such as from capillarity or due to liquid flow such as from an upwelling liquid.
• Figure 16 is a cross-sectional view of a substrate 60 which may have an upper layer of dielectric 61 such as silicon dioxide having surface features or cavities 62 and 63 formed therein for damascene wiring. Cavities 62 may have a width less than one micron and cavity 63 may have a width in the range from 1 to 100 microns.
• a liner 64 may provide adhesion to dielectric 61 and provide a diffusion barrier to metals subsequently plated. Liner 64 may be conductive to act as a plating base for electroplating or an additional plating base layer may be added.
• Figure 17 is a cross-sectional view of substrate 60 having an electrodeposit of metal 66 sufficient to fill cavities 62 and to fill the wide cavity 63 which was plated in an immersion-type cell.
• wide feature 63 fills slower than narrow or submicron features 62.
• the upper surface 67 has a dip 68 over feature 63 with respect to the average height of metal 66.
• like references are used for functions corresponding to the apparatus of Figs. 16 and 17.
• Figure 18 is a cross-sectional view of substrate 60 having an electrodeposit of metal 66 which may be Cu sufficient to fill cavities 62 and to fill wide cavity 63 which was plated in a meniscus-type cup plating cell. As shown in Figure 18, the substrate may be placed in contact with the surface of the bath. The bath may be flowed at the surface of the bath.
• electrodeposit of metal 66 which may be Cu sufficient to fill cavities 62 and to fill wide cavity 63 which was plated in a meniscus-type cup plating cell.
• the substrate may be placed in contact with the surface of the bath.
• the bath may be flowed at the surface of the bath.
• wide feature 63 fills as fast as narrow features 62.
• the upper surface 69 has a very little dip over feature 63 with respect to the average height of metal 66. Accordingly, we describe a mode of the invention in which the plating is done in a cup plater to achieve even superfilling of narrow and wide features. It is believed that the superior performance of meniscus plating is due to the higher concentration and perhaps different orientation of the surface-active additive molecules at the air-liquid surface. Though these molecules may begin to redistribute when the substrate is introduced, residual effects probably persist throughout the plating period, several minutes in duration.
• the electroplated Cu metal 66 shown in Figs. 16 and 17 consists substantially of Cu and may also contain small amounts of atoms and/or molecular fragments of C (less than 2 weight percent) , with O (less than 1 weight percent) , N (less than 1 weight percent) , S (less than 1 weight percent) , or Cl (less than 1 weight percent) .
• C less than 2 weight percent
• O less than 1 weight percent
• N less than 1 weight percent
• S less than 1 weight percent
• Cl less than 1 weight percent
• Chlorine is co-absorbed due to its synergistic role in activating additive action. As a result, it is believed that these inclusions reside in the grain boundaries and in so doing, they do not affect the resistivity of the plated metal.
• the grain size of electroplated Cu is generally larger than that produced by other Cu deposition techniques (see Figures 19 a-d and 20 a-d) .
• Figures 19 a-d are, respectively, a grain orientation map, grain contrast map, inverse pole figure and (111) pole figure of the same region for a 1 micron thick plated Cu film. The grain size is approximately 1.4 microns and the crystallographic texture is random.
• Figures 20 a-d are, respectively, a grain orientation map, grain contrast map, inverse pole figure and (111) pole figure of the same region for a 1 micron thick PVD Cu film. The grain size is approximately 0.4 microns and this film has a strong (111)/ (100) crystallographic texture.
• the crystallographic orientation (also known as texture) of plated Cu is substantially more random than that of non- plated Cu films (see Figures 19 a-d and 20 a-d) .
• This random orientation is indicated by the uniform distribution of grains in the inverse pole figure or the (111) pole figure (see Figures 19 a-d) .
• This is substantially different from that seen for non-plated Cu films.
• Figures 20 a- d where there is substantial (100) and (111) texture in this PVD Cu film.
• the electromigration resistance of electroplated Cu and pure Cu is a function of the activation energy as measured by the methods referred to in MRS Bulletin, Volume XVIII, No. 6 (June 1993) , and Volume XIX, No. 8 (August 1994) , which are incorporated herein by reference.
• the activation energy of electroplated Cu is equal to or greater than 1.0 eV.
• Figures 21a and 21b show a comparison of the drift velocity of plated versus a PVD film.
• the plated Cu shows little change in resistance over time whereas the PVD Cu film resistance increases dramatically.
• the change in resistance is related to the amount of electromigration damage in the Cu line.
• Clearly plated Cu has a much improved electromigration behavior than does PVC Cu .
• the activation energy for plated Cu is 1.1-1.3 eV while that for PVD Cu is considerably less (0.7-0.8 eV) .
• the value of the present invention extends beyond implementation in damascene structures.
• the increased resistance to electromigration, associated with the presence of atoms and/or molecular fragments containing C, O, N, S, and Cl, is similarly beneficial in conductor elements that are fabricated by through-mask plating on a planar base as shown in Figs. 22-26, by through-mask plating on an excavated base as shown in Figs. 22 and 27-31, or by blanket plating followed by patterned etching as shown in Figs. 22, 23 and 32-35.
• Figs. 22-26 The process for through-mask plating on a planar base is shown in Figs. 22-26.
• Fig. 22 shows an insulating layer 1.
• Fig. 23 shows a seed layer (Cu) 5 formed over insulating layer 1.
• a barrier material 4 (not shown) may be placed as a layer between insulating layer 1 and seed layer 5.
• Fig. 24 shows resist 71 which has been patterned over seed layer 5.
• Fig. 25 shows Cu 6 after electroplating through resist 71.
• Fig. 26 shows the structure of Fig. 25 with resist 71 removed and with seed layer 5 removed where not protected by Cu 6.
• Fig. 26 shows a patterned layer of Cu 6 over the patterned seed layer 5.
• Figs. 22 and 27-31 The process for through-mask plating on an excavated base is shown in Figs. 22 and 27-31.
• Fig. 22 shows an insulating layer 1.
• Fig. 27 shows a channel 72 formed in insulating layer 1.
• Fig. 28 shows a seed layer (Cu) 5 formed over insulating layer 1.
• a barrier material 4 (not shown) may be formed underneath seed layer (Cu) 5.
• Fig. 29 shows resist 71 which has been patterned over seed layer 5.
• Fig. 30 shows Cu 6 in channel 72 and over seed layer 5 which was deposited by plating through mask or resist 71.
• Fig. 31 shows Cu 6 with resist 71 removed and with seed layer 5 removed where not protected by Cu 6. It is noted that the superfilling attribute of the plating process of this invention makes it possible to fill cavities or features in the excavated base without remnant voids or seams.
• Figs. 22, 23 and 32-35 The process for blanket plating followed by pattern etching is shown in Figs. 22, 23 and 32-35 for forming patterned lines on an insulating layer.
• Fig. 22 shows an insulating layer 1.
• Fig. 23 shows a barrier layer 4 formed over insulating layer 1.
• a seed layer (Cu) 5 is formed on the upper surface of barrier layer 4.
• a blanket layer 76 of Cu is formed as shown in Fig. 32 by electroplating over seed layer 5.
• a layer of resist 71 is formed over blanket layer 76 and lithographically patterned as shown in Fig. 33.
• Fig. 34 shows blanket layer 76 patterned by etching or removing by other processes where not protected by resist 71.
• Fig. 35 shows the patterned blanket layer 76 with resist 71 removed.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Electroplating Methods And Accessories (AREA)
• Electroplating And Plating Baths Therefor (AREA)
• Electrodes Of Semiconductors (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Applications Claiming Priority (1)

Publications (1)

Family

ID=22256261

Family Applications (1)

Country Status (5)

Cited By (2)

Families Citing this family (39)

Family Cites Families (2)

• 1996
  • 1996-12-16 AU AU13308/97A patent/AU1330897A/en not_active Abandoned
  • 1996-12-16 JP JP10527646A patent/JP2000510289A/ja active Pending
  • 1996-12-16 WO PCT/US1996/019592 patent/WO1998027585A1/en not_active Application Discontinuation
  • 1996-12-16 KR KR1019990705116A patent/KR20000057470A/ko active Search and Examination
  • 1996-12-16 EP EP96944775A patent/EP0932913A1/en not_active Withdrawn

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events