EP0931352A1 - Thyristor a commande par gachette - Google Patents

Thyristor a commande par gachette

Info

Publication number
EP0931352A1
EP0931352A1 EP98945056A EP98945056A EP0931352A1 EP 0931352 A1 EP0931352 A1 EP 0931352A1 EP 98945056 A EP98945056 A EP 98945056A EP 98945056 A EP98945056 A EP 98945056A EP 0931352 A1 EP0931352 A1 EP 0931352A1
Authority
EP
European Patent Office
Prior art keywords
thyristor
cell
zone
thyristor according
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98945056A
Other languages
German (de)
English (en)
Inventor
Jenö Tihanyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE1997132912 external-priority patent/DE19732912C2/de
Priority claimed from DE1997139498 external-priority patent/DE19739498C1/de
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0931352A1 publication Critical patent/EP0931352A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
    • H01L29/742—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a field effect transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect

Definitions

  • the present invention relates to a gate controlled
  • Thyristor such as a cascode MOS thyristor in which an IGBT (Insulated Gate Bipolar Transistor) le in a first cell h ⁇ and a thyristor are connected in the main cell so that the first cell and the main cell a late- ral-FET with a channel of the first conductivity type.
  • IGBT Insulated Gate Bipolar Transistor
  • Such a cascode MOS thyristor was proposed many years ago (DE-A-30 24 015) and has recently been put up for discussion again as “MCCT” (MOS Controlled Cascode Thyristor) (cf. the report “1200 V MCCT: A New Concept Three Terminal MOS-Gated Thyristor "by N. Iwamuro, T. Iwaana, Y. Harada and Y. Seki at the ISPSD 97 conference).
  • MCCT MOS Controlled Cascode Thyristor
  • Such a cascode MOS thyristor like general MOS-controlled bipolar structures, such as IGBTs and MCTs (MOS Controlled Thyristor), is preferred over MOSFETs due to its relatively low on-resistance.
  • Known ⁇ Lich to generally lock a very high voltage switch, but when they are switched on or conductive, have a very low resistance.
  • the main cell A consists in particular of an anode electrode 1, a p- (or p + -) conductive zone 2, an n-conductive base zone 3, a p-conductive base zone 5 with an edge 5 'and an n-conductive emitter zone 9 with a Edge 9 '.
  • An insulator layer 8 made of, for example, silicon dioxide is arranged on the emitter zone 9.
  • the first cell B has a gate contact 10 with an edge 10 'of polysilicon, an n + -le ⁇ tende zone 11 with a Kan ⁇ te 11', a p-type region 6 with an edge 6 'and a contact 12 and forms a first IGBT.
  • the second cell C has a gate contact 13 with an edge 13 'made of polycrystalline silicon, an n + -doped zone 14 with an edge 14', a p-doped zone 4 with an edge 4 'and a contact 7 made of aluminum, for example forms a second IGBT.
  • the IGBTs are thus in contact with the cathode electrode, while the thyristor has a channel zone, but has no cathode contact.
  • This cascode MOS thyristor is relatively low, while it can block a high voltage after the gate voltage has been switched off.
  • a gate controlled thyristor which auszeich by a particularly low on- ⁇ net
  • a charge carrier-recombination-enhancing layer devised in a cascode MOS thyristor of the type mentioned in the emitter region m of the thyristor
  • This layer can consist of a metal or silicide, such as aluminum, titanium silicide, etc.
  • a second cell with egg ⁇ nem MOS switch may be connected forming a FET having a channel of the second conductivity type with the main cell.
  • the thyristor cathode When the gate voltage is positive (see FIG. 8), the thyristor cathode is grounded, so that the on-resistance is extremely small. 0 V or a negative gate voltage to, the first cell as the lateral and vertical FET (field effect transistor) is turned off, while the second cell than in ⁇ play, p-channel FET conducts and no current flows.
  • the individual cells can, for example, be arranged next to one another in strips. It is also possible the first
  • the dimensions for the cells can be selected as desired, and only the first cell can be provided together with the main cell.
  • an insulator layer Under the first cell and the second cell can ⁇ given if an insulator layer are positioned, which provides n-conductive for a better flooding of the particular base region with carriers, thereby switching resistor for an even smaller Em-.
  • This insulator layer can optionally extend as far as the p-type base zone of the thyristor or the main cell. In this case, when the insulator layer reaches the p-type base region, there should be an opening in this to increase the effectiveness of the IGBT.
  • An advantage of the present invention is that a gate controlled thyristor can be created, the FETs of which can be designed practically as desired, so that they can be adapted to a wide variety of applications.
  • At least one trench, in which an insulated gate electrode is provided, is introduced into the lateral FET.
  • At least one trench with a gate electrode is advantageously also introduced into the FET of the second cell.
  • the gate-controlled thyristor according to the invention is simple to produce using customary method steps and is even superior to the existing cascode MOS thyristor in terms of its conductivity, since its side wall FETs formed by the trenches have a large channel area.
  • FIG. 1 shows a section through a first exemplary embodiment of the thyristor according to the invention
  • FIG. 5 shows a section through a fourth exemplary embodiment of the thyristor according to the invention, 6 shows a schematic top view of the trench structure,
  • FIG. 8 shows a section through a conventional cascode MOS thyristor.
  • Fig. 1 shows em first exemplary embodiment of the present invention with a gate-controlled thyristor, which has a very low on resistance.
  • the n-type emitter zone 9 is arranged with a layer 15 made of a metal or silicide, such as aluminum or titanium silicide, which increases the charge carrier recombination. If necessary, other silicides or general materials can be selected for this, which increase the recombination rate of the charge carriers.
  • the gate-controlled thyristor m is constructed in a similar manner to the thyristor of FIG. 8, although the IGBT m of the second cell C has no n + -doped zone 14, so that the edge 14 'is also omitted here.
  • Cell B is therefore a normal IGBT source cell with the n -doped zone 11m of the p-doped zone 6 forming a well.
  • the second cell C has no n * in the p-doped zone 4. -dot ⁇ erte zone.
  • the first cell B and the main cell A thus form an n-channel lateral FET, while the second cell C and
  • Main cell A represent a p-channel FET.
  • the epitaxially grown n-type base region 3 and / or the entire structure may be fully or partially filled with a service life Le ⁇ killer, he testified be ⁇ crystal defects doped by irradiation such as gold, platinum or the like.
  • the lateral FETs with trenches 20 filled with insulated gate electrodes are introduced, as can be seen from the top view of FIG. 6; these trenches 20, which are arranged at a distance from one another perpendicular to the plane of the drawing in FIG. 1, permit virtually any configuration of the two FETs (cf. FIG. 7) and ensure a large channel area.
  • the edge 14 ' (shown in broken lines in FIG. 6) is only present if the layer 14 is additionally introduced in the layer 4, as in FIG. 8.
  • an insulator layer 16 can be provided below the two cells B and C, that is to say below the p-type zones 6 and 4, but does not extend as far as the p-type base zone 5, as shown in FIG 2 is shown.
  • This insulator layer 16 ensures an even better “flooding” of the n-conducting zone 3 with charge carriers, which further lowers the switch-on resistance .
  • the "deleted" reference numerals for the respective edges are partially omitted in FIGS. 4 and 5 for the sake of clarity.
  • the insulator layers 16 can extend as far as the p-conducting base zone 5 and in some cases even cover it. In this case, however, m of the p-base zone 5 an opening 17 to be present to the IGBT effect of
  • intermediate zones 19 are relatively weakly doped and either n- or p-conductive.
  • Fig. 5 shows another embodiment of the Invention ⁇ proper gate controlled thyristor, is provided in which a metal layer 18 above the n ⁇ -type emitter zone 9 on the layer 15.
  • FIG. 3 An equivalent circuit diagram for the gate-controlled thyristor of the above exemplary embodiments is shown in FIG. 3. If the gate voltage at gate G is positive, the thyristor cathode is grounded so that the on-resistance is low. However, if there is 0 V or a negative voltage at gate G, the first cell B is switched off as a lateral and vertical FET, while the second cell C is conducting as a p-channel FET and no current flows.
  • the trench 20 is “filled” in the usual way with an insulated gate electrode, for which purpose suitable materials (for example polysilicon as gate electrode, SiO 2 as gate insulator, etc.) can be used.
  • suitable materials for example polysilicon as gate electrode, SiO 2 as gate insulator, etc.
  • the side wall of the trench 20 acts as a channel region of a MOSFET.
  • the invention thus enables a gate-controlled thyristor which has an extremely low on-resistance and is nevertheless able to block high voltages.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

L'invention concerne un thyristor à commande par gâchette, dans lequel un transistor bipolaire à grille isolée situé dans une première cellule (B) et un thyristor situé dans une cellule principale (A) sont interconnectés de manière que la première cellule (B) et la cellule principale (A) forment un transistor latéral avec un canal du premier type de conductivité. Dans la zone émettrice du thyristor, une couche (15) renforçant la recombinaison du porteur de charge est insérée, afin de réduire la résistance d'enclenchement du thyristor à commande par gâchette. Des fossés (20) remplis d'électrodes à gâchette isolées sont pratiqués dans le transistor à effet de champ latéral, de manière que ce dernier se présente sous forme de transistor à effet de champ à paroi latérale.
EP98945056A 1997-07-30 1998-07-29 Thyristor a commande par gachette Withdrawn EP0931352A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE19732912 1997-07-30
DE1997132912 DE19732912C2 (de) 1997-07-30 1997-07-30 Kaskoden-MOS-Thyristor
DE1997139498 DE19739498C1 (de) 1997-09-09 1997-09-09 Gate-gesteuerter Thyristor
DE19739498 1997-09-09
PCT/DE1998/002154 WO1999007020A1 (fr) 1997-07-30 1998-07-29 Thyristor a commande par gachette

Publications (1)

Publication Number Publication Date
EP0931352A1 true EP0931352A1 (fr) 1999-07-28

Family

ID=26038714

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98945056A Withdrawn EP0931352A1 (fr) 1997-07-30 1998-07-29 Thyristor a commande par gachette

Country Status (4)

Country Link
US (1) US6313485B1 (fr)
EP (1) EP0931352A1 (fr)
JP (1) JP2001501383A (fr)
WO (1) WO1999007020A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2172976A3 (fr) * 1998-09-10 2010-05-05 Mitsubishi Denki Kabushiki Kaisha Dispositif semi-conducteur
US7982528B2 (en) * 2006-05-18 2011-07-19 Stmicroelectronics, S.R.L. Three-terminal power device with high switching speed and manufacturing process

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4007474A (en) * 1972-12-29 1977-02-08 Sony Corporation Transistor having an emitter with a low impurity concentration portion and a high impurity concentration portion
DE3024015A1 (de) * 1980-06-26 1982-01-07 Siemens AG, 1000 Berlin und 8000 München Steuerbarer halbleiterschalter
US5262336A (en) * 1986-03-21 1993-11-16 Advanced Power Technology, Inc. IGBT process to produce platinum lifetime control
GB2213988B (en) 1987-12-18 1992-02-05 Matsushita Electric Works Ltd Semiconductor device
US4982258A (en) 1988-05-02 1991-01-01 General Electric Company Metal oxide semiconductor gated turn-off thyristor including a low lifetime region
JP2752184B2 (ja) * 1989-09-11 1998-05-18 株式会社東芝 電力用半導体装置
JPH03253078A (ja) * 1989-12-21 1991-11-12 Asea Brown Boveri Ag 遮断可能なパワー半導体素子
JP3321185B2 (ja) * 1990-09-28 2002-09-03 株式会社東芝 高耐圧半導体装置
US5306930A (en) * 1992-12-14 1994-04-26 North Carolina State University At Raleigh Emitter switched thyristor with buried dielectric layer
JP2951134B2 (ja) * 1992-12-18 1999-09-20 株式会社日立製作所 半導体スイッチング素子
FR2712428B1 (fr) * 1993-11-10 1996-02-09 Sgs Thomson Microelectronics Commutateur bidirectionnel à commande en tension.

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9907020A1 *

Also Published As

Publication number Publication date
JP2001501383A (ja) 2001-01-30
WO1999007020A1 (fr) 1999-02-11
US6313485B1 (en) 2001-11-06

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