EP0927387A2 - Procede permettant des operations de lecture memoire et appareil correspondant a carte d'acquisition d'images conforme a la norme vga - Google Patents

Procede permettant des operations de lecture memoire et appareil correspondant a carte d'acquisition d'images conforme a la norme vga

Info

Publication number
EP0927387A2
EP0927387A2 EP98909862A EP98909862A EP0927387A2 EP 0927387 A2 EP0927387 A2 EP 0927387A2 EP 98909862 A EP98909862 A EP 98909862A EP 98909862 A EP98909862 A EP 98909862A EP 0927387 A2 EP0927387 A2 EP 0927387A2
Authority
EP
European Patent Office
Prior art keywords
memory
random access
access memory
command
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98909862A
Other languages
German (de)
English (en)
Inventor
George Lyons
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of EP0927387A2 publication Critical patent/EP0927387A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory

Definitions

  • the present invention relates generally to interface circuitry between an information processing unit such as a personal computer and a display device such as a color video monitor.
  • the present invention relates to improving the efficiency of obtaining information stored in random access memory of a display adaptor compliant with interface specifications such as the Video Graphics Array standard by improving the way in which graphics controller latches are used.
  • Video adaptors conform to a variety of interface specifications, some of which are recognized standards and others of which are proprietary.
  • One well-known standard is the Video
  • VGA Graphics Array
  • each storage location in the video RAM of a VGA-compliant adaptor is individually addressable. The exact way in which this information is organized depends on the specific graphics mode that is used. In packed-pixel modes, information for one or more pixels are packed into each memory location. For example, one storage location could record 32 bits in which eight bits of information is stored for each of four pixels representing any one of 256 colors. In planar modes, video RAM is organized into several parallel planes. In one particular 16-color graphics mode, for example, four one-bit planes collectively provide for each pixel a four-bit value, thereby conveying any one of sixteen colors.
  • RAM random access memory
  • One or more "palettes” may be used in a display adaptor to translate the values stored in RAM into specific red, green and blue (RGB) levels which define particular colors.
  • RGB red, green and blue
  • a memory-read instruction when executed in packed-pixel mode, all information stored at a designated address is accessed. For the example mentioned above, the process of obtaining information for a single pixel results in information for four pixels being read.
  • a memory-read command is executed in planar mode, information is read from multiple planes at a designated address. In one particular planar mode, for example, a memory- read instruction obtains four bytes of information, one byte from each of four memory planes.
  • the information that is read from memory is not sent immediately to the device that requested it but instead is copied into one or more graphics controller latches and then subsequently returned to the requesting device.
  • Nearly all modern implementations of display adaptors use RAM to increase the speed at which video signals can be generated to render an image on a video display device.
  • a number of developments in the field of information processing, including the use of graphic display modes and a need to display greater numbers of colors to achieve more accurate rendering of color images, has lead to an increase in the amount of RAM that is typically used in a display adaptor. For example, several megabytes of RAM are used in display adaptors that are capable of supporting screen display resolutions of 1280 x 1024 pixels and/or are capable of displaying more than 16 million different colors.
  • Unfortunately as the amount of information stored in RAM has increased, the amount of time required to effect changes in displayed images has also increased; therefore, advances in faster memory management such as memory caching and dual-port RAM have been sought to improve the efficiency of generating display images.
  • a display adaptor comprises random access memory having a plurality of locations, each of location capable of storing a plurality of bits representing display attributes of one or more pixels in a display image, and a control circuit having a command input and a data output, the control circuit coupled to the random access memory so as to have read access to the locations, thereby being capable of generating a data signal at the data output in response to a memory-read command signal received at the command input, the data signal representing digital information stored in a respective location, the control circuit also having a latch circuit coupled to the random access memory so as to be capable of latching information representing the respective location and the digital information, wherein, in response to a subsequent memory-read command signal, the control circuit is capable of generating the data signal in response to information latched in the latch circuit without access to the random access memory whenever the subsequent memory-read command signal requests reading information in the random access memory stored at the respective location.
  • a method for generating an output signal representing digital information stored at a respective location in random access memory in response to a memory-read command comprises the steps of: receiving a command signal and determining whether the received command signal represents a memory- read command for reading information from the random access memory; if the received command signal does not represent a memory-read command, clearing a saved address if processing of a command represented by the received command signal affects contents of the random access memory, processing the command represented by the received command signal, and bypassing the following steps: if the received command signal does represent a memory-read command, determining whether the saved address agrees with a command address specified by the memory-read command; if the saved address does not agree with the command address, saving the command address as a new saved address, processing the memory-read command represented by the received command signal, wherein the processing includes obtaining information
  • a medium readable by a machine embodying a program of instructions executable by the machine to perform a method in a display adaptor comprising random access memory, wherein the method is equivalent to the method recited in the previous paragraph.
  • a display adaptor comprises random access memory having a plurality of locations, each of the locations capable of storing a plurality of bits representing display attributes of one or more pixels in a display image; a latch coupled to the random access memory so as to be capable of latching digital information stored in a location of the random access memory; and control means coupled to the random access memory and to the latch for generating an output signal in response to a command signal representing a memory-read command, wherein the output signal represents digital information stored at a specified location in the random access memory specified by the memory-read command, wherein the control means generates the output signal in response to information in the latch without access to the random access memory whenever the memory-read command requests information in the random access memory at a location corresponding to the information in the latch.
  • Display adaptors incorporating the present invention may be implemented using discrete components or high-level application-specific integrated circuits (ASIC), for example, and may include microprocessors or other forms of program-controlled circuits.
  • ASICs are used to obtain an implementation that is less expensive to manufacture than can be achieved by many other techniques; however, no particular implementation is critical to the practice of the present invention.
  • Fig. 1 is a functional block diagram of a typical personal computer incorporating a display adaptor for interfacing with a display device.
  • Fig. 2 is a functional block diagram of one embodiment of a display adaptor.
  • Fig. 3 is a flow diagram illustrating various aspects of one embodiment of a method according to the present invention.
  • Fig. 1 is a functional block diagram of a typical personal computer incorporating a display adaptor for interfacing with a display device.
  • CPU 2 provides computing resources.
  • Input/output 3 represents an interface to I/O device 4 such as a keyboard, mouse, modem or printer.
  • Storage controller 6 represents an interface to storage device 7 such as a magnetic tape drive or a disk drive.
  • Display adaptor 8 provides an interface to display device 9.
  • RAM 5 is system random access memory that should not be confused with any video RAM that may exist in display adaptor 8.
  • the functions of one or more of these components can be implemented in a wide variety of ways including discrete logic components, one or more ASICs and/or program-controlled processors.
  • bus 1 which may represent more than one physical bus.
  • some personal computers incorporate only a so called Industry Standard Architecture (ISA) bus.
  • ISA Industry Standard Architecture
  • Many more modern computers incorporate an ISA bus as well as a higher bandwidth bus conforming to some bus standard such as the VESA local bus standard or the PCI local bus standard.
  • display adaptor 8 connects to a high-bandwidth bus to improve the speed of display; however, a bus architecture is not required to practice the present invention.
  • the present invention pertains to features of display adaptor 8; therefore, all of the components illustrated in Fig. 1 are not required to practice the present invention.
  • a display adaptor incorporating aspects of the present invention may be used in an information processing system that includes only CPU 2, input/output 3 connected to some input device 4 such as a switch or keypad, RAM 5, display adaptor 8 and display device 9.
  • Fig. 2 is a functional block diagram of one embodiment of display adaptor 8.
  • controller 100 is coupled to bus 1 to send and receive signals conveying various types of information. For example, controller 100 receives commands from path 11, addresses from path 13, data from path 15 and timing from path 17. Controller 100 sends data to bus 1 along path 15.
  • a command received from path 11 is a memory-read command
  • the address received from path 13 indicates the location in memory that is to be read. Data that is obtained from memory by the read is placed into latch 102 and sent along path 15. If a command received from path 11 is a memory-write command, the address received from path 13 indicates the location in memory where data received from path 15 is to be written.
  • Controller 100 uses memory controller 104 to access video RAM 106.
  • Information read from video RAM 106 passes through memory controller 104 onto memory bus 109.
  • Information written into memory passes from memory bus 109 through memory controller 104 into video RAM 106.
  • memory bus 109 is a 32-bit bus. This width is not critical to the present invention and other widths can be used.
  • Cache 108 is optional but can be used to decrease the time required to access information stored in video RAM 106. Whether or not caching is used, information read from a location in video RAM 106 is placed into latch 102.
  • Video output 110 generates a video output display signal in response to information obtained from video RAM 106.
  • Video output 110 is critical to the practice of the present invention but typical implementations includes a first-in-first-out (FIFO) buffer to ease timing constraints imposed on obtaining information needed to generate a video output display signal, a palette to modify information obtained from video RAM 106 according to display attributes that can be established by controller 100, for example, to make color and gamma corrections, a video shift register to convert pixel information into a serial bit stream, and a digital-to-analog converter to generate an analog video signal. Controller 100 adapts the operation of shift register according to information such as the number of bits per pixel and also provides a video synchronization signal along path 123.
  • FIFO first-in-first-out
  • FIG. 2 The embodiment shown in Fig. 2 is intended to be generic, illustrating basic functions in a broad range of display adaptor implementations.
  • a display adaptor into which the present invention may be incorporated is model SPC8110F0A, manufactured by S MOS Systems
  • Fig. 2 The embodiment shown in Fig. 2 is also intended to be simple, omitting some elements such as buffers, clocks, sprite management, bus mastering, co-processing, pipelining and power management found in many practical implementations.
  • the features omitted from the figure may be used in a wide variety of combinations and can be implemented in many ways; however, these features are not essential to the present invention.
  • the present invention is not limited to display adaptors implemented according to any particular embodiment including the embodiment shown in Fig. 2.
  • the essential features are a latch control function described below that can be provided by controller 100, a graphics controller latch such as latch 102, and random access memory such as video RAM 106.
  • Latch Control Fig. 3 is a flow diagram illustrating functional steps in one method of a latch control function according to the present invention. The operation of this control method will be described with reference to the display adaptor embodiment shown in Fig. 2.
  • Step 202 provides initialization as required.
  • Step 204 determines whether a command received from path 11 is a memory- read command. If it is, step 208 determines whether the read address specified by the command agrees with a previously saved address. If the two addresses agree, data previously placed in latch 102 is provided to path 15. If the two addresses do not agree, the read address specified by the command is saved and the command is processed, causing the requested information to be obtained from cache 108 if possible, otherwise obtained from video RAM 106. If the command received from path 11 is not a memory-read command, step 216 determines whether execution of the command will affect the contents of video RAM 106. If it will, step 218 clears the saved address; step 212 processes the command. Step 214 can provide various housekeeping functions as desired.
  • Two common operations with graphical user interfaces that illustrate a benefit achieved by the present invention are moving and resizing display objects such as windows. Operations like these cause many iterations of commands that read data from video RAM, modify the data, and write the modified data into video RAM. According to the prior art, subsequent memory-read commands cause either cache memory 108, if implemented, or video RAM 106 to be accessed even if the desired information is available in latch 102.
  • each location stores information representing two or more pixels.
  • a move or resizing operation could be performed more efficiently by first executing memory-read commands for all pixels requiring modification that are stored in a given location. The first memory-read command to the given location would obtain the desired information from either cache 108 or video RAM 106 and place the information stored in that location into latch 102. Subsequent memory- read commands for pixel information stored in that location would obtain the desired information from latch 102. Following all the necessary reads to that location, the modified pixel information can be written to video RAM as desired.
  • the proper order for executing memory-read commands relative to other types of commands can be specified by logic in the device that requests the information, e.g., an application or operating system component, or it can be provided by either a special interface called a "device driver" in the requesting device or by logic in the display adaptor itself which examines sequences of commands and reorders them as appropriate.
  • the present invention can improve the efficiency of other types of operations which require repeated access to the same location in video RAM.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
  • Digital Computer Display Output (AREA)

Abstract

On améliore le rendement en matière de lecture d'information à partir d'une mémoire vidéo dans une carte d'acquisition d'images, une carte d'acquisition d'images conforme à la norme VGA notamment, en mettant à disposition, dans la mesure du possible, l'information désirée à partir d'un mécanisme de verrouillage plutôt qu'en l'extrayant de la mémoire vidéo ou de l'antémémoire. Il est possible d'améliorer des routines menées avec des interfaces utilisateur graphiques, des opérations de déplacement et de redimensionnement d'images par exemple, en extrayant tout d'abord une information relative à tous les pixels mémorisés en un lieu donné de la mémoire vidéo et ce, avant d'exécuter une commande modifiant le contenu de ce lieu.
EP98909862A 1997-03-25 1998-03-24 Procede permettant des operations de lecture memoire et appareil correspondant a carte d'acquisition d'images conforme a la norme vga Withdrawn EP0927387A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US82412897A 1997-03-25 1997-03-25
US824128 1997-03-25
PCT/JP1998/001297 WO1998043154A2 (fr) 1997-03-25 1998-03-24 Procede permettant des operations de lecture memoire et appareil correspondant a carte d'acquisition d'images conforme a la norme vga

Publications (1)

Publication Number Publication Date
EP0927387A2 true EP0927387A2 (fr) 1999-07-07

Family

ID=25240660

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98909862A Withdrawn EP0927387A2 (fr) 1997-03-25 1998-03-24 Procede permettant des operations de lecture memoire et appareil correspondant a carte d'acquisition d'images conforme a la norme vga

Country Status (5)

Country Link
EP (1) EP0927387A2 (fr)
JP (1) JP2001505674A (fr)
KR (1) KR20000015972A (fr)
CN (1) CN1220753A (fr)
WO (1) WO1998043154A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005351920A (ja) * 2004-06-08 2005-12-22 Semiconductor Energy Lab Co Ltd 表示装置の制御回路及びそれを内蔵した表示装置・電子機器並びにその駆動方法
US7705821B2 (en) 2005-01-31 2010-04-27 Semiconductor Energy Laboratory Co., Ltd. Driving method using divided frame period

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4672368A (en) * 1985-04-15 1987-06-09 International Business Machines Corporation Raster scan digital display system
EP0228745A3 (fr) * 1985-12-30 1990-03-28 Koninklijke Philips Electronics N.V. Dispositif de contrôle d'affichage vidéo à balayage à trame comportant une antémémoire de mise à jour, antémémoire de mise à jour pour application dans un tel dispositif de contrôle, et terminal d'affichage comportant un tel dispositif de contrôle
DE69226839T2 (de) * 1991-04-15 1999-04-22 Oki Electric Industry Co., Ltd., Tokio/Tokyo Bildverarbeitungsgerät
JPH06332664A (ja) * 1993-03-23 1994-12-02 Toshiba Corp 表示制御システム
US5579473A (en) * 1994-07-18 1996-11-26 Sun Microsystems, Inc. Interface controller for frame buffer random access memory devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9843154A2 *

Also Published As

Publication number Publication date
KR20000015972A (ko) 2000-03-25
JP2001505674A (ja) 2001-04-24
WO1998043154A2 (fr) 1998-10-01
CN1220753A (zh) 1999-06-23
WO1998043154A3 (fr) 1998-11-05

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