EP0228745A3 - Dispositif de contrôle d'affichage vidéo à balayage à trame comportant une antémémoire de mise à jour, antémémoire de mise à jour pour application dans un tel dispositif de contrôle, et terminal d'affichage comportant un tel dispositif de contrôle - Google Patents

Dispositif de contrôle d'affichage vidéo à balayage à trame comportant une antémémoire de mise à jour, antémémoire de mise à jour pour application dans un tel dispositif de contrôle, et terminal d'affichage comportant un tel dispositif de contrôle Download PDF

Info

Publication number
EP0228745A3
EP0228745A3 EP86202315A EP86202315A EP0228745A3 EP 0228745 A3 EP0228745 A3 EP 0228745A3 EP 86202315 A EP86202315 A EP 86202315A EP 86202315 A EP86202315 A EP 86202315A EP 0228745 A3 EP0228745 A3 EP 0228745A3
Authority
EP
European Patent Office
Prior art keywords
update cache
video controller
controller
raster scan
crt display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86202315A
Other languages
German (de)
English (en)
Other versions
EP0228745A2 (fr
Inventor
Craig Alden Mackenna
Jan-Kwei Jack Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Philips Gloeilampenfabrieken NV
Publication of EP0228745A2 publication Critical patent/EP0228745A2/fr
Publication of EP0228745A3 publication Critical patent/EP0228745A3/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)
EP86202315A 1985-12-30 1986-12-18 Dispositif de contrôle d'affichage vidéo à balayage à trame comportant une antémémoire de mise à jour, antémémoire de mise à jour pour application dans un tel dispositif de contrôle, et terminal d'affichage comportant un tel dispositif de contrôle Withdrawn EP0228745A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81536185A 1985-12-30 1985-12-30
US815361 1985-12-30

Publications (2)

Publication Number Publication Date
EP0228745A2 EP0228745A2 (fr) 1987-07-15
EP0228745A3 true EP0228745A3 (fr) 1990-03-28

Family

ID=25217562

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86202315A Withdrawn EP0228745A3 (fr) 1985-12-30 1986-12-18 Dispositif de contrôle d'affichage vidéo à balayage à trame comportant une antémémoire de mise à jour, antémémoire de mise à jour pour application dans un tel dispositif de contrôle, et terminal d'affichage comportant un tel dispositif de contrôle

Country Status (2)

Country Link
EP (1) EP0228745A3 (fr)
JP (1) JPS62183487A (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5185856A (en) * 1990-03-16 1993-02-09 Hewlett-Packard Company Arithmetic and logic processing unit for computer graphics system
US5579473A (en) * 1994-07-18 1996-11-26 Sun Microsystems, Inc. Interface controller for frame buffer random access memory devices
EP0927387A2 (fr) * 1997-03-25 1999-07-07 Seiko Epson Corporation Procede permettant des operations de lecture memoire et appareil correspondant a carte d'acquisition d'images conforme a la norme vga
JP3342352B2 (ja) 1997-07-04 2002-11-05 シャープ株式会社 表示用メモリ制御装置
US6311239B1 (en) * 1998-10-29 2001-10-30 Cypress Semiconductor Corp. Architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media
JP2007124200A (ja) * 2005-10-27 2007-05-17 Nittan Co Ltd 圧電振動板の取付構造

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0029517A2 (fr) * 1979-11-23 1981-06-03 International Business Machines Corporation Appareil de traitement de données avec mode d'écriture en mémoire tampon
JPS60117327A (ja) * 1983-11-30 1985-06-24 Fuji Xerox Co Ltd ディスプレイ装置
EP0150453A2 (fr) * 1984-01-12 1985-08-07 Ascii Corporation Système de commande de transfert de données entre des zones logiques de mémoire
GB2159308A (en) * 1984-05-23 1985-11-27 Univ Leland Stanford Junior High speed memory system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0029517A2 (fr) * 1979-11-23 1981-06-03 International Business Machines Corporation Appareil de traitement de données avec mode d'écriture en mémoire tampon
JPS60117327A (ja) * 1983-11-30 1985-06-24 Fuji Xerox Co Ltd ディスプレイ装置
EP0150453A2 (fr) * 1984-01-12 1985-08-07 Ascii Corporation Système de commande de transfert de données entre des zones logiques de mémoire
GB2159308A (en) * 1984-05-23 1985-11-27 Univ Leland Stanford Junior High speed memory system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, vol. 9, no. 273 (P-401), 30th October 1985; & JP-A-60 117 327 (FUJI XEROX K.K.) 24-06-1985 *

Also Published As

Publication number Publication date
JPS62183487A (ja) 1987-08-11
EP0228745A2 (fr) 1987-07-15

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Inventor name: MACKENNA, CRAIG ALDEN

Inventor name: LI, JAN-KWEI JACK