EP0150453A2 - Système de commande de transfert de données entre des zones logiques de mémoire - Google Patents

Système de commande de transfert de données entre des zones logiques de mémoire Download PDF

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Publication number
EP0150453A2
EP0150453A2 EP84115899A EP84115899A EP0150453A2 EP 0150453 A2 EP0150453 A2 EP 0150453A2 EP 84115899 A EP84115899 A EP 84115899A EP 84115899 A EP84115899 A EP 84115899A EP 0150453 A2 EP0150453 A2 EP 0150453A2
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EP
European Patent Office
Prior art keywords
area
data
register
logical
transfer
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP84115899A
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German (de)
English (en)
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EP0150453A3 (fr
Inventor
Takatoshi Ishii
Ryozo Yamashita
Kazuhiko Nishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASCII Corp
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ASCII Corp
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Publication date
Application filed by ASCII Corp filed Critical ASCII Corp
Publication of EP0150453A2 publication Critical patent/EP0150453A2/fr
Publication of EP0150453A3 publication Critical patent/EP0150453A3/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Definitions

  • the present invention relates to a display control system for use in a computer.
  • Fig. 1 there is illustrated a block diagram of a conventional color graphics display system.
  • a CPU microprocessor 1 for controlling the whole system, to which are connected a main memory 2 and a display control circuit 3.
  • Main Memory 2 is used to hold programs or data, while Display Control Circuit 3 is dedicated to controlling the display of color graphics.
  • Reference character 4 de ⁇ rtes a VRAM (video memory) for holding CRT display data and 5 designates a CRT color display unit.
  • Fig. 2 illustrates a block diagram of an embodiment of the display control circuit 3 shown in Fig. 1.
  • clock signals generated by a timing controller 11 are input to a counter,12 which comprises a column counter, a line counter and a row counter.
  • Counter 12 genereates synchronizing signals for CRT display via a display timing circuit 13, while Counter 12 creates display addresses which are output as VRAM addresses by means of a multiplexer 12.
  • Read data for display access coming from VRAM 4 is input to a video output controller 20 via a buffer 19 so as to create CRT video signals.
  • VRAM 4 when VRAM 4 is accessed by CPU 1, the addresses of VRAM 4 are set in a VRAM address register 14. And, if a write strobe is input to a CPU interface controller 18, Multiplexer 15 selects as VRAM addresses the outputs of VRAM Address Register 14 specified by CPUI and then the write data from CPU1 is written via Buffers 16, 17 into VRAM4.
  • Fig. 3(A) illustrates a logical memory space
  • Fig. 3(B) illustrates a physical memory space
  • the logical memory space there are present an operation table area, a display area and a suppcrt message area, and these three areas are started by separate values respectively and are definetely separated from one another.
  • the display area shown in Fig. 3(A) there happen some cases where a display including a plurality of superposed window frames is requested from an application software. In these cases, there arises a demand to perform data transfer between these areas.
  • the block data of a source area S within VRAM4 is transferred to a destination area D based on the X, Y coordinates.
  • the above-mentioned source area S is considered as a predetermined area (area covered by leftward-falling oblique lines) in the operation table area
  • the above destination area D is considered as a predetermined area(area covered by leftward-falling oblique lines) in the display area.
  • CPU 1 calculates a physical address SA of VRAM 4 based on the value of a base address (this is referred to as "Base SB" hereinafter) in the source area S and the start coordinates (SX, SY) and then sets it in VRAM Address Register 14 within Display Control Circuit 3. And, CPU 1 outputs a read command and reads out the color data within VRAM 4 that corresponds to the above-mentioned start coordinates (SX, SY).
  • Base SB a base address
  • CPU1 based on the Base SB of the destination area to which the block data is to be transferred and its start coordinates (DX, DY), calculates a physical address DA in VRAM 4, and then sets it in VRAM Address Register 14 within Display Control Circuit 3. And, CPU1 outputs the color data and a write command to write them into the locations of VRAM4 that correspond to the start coordinates (DX, DY) of the destination area D.
  • reference character sd designates a status display area
  • sA represents the start coordinates of a support message area
  • sB expresses the base value of the support message area.
  • the operation table area shown in Fig. 3 can be changed according to the kind of application software. That is, a very large area may be requested for it or, on the contrary, a small area may be requested. This is so with the support message area.
  • the display area has a fixed size that is determined by way of hardware by CRT Display. In this case, a predetermined window frame is assumed within the display area and a portion to be operated at that time and requiring display is brought into this window frame, while the assumed window frame is requested for displacement according to the conditions. Accordingly, the transverse width of each of the above areas can take on various values logically.
  • the data to be transferred comprises several divided blocks and the data is also to be transferred between data areas which are different from each other with respect to the distance between the blocks. Such operation can not be processed completely only by the conventional data transfer technique using successive areas which can be dealt with by hardware.
  • a conventional display control system for a personal computer is designed such that amounts of hardware, e.g., the number of gates and the number of IC elements regarding the internal structure of a display unit and interfaces are reduced considerably. As a result of this, the loads of the software are increased accordingly in such conventional system.
  • the present invention aims at eliminating the drawbacks found in the above-mentioned conventional system.
  • a display control sytem is provided with an "area movement" function, and, at the same time, the logical transverse widths of the source area S and destination area D are given separately from each other. Interfacing procedures required for this purpose are to be determined and oriented by software
  • Fig. 4 illustrates a block diagram of an embodiment of the present invention.
  • a clock generator 31 for generating a display timing clock
  • a counter 32 having a column counter, a line counter and a row counter for generating a CRT screen display timing and a VRAM address in accordance with the display timing clock.
  • a data bus 41 from CPU 1 is connected via a buffer 42 to a register data bus 43.
  • the number of registers included in Display Control Circuit 3 to be accessed by CPUl is held by a register pointer/counter 44 and the outputs of this register pointer/counter 44 are decoded by a register selector decoder 45, so that the respective registers can be specified.
  • This register pointer/counter 44 has a count-up function in addition to a register function. Namely, when a parameter is set for each register, Register Pointer/Counter 44 counts up 1 after completion of each setting. Therefore, it can specify the registers one by one automatically and successively.
  • the command information from CPU 1 is held by a command register 46, and a video CPU 47 is able to perform processings on the display data in accordance with the commands from CPU 1.
  • Status from Video CPU 47 to CPU 1 is to be held by an SR register 48.
  • CPU 1 specifies the physical address of VRAM 4 to access VRAM 4, the VRAM address is held by a VRAM address register/counter 37.
  • the write data to VRAM 4 and the read data from VRAM 4 are held by a color code register 33.
  • an SA register 71 for setting up the value of a start physical address of a source area S
  • an SW register 72 for holding the logical width SW of an operation table area
  • a DA register 73 for setting up the value of a start physical address of a destination area D
  • a DW register 74 for holding the logical width DW of a display area.
  • a base value selector 75 which selects either a value of SA Register 71 or a value of DA Register 73
  • a variation value selector 76 which selects one of a value of SW Register 72, a value of DW Register 74, and a value of an NX counter 64.
  • Base Value Selector 75 is connected to cne of inputs of an adder 80 and the output of Varia- tion Value Selector 76 is connected via a 2'S complement operation circuit 81 to the other input of Adder 80, whereby a variation value with respect to a memory address base value is added or subtracted to complete a practical circuit.
  • 2'S Complement Operation Circuit 81 is controlled by the value of either a horizontal direction flag 60 or a vertical direction flag 62 and is operable in cooperation with Adder 8C to perform addition or subtraction depending on the direction of transfer of the data.
  • the above-mentioned SA, DA registers 71, 73 are respectively provided with not only a function to receive the data established by Register Data Bus 43 therefrom but also a function to load the data from VRAM Address Bus 36 therein.
  • an NX register 61 is used to hold the number of the transfer data in a horizontal direction (an X coordinate direction), and an NY register 63 is dedicated to holding the number of the transfer data in a vertical direction (a Y coordinate direction).
  • Horizontal Direction Flag 60 points out a positive direction (a right direction) when it is “O”, while it indicates a negative direction (a left direction) when it is "1".
  • Vertical Direction Flag 62 points out a positive direction (a downward direction) when it is "O”, while it indicates a negative direction (an upward direction) when it is "I”.
  • VRAM address bus 36 which is included in Display Control Circuit 3, is connected via a buffer 55 to an address line 56 of VRAM 4.
  • a VRAM data bus 35 also in Display Control Circuit 3 is connected via a buffer 53 to a VRAM data line 54.
  • An S register 34 is used to hold the read data from the source area S, while a D register 52 is dedicated to holding the read data from the destination area D.
  • An ALU (arithmetic and logic unit) 51 is adapted to peform logical operations, such as IMP, AND, OR, EOR, NOT operations, on the outputs of S Register 34, Color Code Register 34 and D Register 52 in accordance with the control from Video CPU47.
  • Display Control Circuit 3 will be discussed here by taking as an example the transfer of a block data using the X, Y coordinates in case where the logical transverse widths of the source area S and destination area D are different from each other.
  • CPU1 When accessing each of the registers, CPU1 first sets the register number of a register to be accessed in Register Pointer/Counter 44, and thereafter performs its write operations on a series of data.
  • SA Register 71 is composed of SAL (register #30), SAM (register #31) and SAH (register #32)
  • DA Register 73 is composed of DAL (register #35), DAM (register #36) and DAH (register #37).
  • CPUl sets 6-byte parameters regarding the physical addresses SA, DA at the start points of transfer, that is, at the respective start points of the source area S and the destination area D.
  • SW Register 72 is composed of SWL (register #33) and SWH (register #34)
  • DW Register 74 is composed of DWL (register #38) and DWH (register #39).
  • FIG. 5 illustrates the contents of the registers #30 - 39
  • Fig. 6 illustrates the contents of the registers #40 - 46.
  • NX Register 61 is composed of NXL (register #40) and NXH (register #41) and NY Register 63 is composed of NYL (register #42) and NYH (register #43).
  • Direction X Flag 60 corresponds to the bit 2 of an argument register ARGR (register #45)
  • Direction Y Flag 62 corresponds to the bit 3 of an argument register ARGR (register #45).
  • Fig. 7 illustrates a table of command codes.
  • VDC stands for the display control circuit 3.
  • Fig. 8 illustrates a table of logical operations.
  • SC designates a source color code
  • DC represents a destination color code.
  • CPU1 creates a command code such as "10010000" in accordance with the above-mentioned command codes and logical operation codes, and then sets it in Command Register 46 (register #46).
  • the higher 4 bits of the above-mentioned command code are a command to transfer a block data within VRAM 4 when the source area S and the destination area D are both present within VRAM4.
  • the lower 4 bits of the same command code are a logical operation code and then "0000" is a code indicating that the source color code data as it is provides the destination color code data.
  • Video CPU 47 sets the command executing (CE) of the bit 7 of SR Register 48 and initiates an executing processing of the command.
  • the physical address SA at the above-mentioned start point is found by the following equation and is set: in SA Register 71: , where SB expresses the base of the start point and (SX,SY) expresses the coordinates of the start point.
  • Base Value Selector 75 is operated, SA Register 71 holding the physical address SA of the start point of the source area S is selected, and the physical address SA is forwarded to Adder 80.
  • Valuation Value Selector 76 is operated, NX Counter 64 is selected, and the value of NX Counter 64 is forwarded to Adder 80.
  • this source address SA(i,O) can be obtained by the following equation: , where i is a value that can be increased from O up to (NX-1) or the value i of NX Counter is increased one by one for each 1 dot transfer, and when a line of transfers in the source area S have been completed, i becomes NX to clear NX Counter.
  • SA Register 71 is updated in the following manner. Namely, Base Value Selector 75 selects the value of SA Register 71, Variation Value Selector 76 selects the value of DW Register 74 and Adder 80 adds these values, and outputs them to VRAM Address Bus 36. Further, Video CPU 47 controls the added value so that it can be loaded into SA Register 71. Accordingly, the next source address SA (0, 1) can be obtained in the following equation:
  • NX Counter 64 is counted by 1 each time 1 dot is transferred, and, if its value is expressed as i, then the source address SA (i, 1) can be found from the following equation:
  • the value i in the equation (3) is identical with the above-mentioned i, and 1 in the equation (3) indicates that 1 line has been advanced in the source area S, which can be expressed generally by the following equation:
  • the value j in the above equation (4) can be found from the amount of displacement off from the coordinates of the start point in the vertical direction.
  • the address at the start point is found from the above equation (1); the following addresses in the first line can be respectively given by the equation (2); when all of the addresses present in the first line have been completely transferred, then NX Counter 64 is cleared; addresses stored in the second and its following lines are generally given by the equation (4); and, each time the transfer of each of the lines is completed, the value i is counted 1 and the execution is handed over to the lower or following line. The above processings are then repeated.
  • data is read out from the operation table area within VRAM 4.
  • the read-out data is set via Data Line 54, Buffer 53 and VRAM Data Bus 35 into S Register 34.
  • the color code data that is held in S Register 34 and is read out from the source area side is outputted via ALU 51, VRAM Data Bus 35 and Buffer 53 onto VRAM Data Line 54 and is then written into the display area within VRAM4.
  • Procedures for creating the write address in this case are similar to those for creating the address read out from the above-mentioned source area.
  • DA Register 73 is used instead of SA Register 71
  • DW Register 74 is employed in place of SW Register 72
  • a base DB and coordinates (DX, DY) are set up instead of the base SB of the start point of the source area S and the coordinates of the start point (DX, DY); however, the procedures for deducing the above-mentioned equation (4) from the above-mentioned equation (1) are the same as above.
  • Video CPU 47 counts up NX Counter 64. And, when all of the information contained in a line is completely transferred, NY Counter 65 is counted up by Video CPU47. If "1" is set in Direction X Flag 60 and Direction Y Flag 62, then in the horizontal-/vertical-direction processings 2'S Complement Operation Circuit 81 is requested to execute a complement operation and the resultant values are added in Adder 80, that is, a subtraction is executed.
  • NX Counter 64 and NX Register 61 are compared by Comparison Circuit 66, and, if they are not identical with each other, then the data transfer can be repeated in a procedure similar to the above-mentioned one.
  • NX Register 61 and NX Counter 64 are identical, then NX Counter 64 is to be cleared.
  • NX Register 61 and NX Counter 64 are identical with each other and when the contents of NY Register 63 and NY Counter 65 are compared by Comarison Circuit 67 and found identical with each other, then a total of (NX X NY) pieces of block data have been transferred, where NX expresses the number of the X coordinate-direction block data and NY expresses the number of the Y coordinate-direction block data.
  • Video CPU 47 On detecting the coincidence of the contents of NX Register 61 with NX Counter 64 and the coincidence of the contents of NY Register 63 with NY Counter 65, Video CPU 47 decides that the block data transfer has been completed, clears the command executing (CE) bit of SR Register 48 and notifies CPU 1 of the completion of the block data transfer.
  • CE command executing
  • command code was set in Command Register 46 as "10010000"
  • the lower 4 bits L03 - LOO are used to specify the logical operations illustrated in Fig. 8
  • ALU 51 can function to execute the logical operations between S Register 34 and D Register 52.
  • block data transfer employing the X, Y coordinates within VRAM 4 was referred to, block data transfer from CPU 1 to VRAM 4, from VRAM 4 to CPU 1, and from Display Control Circuit 3 to VRAM 4 can also be executed in a similar manner to the above. Accordingly, such block data transfer will be discussed hereinbelow.
  • Video CPU 47 writes the block data to be transferred in Color Code Register 33 into VRAM 4 in accordance with DA Register 73 and DW Register 74. After then, Video CPU 47 sets the transfer ready (TR) bit of SR Register 48 and notifies CPU 1 that the transfer of 1 piece of block data is completed and that the next block data can be accepted.
  • TR transfer ready
  • CPU1 sets the next transfer data in Color Code Register 33. This resets the TR bit to return to its original status.
  • Other operations to be performed in this case are similar to those mentioned above in the case when the block data within VRAM 4 is transferred.
  • Video CPU 47 reads out the transfer data from VRAM4 in accordance with SA Register 71 and SW Register 72, sets it in Color Code Register 33, and also sets the TR bit of SR Register 48 for " 1 ".
  • CPU 1 checks the status of the TR bit and, if it is found "1", then it reads out a piece of block data from Color Code Register 33. This resets the status of the TR bit to return to its original status.
  • Other operations required in this case are similar to those mentioned above in the case in which the block data within VRAP 4 is transferred.
  • the invention can also apply to a monochromatic system and in this case the above-mentioned color code or color data can be replaced with the byte data.
  • the present invention can be effectively used to perform a display control operation for not only the color CRT but also other display units such as a monochromatic CRT, LCD, plasma, EL and the like.
  • the display memory access can be speeded up with smaller amounts of the necessary hardware increased for this purpose.
  • the invention is also effectively used in a system in which a display memory is not separated from a main memory. Further, it is quite clear that the above-mentioned effect of the invention can also be applied to data transfer in the main memory.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Memory System (AREA)
EP84115899A 1984-01-12 1984-12-20 Système de commande de transfert de données entre des zones logiques de mémoire Withdrawn EP0150453A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59002710A JPS60147785A (ja) 1984-01-12 1984-01-12 論理領域間デ−タ移動制御装置
JP2710/84 1984-01-12

Publications (2)

Publication Number Publication Date
EP0150453A2 true EP0150453A2 (fr) 1985-08-07
EP0150453A3 EP0150453A3 (fr) 1987-09-16

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EP84115899A Withdrawn EP0150453A3 (fr) 1984-01-12 1984-12-20 Système de commande de transfert de données entre des zones logiques de mémoire

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JP (1) JPS60147785A (fr)
CA (1) CA1224574A (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2587520A1 (fr) * 1985-09-13 1987-03-20 Sun Microsystems Inc Appareil et procedes d'affichage a fenetre a acces direct en memoire
EP0228745A2 (fr) * 1985-12-30 1987-07-15 Koninklijke Philips Electronics N.V. Dispositif de contrôle d'affichage vidéo à balayage à trame comportant une antémémoire de mise à jour, antémémoire de mise à jour pour application dans un tel dispositif de contrôle, et terminal d'affichage comportant un tel dispositif de contrôle
GB2202978A (en) * 1987-03-19 1988-10-05 Apple Computer Video apparatus employing vrams
US4777485A (en) * 1985-09-13 1988-10-11 Sun Microsystems, Inc. Method and apparatus for DMA window display
EP0361471A2 (fr) * 1988-09-29 1990-04-04 Canon Kabushiki Kaisha Système et dispositif de traitement de données
US5113180A (en) * 1988-04-20 1992-05-12 International Business Machines Corporation Virtual display adapter
EP0708429A1 (fr) * 1994-10-19 1996-04-24 Nec Corporation Système de commande de mémoire pour interdire la réecriture dans une région prédéterminée de la mémoire
EP0814428A2 (fr) * 1996-06-20 1997-12-29 Cirrus Logic, Inc. Méthode et appareil pour transferrer des donnés de pixel enregistrées dans un circuit mémoire

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4806921A (en) * 1985-10-04 1989-02-21 Ateq Corporation Rasterizer for pattern generator
KR100219758B1 (ko) * 1992-06-29 1999-09-01 구라우치 노리타카 알루미늄 합금제 오일펌프

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5596988A (en) * 1979-01-19 1980-07-23 Tokyo Shibaura Electric Co Crt display unit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HEWLETT-PACKARD JOURNAL, vol. 31, no. 12, December 1980, pages 25-32, Amstelveen, NL; H.L. BAEVERSTAD et al.: "Display system designed for color graphics" *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 25, no. 3A, August 1982, pages 1270-1273, New York, US; C.J. EVANGELISTI et al.: "Generalized pattern transfer from storage to storage bit buffer" *

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2180729A (en) * 1985-09-13 1987-04-01 Sun Microsystems Inc Direct memory access window display
US4777485A (en) * 1985-09-13 1988-10-11 Sun Microsystems, Inc. Method and apparatus for DMA window display
GB2180729B (en) * 1985-09-13 1989-10-11 Sun Microsystems Inc Method and apparatus for dma window display
FR2587520A1 (fr) * 1985-09-13 1987-03-20 Sun Microsystems Inc Appareil et procedes d'affichage a fenetre a acces direct en memoire
EP0228745A2 (fr) * 1985-12-30 1987-07-15 Koninklijke Philips Electronics N.V. Dispositif de contrôle d'affichage vidéo à balayage à trame comportant une antémémoire de mise à jour, antémémoire de mise à jour pour application dans un tel dispositif de contrôle, et terminal d'affichage comportant un tel dispositif de contrôle
EP0228745A3 (fr) * 1985-12-30 1990-03-28 Koninklijke Philips Electronics N.V. Dispositif de contrôle d'affichage vidéo à balayage à trame comportant une antémémoire de mise à jour, antémémoire de mise à jour pour application dans un tel dispositif de contrôle, et terminal d'affichage comportant un tel dispositif de contrôle
GB2202978A (en) * 1987-03-19 1988-10-05 Apple Computer Video apparatus employing vrams
US4884069A (en) * 1987-03-19 1989-11-28 Apple Computer, Inc. Video apparatus employing VRAMs
AU602062B2 (en) * 1987-03-19 1990-09-27 Apple Computer, Inc. Video apparatus employing vrams
GB2202978B (en) * 1987-03-19 1991-12-11 Apple Computer Video apparatus employing vrams
US5113180A (en) * 1988-04-20 1992-05-12 International Business Machines Corporation Virtual display adapter
US5345250A (en) * 1988-09-29 1994-09-06 Canon Kabushiki Kaisha Data processing system and apparatus and display system with image information memory control
US5646646A (en) * 1988-09-29 1997-07-08 Canon Kabushiki Kaisha Data processing system and apparatus processing scroll display data and cursor display data
US5359344A (en) * 1988-09-29 1994-10-25 Canon Kabushiki Kaisha Data processing system and apparatus
US5818410A (en) * 1988-09-29 1998-10-06 Canon Kabushiki Kaisha Data processing system and apparatus having first and second graphic event data
EP0361471B1 (fr) * 1988-09-29 1996-06-19 Canon Kabushiki Kaisha Système et dispositif de traitement de données
US5543817A (en) * 1988-09-29 1996-08-06 Canon Kabushiki Kaisha Data processing system and apparatus
US5574476A (en) * 1988-09-29 1996-11-12 Canon Kabushiki Kaisha Data processing system and apparatus with graphic event priority levels for storage and retrieval of different graphic event data
EP0361471A2 (fr) * 1988-09-29 1990-04-04 Canon Kabushiki Kaisha Système et dispositif de traitement de données
US5657042A (en) * 1988-09-29 1997-08-12 Canon Kabushiki Kaisha Data processing system and apparatus capable of inhibiting the storage of image data during partial rewriting
US5677706A (en) * 1988-09-29 1997-10-14 Canon Kabushiki Kaisha Data processing system and apparatus
US5784043A (en) * 1988-09-29 1998-07-21 Canon Kabushiki Kaisha Data processing system and apparatus with prioritized processing of first graphic event data and second graphic event data
US5777632A (en) * 1994-10-19 1998-07-07 Nec Corporation Storage control system that prohibits writing in certain areas
EP0708429A1 (fr) * 1994-10-19 1996-04-24 Nec Corporation Système de commande de mémoire pour interdire la réecriture dans une région prédéterminée de la mémoire
EP0814428A2 (fr) * 1996-06-20 1997-12-29 Cirrus Logic, Inc. Méthode et appareil pour transferrer des donnés de pixel enregistrées dans un circuit mémoire
EP0814428A3 (fr) * 1996-06-20 1998-08-19 Cirrus Logic, Inc. Méthode et appareil pour transferrer des donnés de pixel enregistrées dans un circuit mémoire

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EP0150453A3 (fr) 1987-09-16
JPS60147785A (ja) 1985-08-03
CA1224574A (fr) 1987-07-21

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