EP0878008A1 - Circuit de compensation de charge de reenclenchement - Google Patents

Circuit de compensation de charge de reenclenchement

Info

Publication number
EP0878008A1
EP0878008A1 EP97902877A EP97902877A EP0878008A1 EP 0878008 A1 EP0878008 A1 EP 0878008A1 EP 97902877 A EP97902877 A EP 97902877A EP 97902877 A EP97902877 A EP 97902877A EP 0878008 A1 EP0878008 A1 EP 0878008A1
Authority
EP
European Patent Office
Prior art keywords
charge
converter
fet
switch
reset switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97902877A
Other languages
German (de)
English (en)
Other versions
EP0878008A4 (fr
Inventor
Hans Weedon
Roger Finch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analogic Corp
Original Assignee
Analogic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analogic Corp filed Critical Analogic Corp
Publication of EP0878008A1 publication Critical patent/EP0878008A1/fr
Publication of EP0878008A4 publication Critical patent/EP0878008A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier

Definitions

  • the present invention relates generally to apparatus for resetting the input to a charge-to- voltage converter, and more particularly to such apparatus for use with input signals of very low amplitudes.
  • Digital or computed radiology is a known technique in which X-ray latent images are formed on a special substrate or plate rather than the usual X-ray film.
  • the latent image is scanned with a laser and each image pixel is read out as an electrical charge.
  • the charge on each pixel is typically very small, i.e. , on the order of a few picocoulombs full scale. Accurately reading such small signals requires sensitive equipment and also requires suppression of even very small sources of noise.
  • computed radiology is superior to X-ray films for several reasons.
  • the substrate is typically erasable and reusable, while X-ray film is not.
  • X-ray energy i.e., a peak voltage and maximum milliampere level for powering the X-ray source
  • time duration of each pulse driving the pulsed X-ray source If the parameters of the X-ray exposure are wrong the resulting X-ray image recorded on film tends to be either under or over exposed, because of the mismatch between the X-ray flux and the film dynamic range, resulting in poor diagnostic quality images.
  • computed radiology is that information derived from the latent image formed in the substrate intrinsically can be formed as a digital data file.
  • a fourth advantage of computed radiology is that the X-ray dosage can be reduced because the material used has a higher DQE than that of standard X-ray film.
  • the estimate of X-ray images recorded on film that are so poor as to require the retaking of the image (“recall") is estimated to be around 20% . Radiologists expect this number to go up, because of the poorer training and skills of X-ray technicians.
  • the signals representative of pixels of a latent image on a plate can be digitized over a sufficiently large dynamic range so that one should not have to retake the X-ray image.
  • an exposed X-ray plate is scanned, for example by a laser beam, and each pixel defined area of the plate is read over a time, known as an integration window, of about 30 to 70 ⁇ sec to permit the full charge of the reading to be collected into a charge-to- voltage conversion device.
  • the resulting voltages are then typically converted to digital format for storage, processing and display. Obviously, sequentially reading the typically millions of pixels for each plate into but a single information channel would be unduly time consuming.
  • the voltage generated at the output of the charge-to- voltage conversion device is indicative of the charge stored on that pixel.
  • the charge-to- voltage converter is then "reset” or “cleared” and the next pixel value is then read.
  • prior art systems typically inject a small amount of charge into the charge-to-voltage converter due to the intrinsic capacitance of the switches used in the reset circuitry. The amount of charge injected is small, but is significant compared to the pixel values. Therefore, to accurately read the pixel values from a computed radiology plate, it is important to compensate for the charge that is injected into the charge-to-voltage conversion device by the reset circuitry.
  • Another object of the invention is to provide a charge-to- voltage conversion device that suppresses uncertainty associated with associated reset circuitry.
  • Still another object of the invention is to provide a charge-to- voltage conversion device including compensation circuitry for reducing the effect of charge injection due to the stray capacitance of d e reset circuitry.
  • Yet another object of the invention is to provide a charge-to-voltage conversion device having a capacitive device that matches the temperature profile of the stray capacitance of the reset circuitry.
  • Still ano er object of the invention is to provide a charge-to-voltage conversion device that drives a capacitive load in antiphase with the stray capacitance of the reset circuitry.
  • a charge-to-voltage conversion device that includes a compensation field effect transistor (FET) switch operated in antiphase with the FET switch used in the reset circuitry.
  • the compensation FET has a parasitic capacitance that is related to the parasitic capacitance of the reset FET. Operating the two FET switches in antiphase insures that when one FET is charging the other is discharging.
  • the compensation circuitry can include a potentiometer for adjusting the voltage level of the signal driving the compensation FET. This level adjustment allows the compensation circuitry to compensate for the charge injected by the reset FET as well as other stray capacitances that may be present in the charge-to- voltage conversion device.
  • Figure 1 is a partial schematic, partial block diagram illustrating a prior art charge-to- voltage conversion device
  • Figure 2 is a schematic diagram of an equivalent circuit for the FET reset switch used in the charge-to-voltage conversion device shown in Figure 1
  • Figure 3 is a partial schematic, partial block diagram illustrating a charge-to- voltage conversion device according to the invention
  • Figure 4 is a partial schematic, partial block diagram illustrating a preferred charge-to-voltage conversion device according to the invention
  • Figure 5 is a schematic diagram of an equivalent circuit of the FET compensation switch used in the charge-to-voltage conversion device shown in Figure 4.
  • FIG. 1 shows a computed radiology plate 12 coupled to a set of N identical prior art charge-to- voltage converters 15.
  • Computed radiology plate 12 is typically arranged as a matrix of pixels. In one preferred embodiment plate 12 has approximately 5,000 rows of pixels, and approximately 4,000 columns of pixels. After plate 12 is exposed to X-radiation, each pixel in plate 12 accumulates a charge indicative of the amount of X-radiation that was incident on that pixel. The pixel data is then read out of plate 12 by a set of N information channels, each information channel including one charge-to-voltage converter. Typically, each info ⁇ nation channel is dedicated to reading out a predetermined number of columns of pixel data.
  • FIG. 1 shows the internal structure of the jth conversion device 15-j in detail.
  • Prior art converter 15 includes an integrator exemplified by a well-known integrating operational amplifier 20 having the usual inverting input terminal 22 for receiving the input signal representing me value of each pixel, non-inverting input terminal 24, output terminal 26, integrating capacitor 28 connected in a negative feedback path between terminals 26 and 22, and switch means, such as field effect transistor (FET) reset switch 30, connected in parallel to capacitor 28, wherein the source and drain of switch 30 is connected to opposite sides of the capacitor 28 and the gate is connected to reset control line 52.
  • FET field effect transistor
  • the analog output signal from the latter is preferably converted to digital form by an A/D converter 36, amplifier 34 serving to adjust the voltage to match A/D converter 36.
  • the output of A/D converter 36 is typically digitally filtered and then sent, for example, to a display or communication device (not shown).
  • Post processing components 32, 34, 36 can be shared by all N information channels via a multiplexing arrangement, or alternatively, each information channel may include its own set of post processing components.
  • Inverting input 22 is coupled to computed radiology plate 12, and non-inverting input 24 is coupled to ground.
  • reset switch 30 open (i.e.
  • inverting input 22 is coupled to a single pixel, typically by scanning the pixel with a laser, thus allowing d e charge on that pixel to accumulate on capacitor 28, for a time period known as an integration window.
  • operational amplifier 20 At the end of the integration window, operational amplifier 20 generates at output 26 an analog voltage signal indicative of the charge on the pixel.
  • a controller 50 provides a reset control signal to reset switch 30 via reset control line 52.
  • the controller closes switch 30 (i.e. , low impedance state) to clear the charge stored on capacitor 28. After this reset operation, the controller opens switch 30 so the converter 15 can then read the next pixel value.
  • Controller 50 can be implemented as an appropriately programmed computer, processor, or the like.
  • Prior art converter 15 has a disadvantage associated with me intrinsic gate-to- source capacitance of reset switch 30. Due to this intrinsic capacitance, a transient signal or charge is injected into the node coupled to inverting input 22 whenever reset switch 30 is opened or closed. This injected charge is small, but since the average charge per pixel is also very small, and since the plate 12 is a dense capacitive matrix, the injected charge becomes an important source of uncertainty for prior art converter 15.
  • Figure 2 shows an equivalent circuit of the FET reset switch 30. As shown in Figure 2, for purposes of considering the charge injection caused by the switching of FET switch 30, it is effective to model switch 30 as two capacitors coupled in series, namely, a gate-to-source capacitance 72 and a gate-to-drain capacitance 74.
  • capacitance 72 is approximately equal in value to capacitance 74, and both are typically on the order of one half of one picofarad.
  • converter 50 opens switch 30 at the beginning of an integration window, by applying a high voltage (normally about 5 volts) to the gate of switch 30, a small amount of charge is injected through gate-to-source capacitance 72 to the node coupled to inverting input 22.
  • controller 50 resets converter 15-j by applying a low voltage (normally near zero volts) to the gate of switch 30, gate-to- source capacitance 72 absorbs a small amount of charge from the node coupled to inverting input 22. These charges can be termed collectively, “switching charges”.
  • FIG. 3 shows one embodiment of a charge-to- voltage converter 16 according to the invention which includes circuitry to compensate for the switching charges.
  • a set of N information channels are used to read the data out of plate 12, and each channel includes one charge-to-voltage converter 16.
  • Converter 16 is similar to converter 15 (shown in Figure 1) but additionally contains inverter 54 and capacitor 55.
  • inverter 54 drives one plate of capacitor 55 and the other plate of capacitor 55 is coupled to inverting input 22 of operational amplifier 20.
  • capacitor 55 Since inverter 54 drives capacitor 55 in antiphase from FET reset switch 30, capacitor 55 provides compensation for the switching charges. Since they are driven in antiphase, capacitor 55 is charging whenever gate-to-source capacitance 72 (shown in Figure 2) is discharging, and similarly, capacitor 55 is discharging whenever gate-to- source capacitance 72 is charging. Further, capacitor 55 is chosen to have a value equal to gate-to-source capacitance 72, so capacitor 55 absorbs the same amount of charge that is discharged by capacitance 72 when switch 30 is turned off, and similarly, capacitor 55 discharges the same amount of charge that is absorbed by capacitance 72 when switch 30 is turned on.
  • Capacitor 55 functions as a parasitic capacitance that exactly matches and compensates for the parasitic gate-to-source capacitance 72 of FET switch 30.
  • Charge- to-voltage converter 16 merefore suppresses the uncertainty associated with the switching charges.
  • One problem with converter 16-j is that it is difficult to find a discrete capacitor 55 that exactly matches the gate-to-source capacitance 72 of switch 30. Further, the gate-to-source capacitance 72 varies with temperature and it is even more difficult to find a discrete capacitor 55 that has a temperature profile exactly matching that of gate- to-source capacitance 72.
  • Figure 4 shows a preferred embodiment of a charge-to-voltage converter 17 according to the invention.
  • a set of N information channels are used to read the data out of plate 12, and each channel includes one charge-to-voltage converter 17.
  • Converter 17 is similar to converter 16 (shown in Figure 3) except mat in converter 17, capacitor 55 is replaced with FET 60 and voltage level adjustment device 56.
  • Voltage level adjustment device is implemented as a potentiometer, but could be implemented as any manner of level adjusting device.
  • the output of inverter 54 drives one end of potentiometer 56, the other end of which is grounded.
  • a center tap 58 of potentiometer 56 is connected to the gate of FET 60.
  • the drain and source of FET 60 are coupled togemer and are also coupled to the inverting input 22 of operational amplifier 20.
  • Figure 5 shows the equivalent circuit of FET 60.
  • FET 60 Since the drain and source are coupled together, FET 60 is modeled by a gate-to-source capacitance 76 coupled in parallel with a gate-to-drain capacitance 78. As with FET switch 30, capacitances 76 and 78 are equal and are each on the order of one half of one picofarad. Therefore, FET 60 provides an equivalent capacitance that is twice the gate-to-source capacitance 72 of switch 30. Since FET 60 has twice the capacitance of gate-to-source capacitance 72, FET 60 will only compensate for the switching charges associated with switch 30 if the voltage driving the gate of FET 60 is reduced by a factor of two. Potentiometer 56 is used to reduce the voltage driving the gate of FET 60 to the desired level.
  • the voltage driving the gate of FET 60 should be reduced by a factor of exactly two, however in practice, small deviations from a factor of two are typically desirable to compensate for other intrinsic properties of the circuit, such as other stray capacitances.
  • Potentiometer 56 provides enough flexibility to set the voltage to the ideal level. Since FET 60 and FET 30 are preferably manufactured by identical processes, the temperature profile of the intrinsic capacitance of FET 60 will match the temperamre profile of FET 30. Therefore, FET 60 provides good compensation for the switching charges introduced by FET 30, and converter 17 reduces the uncertainty associated with the switching charges.
  • An alternative embodiment for a charge-to-voltage converter according to die invention is to leave the drain (or source) of FET 60 unconnected and to couple me source (or drain) of FET 60 to inverting input 22, rather than coupling me drain and source together as shown in Figure 4.
  • the capacitance provided by FET 60 equals d e gate-to- source capacitance 72 of FET 30, rather than exceeding capacitance 72 by a factor of two. Since the capacitances are equal, the voltage adjustment provided by potentiometer 56 is unnecessary.
  • converter 17 shown in Figure 4 is preferred precisely because FET 60 provides a capacitance that is larger than the gate-to-source capacitance 72 of FET switch 30.

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  • Analogue/Digital Conversion (AREA)

Abstract

L'invention a trait à un dispositif de conversion charge-tension (17-j) comportant des circuits de compensation destinés à absorber des charges produites par la commutation d'un disjoncteur associé de réenclenchement (30). Les circuits de compensation génèrent une capacité parasite (60) qui compense la capacité intrinsèque du disjoncteur à réenclenchement (30). Ce dernier fait fonctionner les circuits de compensation en opposition de phase et, de ce fait, les circuits de compensation chargent lorsque le disjoncteur décharge et réciproquement. Le système selon l'invention comporte également un dispositif d'ajustement de niveau de tension (56) servant à ajuster le niveau du signal commandant les circuits de compensation.
EP97902877A 1996-01-31 1997-01-13 Circuit de compensation de charge de reenclenchement Withdrawn EP0878008A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US59442596A 1996-01-31 1996-01-31
US594425 1996-01-31
PCT/US1997/000349 WO1997028533A1 (fr) 1996-01-31 1997-01-13 Circuit de compensation de charge de reenclenchement

Publications (2)

Publication Number Publication Date
EP0878008A1 true EP0878008A1 (fr) 1998-11-18
EP0878008A4 EP0878008A4 (fr) 1999-06-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP97902877A Withdrawn EP0878008A4 (fr) 1996-01-31 1997-01-13 Circuit de compensation de charge de reenclenchement

Country Status (3)

Country Link
EP (1) EP0878008A4 (fr)
JP (1) JP2000505927A (fr)
WO (1) WO1997028533A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3758223A1 (fr) * 2019-06-25 2020-12-30 Oxford Instruments Technologies Oy Circuit de préamplificateur

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4451820A (en) * 1981-08-27 1984-05-29 Gte Automatic Electric Incorporated Charge redistribution integratable D/A convertor
EP0616194A1 (fr) * 1993-03-19 1994-09-21 Hamamatsu Photonics K.K. Dispositif de prise de vue à l'état solide

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4163947A (en) * 1977-09-23 1979-08-07 Analogic Corporation Current and voltage autozeroing integrator
JPS55163694A (en) * 1979-06-01 1980-12-19 Fujitsu Ltd Sample holding circuit
US4308468A (en) * 1979-11-15 1981-12-29 Xerox Corporation Dual-FET sample and hold circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4451820A (en) * 1981-08-27 1984-05-29 Gte Automatic Electric Incorporated Charge redistribution integratable D/A convertor
EP0616194A1 (fr) * 1993-03-19 1994-09-21 Hamamatsu Photonics K.K. Dispositif de prise de vue à l'état solide

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO9728533A1 *

Also Published As

Publication number Publication date
JP2000505927A (ja) 2000-05-16
WO1997028533A1 (fr) 1997-08-07
EP0878008A4 (fr) 1999-06-30

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