EP0821460A2 - Source de courant - Google Patents

Source de courant Download PDF

Info

Publication number
EP0821460A2
EP0821460A2 EP97111124A EP97111124A EP0821460A2 EP 0821460 A2 EP0821460 A2 EP 0821460A2 EP 97111124 A EP97111124 A EP 97111124A EP 97111124 A EP97111124 A EP 97111124A EP 0821460 A2 EP0821460 A2 EP 0821460A2
Authority
EP
European Patent Office
Prior art keywords
transistor
current source
switch
constant current
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP97111124A
Other languages
German (de)
English (en)
Other versions
EP0821460A3 (fr
EP0821460B1 (fr
Inventor
Friedbert Riedel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Electrowatt Technology Innovation AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Electrowatt Technology Innovation AG filed Critical Electrowatt Technology Innovation AG
Publication of EP0821460A2 publication Critical patent/EP0821460A2/fr
Publication of EP0821460A3 publication Critical patent/EP0821460A3/fr
Application granted granted Critical
Publication of EP0821460B1 publication Critical patent/EP0821460B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

Definitions

  • the invention relates to a power source of the type mentioned in the preamble of claim 1.
  • Such current sources are suitable for example for the generation of highly constant currents by far Output control range. They are advantageous in operational amplifiers, slope amplifiers, Switched current mode techniques are used for sigma-delta modulators, A / D converters, etc.
  • a power source of the type mentioned in the preamble of claim 1 is known from the article "A High-Swing, High-Impedance MOS Cascode Circuit", IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 289-297, Feb. 1990 by the authors E. Sburginger and W. Guggenbühl. It is this power source a regulated MOS cascode constant current source.
  • the constant current source feeds a load.
  • a Switch either be supplied to the load or switched to ground (U. Tietze and Ch. Schenk, "Semiconductor Circuitry", Springer Verlag, 10th edition, p. 759).
  • the constant current source is therefore always in operation. This leads to a continuous consumption of power loss.
  • At the Switching naturally also changes the potential at the output of the current source from ground to one of the load-dependent value of the potential. This leads to undesirably large on or off current spikes, since when the potential changes, charge shifts in parasitic capacitances occur.
  • the invention has for its object a constant current source with very good switching properties to propose. Another task is to make the power dissipation one for comparatively large ones To keep currents designed constant current source as low as possible.
  • the constant current source 1 shows a constant current source 1 which has a current source transistor T1, a cascode transistor T2 operating as a follower, an amplifier transistor T3, an internal current source 2 and three switches S1, S2 and S3.
  • the transistors T1, T2 and T3 are PMOS transistors, the connections of which, as usual, are referred to as gate, drain or source and which are represented by the symbols customary in the specialist literature.
  • the constant current source 1 is supplied with the operating voltage V dd with respect to the ground m.
  • the transistors T1 and T2 and the load L to be switched are connected in series: the source of the transistor T1 is connected to V dd , the drain of the transistor T1 is connected to the source of the transistor T2.
  • the load L depends on the drain of the transistor T2 and the ground m.
  • the transistor T3 and the current source 2 are also connected in series between the operating voltage V dd and the ground m, the source of the transistor T3 being connected to V dd .
  • a constant voltage is applied to the gate of transistor T1.
  • the gate of the transistor T2 can be connected on the one hand via the switch S3 to the voltage V dd or on the other hand via the switch S1 to the drain of the transistor T3.
  • the drain of transistor T1 can be connected to the gate of transistor T3 via switch S2.
  • the switches S1 and S2 are closed and the switch S3 is open.
  • the amplifier transistor T3, the cascode transistor T2 and the current source 2 form a negative feedback loop in order to regulate the potential at the drain of the current source transistor T1 to a predetermined value that is as constant as possible.
  • a current I p is fed into the load L.
  • the switches S1 and S3 are used to switch the constant current source 1 on and off, during the Switch S2 shortens the settling time when switching on and off.
  • the two switches S1 and S2 are first opened, which breaks the negative feedback loop. Switch S3 is then slightly delayed closed. When the constant current source 1 is switched on, the Switch S3 opened and then switches S1 and S2 closed.
  • the transistor T3 also conducts the constant current source 1 when it is switched off, so that the current I 0 supplied by the internal current source 2 can continue to flow. Without the switch S2, ie with a direct connection between the drain of the transistor T1 and the gate of the transistor T3, the gate of the transistor T3 would be discharged via the transistor T1, so that the transistor T3 blocks and the current I 0 could no longer flow .
  • the non-overlapping switching method ensures that the drain of the transistor T3 is not briefly connected to the potential V dd via the switches S1 and S3.
  • the negative feedback loop stabilizes the potential at the drain of the current source transistor T1 very quickly when the constant current source 1 is switched on, so that the settling time and the switching spikes when the constant current source 1 is switched on become extremely short or small.
  • the gate charge of the transistor T3 is briefly increased by charge injection of its channel feedback capacitances, but this is compensated again due to the reactive effect of the gate-drain channel feedback capacitance of the transistor T3, since the current I 0 always flows through the transistor T3.
  • Constant current source 1 can be implemented using standard CMOS bulk technology.
  • Fig. 1 shows a constant current source 1 realized with PMOS transistors.
  • the Constant current source 1 but without switches S1, S2 and S3, in the version with NMOS Transistors revealed.
  • the switches S1, S2 and S3 can be analogously implemented in this version with NMOS transistors.
  • Such a constant current source 1 can be designed for a current I p , which can be, for example, 10 microamperes or one milliampere.
  • I p a current which can be, for example, 10 microamperes or one milliampere.
  • the power loss is noticeably reduced by switching off.
  • the switches S1 to S3 are analog components with a finite switching time ⁇ .
  • a "H” level is assigned to the "switched on” state of the switches S1 to S3 in FIG. 2, and a “L” level is assigned to the "switched off” state.
  • the switches S1 to S3 for non-overlapping switching are activated, for example, with the 3 shown in the circuit.
  • the circuit has a control input 3 and an output 4 Control of the switches S1 and S2 and an output 5 to control the switch S3.
  • This Circuitry with two NOR gates and one inverter is often used for switched capacitor circuits used and is e.g. from the article "Switched Capacitor Circuit Design", R. Gregorian, K.W. Martin and G.C. Temes, Proc. IEEE, vol. 71, pp. 941-966, Aug. 1983. With additional inverters Between the outputs of the NOR gates and outputs 4 and 5, the duration of the Extend non-overlap between switching.
  • FIG. 4 shows a special embodiment of the constant current source 1 shown in FIG. 1, in which MOS transistors are used as switches S1 to S3.
  • the constant current source 1 has the input 3, via which the switches S1 to S3 are controlled.
  • Switch S1 is an NMOS transistor with a body effect
  • switches S2 and S3 are PMOS switches without a body effect.
  • the switch S2 therefore has its own n-well or is integrated in the n-well of the transistor T2.
  • the gates of switches S1 and S3 are connected directly to input 3, the gate of switch S2 is connected to input 3 via an inverter 6.
  • the current source 2 consists of an NMOS transistor T4, which forms a current mirror with another NMOS transistor T5.
  • the constant voltage at the gate of transistor T1 is generated by means of a PMOS transistor T6.
  • the transistor T5 and the transistor T6 are in turn fed from further current sources 7 and 8 with currents I T5 and I T6 , respectively.
  • the current source 7 is, for example, a PMOS transistor, the gate of which is connected to the gate of the transistor T6.
  • the current I T6 and to a lesser extent the current I T5 influence the settling time of the constant current source 1. They must therefore be chosen large enough to keep the settling time as short as possible.
  • the load L is, for example, a capacitor that is charged as long as there is a pulse at input 3 is present.
  • the pulse lengths of a given number of pulses are simple in this way and add exactly and read out later with a correspondingly expanded circuit arrangement.
  • the constant current source 9 shows a further constant current source 9 with PMOS transistors, in which the current I p flowing to the load L is not switched off, but is redirected.
  • the constant current source 9 in turn has the current source transistor T1 and a negative feedback loop, which is formed by the one of two cascode transistors T2a and T2b arranged in parallel, the amplifier transistor T3 and the current source 2.
  • a first switch S4 connects either the gate of the first cascode transistor T2a or the gate of the second cascode transistor T2b to the potential V dd .
  • the gate of the other cascode transistor T2b or T2a is connected to the drain of transistor T3 by means of a second switch S5.
  • the switches S4 and S5 are switched simultaneously.
  • a load L1 is connected between the drain of the first cascode transistor T2a and the ground m, and a second load L2 is connected between the drain of the second cascode transistor T2b and the ground m.
  • the drain of the first cascode transistor T2a or the drain of the second cascode transistor T2b can also be connected directly to the ground m.
  • the constant current supplied by constant current source 9 thus feeds load L1 as current I pa or load L2 as current I pb .
  • the potential at the drain of the current source transistor T1 is thus permanently regulated to a constant value.
  • the potential at the drain of the current source transistor T1 can change briefly, since the diversity of the loads L1 and L2 generally causes different voltages at the drains of the cascode transistors T2a and T2b, which in turn causes the drain bulk Capacitance of the current source transistor T1 recharges.
  • the currents I pa and I pb therefore have switch-on and switch-off spikes , but these are lower than in the conventional type of switching, where instead of the transistors T2a and T2b only the transistor T2 is present and where a changeover switch either drains the transistor T2 connects to load L1 or to load L2.
  • the settling time of the currents I pa and I pb are roughly comparable to the settling time of the current I p of the constant current source 1 (FIG. 1).
  • the constant current source 9 can also be implemented in an analog manner with NMOS transistors.
  • the switched currents I p or I pa and I pb have current spikes when switching on and off, which are in the order of magnitude of the nominal value of the currents.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Solid-Sorbent Or Filter-Aiding Compositions (AREA)
EP97111124A 1996-07-19 1997-07-03 Source de courant Expired - Lifetime EP0821460B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CH1811/96 1996-07-19
CH181196 1996-07-19
CH181196 1996-07-19

Publications (3)

Publication Number Publication Date
EP0821460A2 true EP0821460A2 (fr) 1998-01-28
EP0821460A3 EP0821460A3 (fr) 1998-04-08
EP0821460B1 EP0821460B1 (fr) 2002-06-19

Family

ID=4219161

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97111124A Expired - Lifetime EP0821460B1 (fr) 1996-07-19 1997-07-03 Source de courant

Country Status (5)

Country Link
EP (1) EP0821460B1 (fr)
AT (1) ATE219610T1 (fr)
CZ (1) CZ223297A3 (fr)
DE (1) DE59707548D1 (fr)
PL (1) PL183356B1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1303047A1 (fr) * 2001-10-09 2003-04-16 Philips Corporate Intellectual Property GmbH Digital source de courant commutable

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0637874A1 (fr) * 1993-08-02 1995-02-08 Siemens Aktiengesellschaft Etage de commutation MOS
EP0722221A2 (fr) * 1995-01-13 1996-07-17 Nec Corporation Circuit commutateur de courant à fonctionnement rapide sans fourniture externe de polarisation de référence

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0637874A1 (fr) * 1993-08-02 1995-02-08 Siemens Aktiengesellschaft Etage de commutation MOS
EP0722221A2 (fr) * 1995-01-13 1996-07-17 Nec Corporation Circuit commutateur de courant à fonctionnement rapide sans fourniture externe de polarisation de référence

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
S[CKINGER ET AL: "a high-swing, high-impedance mos cascode circuit" IEEE JOURNAL OF SOLID STATE CIRCUITS, Bd. 25, Nr. 1, Februar 1990, NEW-YORK, Seiten 289-298, XP000101879 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1303047A1 (fr) * 2001-10-09 2003-04-16 Philips Corporate Intellectual Property GmbH Digital source de courant commutable

Also Published As

Publication number Publication date
CZ223297A3 (cs) 1998-02-18
PL183356B1 (pl) 2002-06-28
EP0821460A3 (fr) 1998-04-08
ATE219610T1 (de) 2002-07-15
PL320932A1 (en) 1998-02-02
EP0821460B1 (fr) 2002-06-19
DE59707548D1 (de) 2002-07-25

Similar Documents

Publication Publication Date Title
DE2555297C2 (de) Digitalschaltung mit Feldeffekttransistoren
DE3740571C2 (de) Schaltungsanordnung zum Einschalt-Rücksetzen von integrierten logischen Schaltungen in MOS-Technik
DE3705140C2 (de) In MOS-Technologie ausgeführte Einschalt-Rückstellschaltung für logische Schaltungsanordnungen, insbesondere für Peripherien von Mikroprozessoren
EP0591750B1 (fr) Méthode pour régler le courant d'un circuit d'attaque de sortie intégré monolithique
DE10128384A1 (de) Ladungspumpenschaltung
DE19637444C2 (de) Eingabeschaltung
DE3228013A1 (de) Treiberschaltung fuer eine sammelleitung
DE102007054519A1 (de) Elektronische Schaltung und zeitlich fortlaufend arbeitender Delta-Sigma-Modulator
WO2007118540A1 (fr) Miroir de courant CMOS rapide
DE102007055419A1 (de) Transistorschalter
DE10207802B4 (de) CMOS-Differenzverstärker
DE60203039T2 (de) Geschaltete Pegelschiebeschaltung in einem Analogschalter
DE2802595C2 (de) Schaltungsanordnung mit Feldeffekttransistoren zur Spannungspegelumsetzung
DE3321553A1 (de) Impulsgenerator als integrierte schaltung
EP1733475A1 (fr) Circuit a generateur d impulsions et dispositif a circuit
DE19949144C1 (de) Digitale Treiberschaltung
EP0022931B1 (fr) Circuit pour convertir des niveaux de tension et procédé à cet effet
DE2835692B2 (de) Binäres logisches ODER-Glied für programmierte logische Anordnungen
EP0821460B1 (fr) Source de courant
DE2552849C3 (de) Logische Schaltung
EP0496910B1 (fr) Montage servant à générer un signal de remise à zéro
EP0009085B1 (fr) Circuit de verrouillage pour séparation des phases et changement de niveau d'un signal d'entrée TTL comportant des transistors à effet de champ et méthode de mise en oeuvre
DE19906860C2 (de) Tristate-Differenz-Ausgangsstufe
EP2182637A1 (fr) Commutation, procédé de commande et d'utilisation d'une commutation pour un mode de repos et un mode de fonctionnement
EP0905598B1 (fr) Circuit source de courant commutable

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT CH DE FR LI SE

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

17P Request for examination filed

Effective date: 19981008

AKX Designation fees paid

Free format text: AT CH DE FR LI SE

RBV Designated contracting states (corrected)

Designated state(s): AT CH DE FR LI SE

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SIEMENS AKTIENGESELLSCHAFT

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

17Q First examination report despatched

Effective date: 20011004

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT CH DE FR LI SE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20020619

REF Corresponds to:

Ref document number: 219610

Country of ref document: AT

Date of ref document: 20020715

Kind code of ref document: T

REG Reference to a national code

Ref country code: CH

Ref legal event code: NV

Representative=s name: SIEMENS SCHWEIZ AG

Ref country code: CH

Ref legal event code: EP

REF Corresponds to:

Ref document number: 59707548

Country of ref document: DE

Date of ref document: 20020725

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20020919

EN Fr: translation not filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20030320

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: AT

Payment date: 20040505

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 20040517

Year of fee payment: 8

REG Reference to a national code

Ref country code: CH

Ref legal event code: PUE

Owner name: LANDIS+GYR GMBH

Free format text: SIEMENS AKTIENGESELLSCHAFT#WITTELSBACHERPLATZ 2#80333 MUENCHEN (DE) -TRANSFER TO- LANDIS+GYR GMBH#HUMBOLDTSTRASSE 64#90459 NUERNBERG (DE)

Ref country code: CH

Ref legal event code: NV

Representative=s name: OK PAT AG PATENTE MARKEN LIZENZEN

REG Reference to a national code

Ref country code: CH

Ref legal event code: NV

Representative=s name: RENTSCH & PARTNER

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050703

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050731

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050731

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20070919

Year of fee payment: 11

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20090203