EP0821460A2 - Current source - Google Patents

Abstract

The current source has a cascode transistor (T2) whose gate is connected via a first switch (S1) to the drain of an amplifier transistor (T3), whose gate is connected via a second switch (S2) to the drain of a current source transistor (T1). The cascode transistor gate is also connected via a third switch (S3), when a PMOS transistor is used, to an operating voltage (Vdd), or, when an NMOS, to earth. In the on state the first and second switches are closed and the third is open. In the off state the first and second switches are open and the third is closed.

Description

The invention relates to a power source of the type mentioned in the preamble of claim 1.

Such current sources are suitable for example for the generation of highly constant currents by far Output control range. They are advantageous in operational amplifiers, slope amplifiers, Switched current mode techniques are used for sigma-delta modulators, A / D converters, etc.

A power source of the type mentioned in the preamble of claim 1 is known from the article "A High-Swing, High-Impedance MOS Cascode Circuit ", IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 289-297, Feb. 1990 by the authors E. Säckinger and W. Guggenbühl. It is this power source a regulated MOS cascode constant current source.

The constant current source feeds a load. To quickly switch the load on and / or off can achieve the current supplied by the constant current source in a known manner by means of a Switch either be supplied to the load or switched to ground (U. Tietze and Ch. Schenk, "Semiconductor Circuitry", Springer Verlag, 10th edition, p. 759). The constant current source is therefore always in operation. This leads to a continuous consumption of power loss. At the Switching naturally also changes the potential at the output of the current source from ground to one of the load-dependent value of the potential. This leads to undesirably large on or off current spikes, since when the potential changes, charge shifts in parasitic capacitances occur.

The invention has for its object a constant current source with very good switching properties to propose. Another task is to make the power dissipation one for comparatively large ones To keep currents designed constant current source as low as possible.

According to the invention, the stated object is achieved by the features of claims 1 and 5.

Exemplary embodiments of the invention are explained in more detail below with reference to the drawing.

Fig. 1

eine mit PMOS Transistoren realisierte, ein- und ausschaltbare Konstantstromquelle,

Fig. 2

ein Zeitdiagramm zur Darstellung des Schaltvorganges,

Fig. 3

eine Schaltungsanordnung zum nichtüberlappenden Schalten von zwei Schaltern,

Fig. 4

die Konstantstromquelle mit als MOS Transistoren ausgebildeten Schaltern und

Fig. 5

eine umschaltbare Konstantstromquelle.

Show it:

Fig. 1

a constant current source realized with PMOS transistors that can be switched on and off,

Fig. 2

1 shows a time diagram to illustrate the switching process,

Fig. 3

a circuit arrangement for the non-overlapping switching of two switches,

Fig. 4

the constant current source with switches designed as MOS transistors and

Fig. 5

a switchable constant current source.

1 shows a constant current source 1 which has a current source transistor T1, a cascode transistor T2 operating as a follower, an amplifier transistor T3, an internal current source 2 and three switches S1, S2 and S3. The transistors T1, T2 and T3 are PMOS transistors, the connections of which, as usual, are referred to as gate, drain or source and which are represented by the symbols customary in the specialist literature. The constant _current source 1 is supplied with the operating voltage V _dd with respect to the ground m.

The transistors T1 and T2 and the load L to be switched are connected in series: the source of the transistor T1 is connected to V _dd , the drain of the transistor T1 is connected to the source of the transistor T2. The load L depends on the drain of the transistor T2 and the ground m. The transistor T3 and the current source 2 are also connected in series between the operating voltage V _dd and the ground m, the source of the transistor T3 being connected to V _dd . A constant voltage is applied to the gate of transistor T1. The gate of the transistor T2 can be connected on the one hand via the switch S3 to the voltage V _dd or on the other hand via the switch S1 to the drain of the transistor T3. The drain of transistor T1 can be connected to the gate of transistor T3 via switch S2.

When the constant current source 1 is switched on, the switches S1 and S2 are closed and the switch S3 is open. In this state, the amplifier transistor T3, the cascode transistor T2 and the current source 2 form a negative feedback loop in order to regulate the potential at the drain of the current source transistor T1 to a predetermined value that is as constant as possible. A current I _{p is} fed into the load L.

When the constant current source 1 is switched off, the switches S1 and S2 are open and the Switch S3 closed. The gate-source capacitance of the transistor T2 is when the Discharge switch S3 very quickly, so that transistor T2 blocks immediately. There is no current in the load L. fed.

The switches S1 and S3 are used to switch the constant current source 1 on and off, during the Switch S2 shortens the settling time when switching on and off.

To switch off the constant current source 1, the two switches S1 and S2 are first opened, which breaks the negative feedback loop. Switch S3 is then slightly delayed closed. When the constant current source 1 is switched on, the Switch S3 opened and then switches S1 and S2 closed.

The transistor T3 also conducts the constant current source 1 when it is switched off, so that the current I ₀ supplied by the internal current source 2 can continue to flow. Without the switch S2, ie with a direct connection between the drain of the transistor T1 and the gate of the transistor T3, the gate of the transistor T3 would be discharged via the transistor T1, so that the transistor T3 blocks and the current I ₀ could no longer flow . The non-overlapping switching method ensures that the drain of the transistor T3 is not briefly connected to the potential V _dd via the switches S1 and S3. Since the operating point of the transistor T3 does not change significantly when switching and the current I ₀ always flows, the negative feedback loop stabilizes the potential at the drain of the current source transistor T1 very quickly when the constant current source 1 is switched on, so that the settling time and the switching spikes when the constant current source 1 is switched on become extremely short or small.

When the switch S2 is opened, the gate charge of the transistor T3 is briefly increased by charge injection of its channel feedback capacitances, but this is compensated again due to the reactive effect of the gate-drain channel feedback capacitance of the transistor T3, since the current I ₀ always flows through the transistor T3.

The use of additional capacitive elements to reduce the charge injection on the gate of the Transistor T3, e.g. in the form of so-called dummy transistors, did not shorten the Settling time.

When switch S1 is closed, the gate-drain channel feedback capacitance inside a very short time of typically one nanosecond a larger current spike in the common Node of the drain of the transistor T3 and the current source 2 injected, but in this period is immediately canceled by the current source 2. The use of dummy transistors is also worthwhile here not for the purely capacitive compensation of the current spikes, since these are the reaction times do not shorten and the settling process is slowed down even without dummy transistors.

Constant current source 1 can be implemented using standard CMOS bulk technology. In the Fig. 1 shows a constant current source 1 realized with PMOS transistors. The is preferred Use of an n-well technology, in which the source-bulk short-circuit of the transistor T2 in a separate n-well is possible, whereby the modulation range of transistor T2 is positive Direction increased. In the above-mentioned article by the authors E. Säckinger and W. Guggenbühl, the Constant current source 1, but without switches S1, S2 and S3, in the version with NMOS Transistors revealed. The switches S1, S2 and S3 can be analogously implemented in this version with NMOS transistors.

Such a constant current source 1 can be designed for a current I _p , which can be, for example, 10 microamperes or one milliampere. In the case of a constant current source 1 designed for comparatively large currents, in which the current I _{p is} significantly greater than the current I ₀ or other internal currents, the power loss is noticeably reduced by switching off.

2 shows the position of the switches S1-S3 and the idealized current I _p as a function of the time t, the constant current source _{1 being} switched off at the time t ₁ and switched on again at the time t ₂ . The switches S1 to S3 are analog components with a finite switching time τ. A "H" level is assigned to the "switched on" state of the switches S1 to S3 in FIG. 2, and a "L" level is assigned to the "switched off" state.

The switches S1 to S3 for non-overlapping switching are activated, for example, with the 3 shown in the circuit. The circuit has a control input 3 and an output 4 Control of the switches S1 and S2 and an output 5 to control the switch S3. This Circuitry with two NOR gates and one inverter is often used for switched capacitor circuits used and is e.g. from the article "Switched Capacitor Circuit Design", R. Gregorian, K.W. Martin and G.C. Temes, Proc. IEEE, vol. 71, pp. 941-966, Aug. 1983. With additional inverters Between the outputs of the NOR gates and outputs 4 and 5, the duration of the Extend non-overlap between switching.

FIG. 4 shows a special embodiment of the constant current source 1 shown in FIG. 1, in which MOS transistors are used as switches S1 to S3. The constant current source 1 has the input 3, via which the switches S1 to S3 are controlled. Switch S1 is an NMOS transistor with a body effect, switches S2 and S3 are PMOS switches without a body effect. The switch S2 therefore has its own n-well or is integrated in the n-well of the transistor T2. The gates of switches S1 and S3 are connected directly to input 3, the gate of switch S2 is connected to input 3 via an inverter 6. If input 3 has a logically high potential, for example potential V _dd , then constant _{current source} 1 is switched on, input 3 has a logically low potential, for example the potential of ground m, then constant current source 1 is switched off. Pulses of the correct polarity arriving at input 3 thus switch on constant current source 1 with their positive edge and switch off again with their negative edge.

When constant current source 1 is switched on, the following happens: At the beginning, the gate of transistor T2 is connected to V _dd , so that the NMOS transistor serving as switch S1 blocks. If the voltage at input 3 reaches the threshold voltage of switch S3, then switch S3 blocks, so that the voltage at the gate of transistor T2 and at the source of switch S1 decreases, and finally switch S1 becomes conductive, ie closes. Switch S1 therefore only switches on when switch S3 is already open. Switch S2 closes by a very small gate delay before switch S1, since switch S2 acts without a body effect. With the body effect of switching S2, the settling time of the current I _p would be longer.

The current source 2 consists of an NMOS transistor T4, which forms a current mirror with another NMOS transistor T5. The constant voltage at the gate of transistor T1 is generated by means of a PMOS transistor T6. The transistor T5 and the transistor T6 are in turn fed from further current sources 7 and 8 with currents I _T5 and I _T6 , respectively. The current source 7 is, for example, a PMOS transistor, the gate of which is connected to the gate of the transistor T6. Above all, the current I _T6 and to a lesser extent the current I _T5 influence the settling time of the constant current _source 1. They must therefore be chosen large enough to keep the settling time as short as possible.

The load L is, for example, a capacitor that is charged as long as there is a pulse at input 3 is present. The pulse lengths of a given number of pulses are simple in this way and add exactly and read out later with a correspondingly expanded circuit arrangement.

5 shows a further constant current source 9 with PMOS transistors, in which the current I _p flowing to the load L is not switched off, but is redirected. The constant current source 9 in turn has the current source transistor T1 and a negative feedback loop, which is formed by the one of two cascode transistors T2a and T2b arranged in parallel, the amplifier transistor T3 and the current source 2. A first switch S4 connects either the gate of the first cascode transistor T2a or the gate of the second cascode transistor T2b to the potential V _dd . The gate of the other cascode transistor T2b or T2a is connected to the drain of transistor T3 by means of a second switch S5. The switches S4 and S5 are switched simultaneously. A load L1 is connected between the drain of the first cascode transistor T2a and the ground m, and a second load L2 is connected between the drain of the second cascode transistor T2b and the ground m. However, the drain of the first cascode transistor T2a or the drain of the second cascode transistor T2b can also be connected directly to the ground m. The constant current supplied by constant current _source 9 thus feeds load L1 as current I _pa or load L2 as current I _pb . The potential at the drain of the current source transistor T1 is thus permanently regulated to a constant value.

During the switching process of the two switches S4 and S5, the potential at the drain of the current source transistor T1 can change briefly, since the diversity of the loads L1 and L2 generally causes different voltages at the drains of the cascode transistors T2a and T2b, which in turn causes the drain bulk Capacitance of the current source transistor T1 recharges. The currents I _pa and I _pb therefore have switch-on and switch-off _spikes , but these are lower than in the conventional type of switching, where instead of the transistors T2a and T2b only the transistor T2 is present and where a changeover switch either drains the transistor T2 connects to load L1 or to load L2. The settling time of the currents I _pa and I _pb are roughly comparable to the settling time of the current I _{p of} the constant current _source 1 (FIG. 1). The constant current source 9 can also be implemented in an analog manner with NMOS transistors.

With constant current sources 1 and 9, settling times of approximately 50 nanoseconds can be achieved when implemented in a 2 µm CMOS bulk technology. The switched currents I _p or I _pa and I _{pb have} current spikes when switching on and off, which are in the order of magnitude of the nominal value of the currents.

Claims (6)

Constant current source (1) for supplying a load (L) with a current (I _p ), the constant current source (1) comprising a current source transistor (T1), a cascode transistor (T2) operating as a follower, an amplifier transistor (T3) and an internal current source ( 2), the current source transistor (T1), the cascode transistor (T2) and the amplifier transistor (T3) being either PMOS or NMOS transistors with a gate, a drain and a source, the current source transistor (T1) and the cascode transistor (T2) are connected in series, the amplifier transistor (T3) and the internal current source (2) being connected in series, the constant current source (1) being supplied with an operating voltage (V _dd ) with respect to ground (m) and the load (L) in the case of PMOS transistors between the drain of the cascode transistor (T2) and the ground (m), in the case of NMOS transistors between the drain of the cascode transistor (T2) and the operating voltage (V _dd ) t, characterized in that the gate of the cascode transistor (T2) by means of a first switch (S1) can be connected to the drain of the amplifier transistor (T3), that the gate of the amplifier transistor (T3) by means of a second switch (S2) to the drain of the Current source transistor (T1) can be connected such that the gate of the cascode transistor (T2) can be connected to the operating voltage (V _dd ) in the case of PMOS transistors or to the ground (m) in the case of PMOS transistors by means of a third switch (S3), that when the constant current source (1) is switched on, the first and the second switch (S1; S2) is closed and the third switch (S3) is open and that in the switched-off state the first and second switches (S1; S2) are open and the third switch (S3) is closed. Constant current source (1) according to claim 1, characterized in that when switching on first the third switch (S3) is opened and then the first and second switches (S1; S2) are closed and that when switching off first the third switch (S3) is closed and then the first and the second switch (S1; S2) are opened. Constant current source (1) according to claim 1 or 2, characterized in that an input (3) for controlling the switches (S1; S2; S3) is provided, that the first switch (S1) is an NMOS transistor and the second and third Switches (S2; S3) are PMOS switches, provided that the transistors (T1; T2; T3) are PMOS transistors, or that the first switch (S1) is a PMOS transistor, the second and third switches (S2; S3) are NMOS If the transistors (T1; T2; T3) are NMOS transistors, the gates of the first and third switches (S1; S3) are connected directly to the input (3) and the gate of the second switch (S2) is connected to the input (3) via an inverter (6). Constant current source (1) according to one of claims 1 to 3, characterized in that the first switch (S1) is a transistor with a body effect and that the second and third switches (S2; S3) are transistors without a body effect. Constant current source (9) for supplying a load (L1) with a current (I _pa ), the constant current source (9) comprising a current source transistor (T1), a first cascode transistor (T2a) operating as a follower, an amplifier transistor (T3) and an internal current source (2), wherein the current source transistor (T1), the cascode transistor (T2a) and the amplifier transistor (T3) are either PMOS or NMOS transistors with a gate, a drain and a source, the current source transistor (T1) and the cascode transistor (T2a ) are connected in series, the amplifier transistor (T3) and the internal current source (2) being connected in series, the constant current source (1) being supplied with an operating voltage (V _dd ) to ground (m) and the load (L1 ) in the case of PMOS transistors between the drain of the cascode transistor (T2a) and the ground (m), in the case of NMOS transistors between the drain of the cascode transistor (T2a) and the operating voltage (V _dd ) is arranged, characterized in that a second cascode transistor (T2b) is connected in parallel to the first cascode transistor (T2a), the drain of which feeds a second load (L2) that by means of a first switch (S4) either the gate of the one cascode transistor (T2a ; T2b) is connected to the operating voltage (V _dd ) in the case of PMOS transistors or to ground (m) in the case of NMOS transistors and that the gate of the other cascode transistor (T2b; T2a) is connected to the by means of a second switch (S5) Drain of the amplifier transistor (T3) is connected. Constant current source (9) according to claim 5, characterized in that the second load (L2) is a short circuit.

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