DE59707548D1 - power source - Google Patents

power source

Info

Publication number
DE59707548D1
DE59707548D1 DE59707548T DE59707548T DE59707548D1 DE 59707548 D1 DE59707548 D1 DE 59707548D1 DE 59707548 T DE59707548 T DE 59707548T DE 59707548 T DE59707548 T DE 59707548T DE 59707548 D1 DE59707548 D1 DE 59707548D1
Authority
DE
Germany
Prior art keywords
transistor
switch
connected via
power source
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE59707548T
Other languages
German (de)
Inventor
Friedbert Riedel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Landis and Gyr GmbH
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of DE59707548D1 publication Critical patent/DE59707548D1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Solid-Sorbent Or Filter-Aiding Compositions (AREA)

Abstract

The current source has a cascode transistor (T2) whose gate is connected via a first switch (S1) to the drain of an amplifier transistor (T3), whose gate is connected via a second switch (S2) to the drain of a current source transistor (T1). The cascode transistor gate is also connected via a third switch (S3), when a PMOS transistor is used, to an operating voltage (Vdd), or, when an NMOS, to earth. In the on state the first and second switches are closed and the third is open. In the off state the first and second switches are open and the third is closed.
DE59707548T 1996-07-19 1997-07-03 power source Expired - Fee Related DE59707548D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH181196 1996-07-19

Publications (1)

Publication Number Publication Date
DE59707548D1 true DE59707548D1 (en) 2002-07-25

Family

ID=4219161

Family Applications (1)

Application Number Title Priority Date Filing Date
DE59707548T Expired - Fee Related DE59707548D1 (en) 1996-07-19 1997-07-03 power source

Country Status (5)

Country Link
EP (1) EP0821460B1 (en)
AT (1) ATE219610T1 (en)
CZ (1) CZ223297A3 (en)
DE (1) DE59707548D1 (en)
PL (1) PL183356B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10149769A1 (en) * 2001-10-09 2003-04-17 Philips Corp Intellectual Pty Digitally switchable power source

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4325899C2 (en) * 1993-08-02 1995-11-16 Siemens Ag MOS switching stage
JP2776285B2 (en) * 1995-01-13 1998-07-16 日本電気株式会社 Current switch circuit

Also Published As

Publication number Publication date
EP0821460A2 (en) 1998-01-28
ATE219610T1 (en) 2002-07-15
PL183356B1 (en) 2002-06-28
EP0821460A3 (en) 1998-04-08
PL320932A1 (en) 1998-02-02
EP0821460B1 (en) 2002-06-19
CZ223297A3 (en) 1998-02-18

Similar Documents

Publication Publication Date Title
DE69119926D1 (en) CMOS clamp circuits
KR910017762A (en) Output circuit
JP2000151378A5 (en)
DE60122722D1 (en) MOS current detection circuit
KR870011616A (en) Sense amplifier
KR920007343A (en) Buffer circuit
KR880001108A (en) CMOS input circuit
EP0570584A4 (en)
KR870006728A (en) BIMOS circuit
KR950007285A (en) Flip-flop amplifier circuit
EP0370814A3 (en) Offset cancel latching comparator
KR940020189A (en) Integrated Circuit with Cascode Current Mirror
KR860003712A (en) Logic Gate Circuit
EP1100200A3 (en) Analog switch including two complementary MOS field-effect transistors
ATE139875T1 (en) CMOS BUFFER CIRCUIT
ATE219610T1 (en) POWER SOURCE
DE602004021198D1 (en) LEVEL CONTROL CIRCUIT, ADJUSTMENT DEVICE AND OPTICAL SWITCH SYSTEM
KR950016002A (en) 3-input buffer circuit
KR910003936A (en) Switching matrix switching element
ATE254338T1 (en) CURRENT CONTROLLED FIELD EFFECT TRANSISTOR
TW326598B (en) Output circuit
KR940026953A (en) Semiconductor memory device
KR890011195A (en) Amplification circuit
KR960027331A (en) Buffer circuit and bias circuit
ATE511133T1 (en) CURRENT LIMITING CIRCUIT

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: LANDIS + GYR GMBH, 90459 NUERNBERG, DE

8339 Ceased/non-payment of the annual fee