EP0764983A3 - Dispositif semi-conducteur et procédé de fabrication - Google Patents

Dispositif semi-conducteur et procédé de fabrication Download PDF

Info

Publication number
EP0764983A3
EP0764983A3 EP96114483A EP96114483A EP0764983A3 EP 0764983 A3 EP0764983 A3 EP 0764983A3 EP 96114483 A EP96114483 A EP 96114483A EP 96114483 A EP96114483 A EP 96114483A EP 0764983 A3 EP0764983 A3 EP 0764983A3
Authority
EP
European Patent Office
Prior art keywords
sacrificial layer
manufacturing
same
semiconductor device
rib
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP96114483A
Other languages
German (de)
English (en)
Other versions
EP0764983A2 (fr
EP0764983B1 (fr
Inventor
Martin Dr. Rer. Nat. Kerber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0764983A2 publication Critical patent/EP0764983A2/fr
Publication of EP0764983A3 publication Critical patent/EP0764983A3/fr
Application granted granted Critical
Publication of EP0764983B1 publication Critical patent/EP0764983B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/765Making of isolation regions between components by field effect

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Junction Field-Effect Transistors (AREA)
EP96114483A 1995-09-19 1996-09-10 Dispositif semi-conducteur et procédé de fabrication Expired - Lifetime EP0764983B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19534784A DE19534784C1 (de) 1995-09-19 1995-09-19 Halbleiter-Schaltungselement und Verfahren zu seiner Herstellung
DE19534784 1995-09-19

Publications (3)

Publication Number Publication Date
EP0764983A2 EP0764983A2 (fr) 1997-03-26
EP0764983A3 true EP0764983A3 (fr) 1997-04-02
EP0764983B1 EP0764983B1 (fr) 2001-11-21

Family

ID=7772598

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96114483A Expired - Lifetime EP0764983B1 (fr) 1995-09-19 1996-09-10 Dispositif semi-conducteur et procédé de fabrication

Country Status (8)

Country Link
US (1) US5962901A (fr)
EP (1) EP0764983B1 (fr)
JP (1) JP3875750B2 (fr)
KR (1) KR100279956B1 (fr)
AT (1) ATE209395T1 (fr)
DE (2) DE19534784C1 (fr)
HK (1) HK1003548A1 (fr)
TW (1) TW353793B (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6368970B1 (en) * 2000-08-24 2002-04-09 Infineon Technologies Ag Semiconductor configuration and corresponding production process
TW200509123A (en) * 2003-08-07 2005-03-01 Matsushita Electric Ind Co Ltd Optical information recording medium and a method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0181501A2 (fr) * 1984-10-18 1986-05-21 Matsushita Electronics Corporation Procédé pour la fabrication d'un circuit intégré MOS complémentaire
DE3942648A1 (de) * 1988-12-24 1990-06-28 Mitsubishi Electric Corp Halbleitervorrichtung und verfahren zur herstellung der halbleitervorrichtung
EP0417715A1 (fr) * 1989-09-11 1991-03-20 Kabushiki Kaisha Toshiba Dispositif semi-conducteur et procédé de fabrication associé
DE4214302A1 (de) * 1991-05-03 1992-11-05 Hyundai Electronics Ind Verfahren zur herstellung einer cmos-struktur mit twin wells

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3724065A (en) * 1970-10-01 1973-04-03 Texas Instruments Inc Fabrication of an insulated gate field effect transistor device
US5190886A (en) * 1984-12-11 1993-03-02 Seiko Epson Corporation Semiconductor device and method of production
JPH0722179B2 (ja) * 1985-12-27 1995-03-08 日本電気株式会社 半導体ウエ−ハの位置合せマ−クの形成方法
US4690730A (en) * 1986-03-07 1987-09-01 Texas Instruments Incorporated Oxide-capped titanium silicide formation
US4893163A (en) * 1988-03-28 1990-01-09 International Business Machines Corporation Alignment mark system for electron beam/optical mixed lithography
JPH0265254A (ja) * 1988-08-31 1990-03-05 Toshiba Corp 半導体装置
US4992394A (en) * 1989-07-31 1991-02-12 At&T Bell Laboratories Self aligned registration marks for integrated circuit fabrication
US5214305A (en) * 1990-08-28 1993-05-25 United Microelectronics Corporation Polycide gate MOSFET for integrated circuits
US5237188A (en) * 1990-11-28 1993-08-17 Kabushiki Kaisha Toshiba Semiconductor device with nitrided gate insulating film
JPH04286361A (ja) * 1991-03-15 1992-10-12 Sony Corp 固体撮像装置
DE69229842T2 (de) * 1991-03-27 2000-04-20 Fujitsu Ltd Halbleiterspeicheranordnung mit einem Dünnschichttransistor und Herstellungsmethode für selben
DE69332006T2 (de) * 1992-03-25 2002-11-28 Texas Instruments Inc Planares Verfahren unter Verwendung von gemeinsamen Ausrichtungsmarken für die Wannenimplantierungen
JP2809253B2 (ja) * 1992-10-02 1998-10-08 富士電機株式会社 注入制御型ショットキーバリア整流素子
US5486715A (en) * 1993-10-15 1996-01-23 Ixys Corporation High frequency MOS device
US5397715A (en) * 1993-10-21 1995-03-14 Micrel, Incorporated MOS transistor having increased gate-drain capacitance
JPH07176639A (ja) * 1993-12-17 1995-07-14 Nec Corp 半導体集積回路装置及びその製造方法
US5455444A (en) * 1994-04-22 1995-10-03 United Microelectronics Corporation Double polysilicon electrostatic discharge protection device for SRAM and DRAM memory devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0181501A2 (fr) * 1984-10-18 1986-05-21 Matsushita Electronics Corporation Procédé pour la fabrication d'un circuit intégré MOS complémentaire
DE3942648A1 (de) * 1988-12-24 1990-06-28 Mitsubishi Electric Corp Halbleitervorrichtung und verfahren zur herstellung der halbleitervorrichtung
EP0417715A1 (fr) * 1989-09-11 1991-03-20 Kabushiki Kaisha Toshiba Dispositif semi-conducteur et procédé de fabrication associé
DE4214302A1 (de) * 1991-05-03 1992-11-05 Hyundai Electronics Ind Verfahren zur herstellung einer cmos-struktur mit twin wells

Also Published As

Publication number Publication date
US5962901A (en) 1999-10-05
KR970018713A (ko) 1997-04-30
DE59608249D1 (de) 2002-01-03
EP0764983A2 (fr) 1997-03-26
DE19534784C1 (de) 1997-04-24
JP3875750B2 (ja) 2007-01-31
JPH09129836A (ja) 1997-05-16
HK1003548A1 (en) 1998-10-30
ATE209395T1 (de) 2001-12-15
TW353793B (en) 1999-03-01
EP0764983B1 (fr) 2001-11-21
KR100279956B1 (ko) 2001-02-01

Similar Documents

Publication Publication Date Title
AU2003301057A1 (en) Methods of forming semiconductor mesa structures including self-aligned contact layers and related devices
MY134849A (en) Laser annealing method and semiconductor device fabricating method
TW363276B (en) Thin-film semiconductor device, thin-film transistor and method for fabricating the same
EP0363689A3 (fr) Fabrication de dispositifs semi-conducteurs utilisant la croissance épitaxiale sélective et le dépôt de poly-Si dans le même appareil
DE69118031D1 (de) Verfahren zum Herstellen einer Halbleiteranordnung mit einer Ausrichtungsmarke
TW328147B (en) Semiconductor device fabrication
EP0797245A3 (fr) Méthode de fabrication d'un dispositif semi-conducteur MOS vertical
DE69109366T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit Gatestruktur.
JPS57176772A (en) Semiconductor device and manufacture thereof
EP1246258A4 (fr) Dispositif semi-conducteur, son procede de fabrication et dispositif de traitement de l'information
WO2003003452A3 (fr) Composant semi-conducteur et son procede de fabrication
EP0899782A3 (fr) Méthode de fabrication d'un transistor à effet de champ
EP0884774A3 (fr) Méthode de fabrication d'un dispositif semi-conducteur comportant une rainure d'isolation
EP0380682A4 (en) Method of fabricating semiconductor devices
DE3585115D1 (de) Verfahren zur herstellung und einstellung von eingegrabenen schichten.
EP0397148A3 (fr) Dispositif à hétérostructure et procédé pour sa fabrication
EP0764983A3 (fr) Dispositif semi-conducteur et procédé de fabrication
SE8306071D0 (sv) Sett att bilda kiseldioxid
EP0984535A3 (fr) Laser semi-conducteur comportant un réseau
EP0373221A4 (en) Fabrication method for semiconductor device and film formation apparatus for said method
TW326557B (en) Fabrication method of bipolar transistor employs a series of fabrication processes so that the ion can be implanted independently in a coupling area and an elementary area.
JPS57211775A (en) Semiconductor device and manufacture thereof
KR960009100B1 (en) Manufacturing method of minute contact hole for highly integrated device
TW325583B (en) Method of etching a polysilicon layer
TW345701B (en) Semiconductor production process capable of preventing the disappearance of alignment mark after chemical mechanical polishing

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT DE FR GB IE IT NL

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT DE FR GB IE IT NL

17P Request for examination filed

Effective date: 19970505

17Q First examination report despatched

Effective date: 19990826

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT DE FR GB IE IT NL

REF Corresponds to:

Ref document number: 209395

Country of ref document: AT

Date of ref document: 20011215

Kind code of ref document: T

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: GERMAN

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

REF Corresponds to:

Ref document number: 59608249

Country of ref document: DE

Date of ref document: 20020103

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 20020129

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 20050914

Year of fee payment: 10

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: AT

Payment date: 20050919

Year of fee payment: 10

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060910

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20060921

Year of fee payment: 11

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20070401

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 20070401

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IE

Payment date: 20070924

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20070925

Year of fee payment: 12

Ref country code: DE

Payment date: 20071113

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20070914

Year of fee payment: 12

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20070910

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20070910

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20090529

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080910

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080910

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20090401

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080930